i2s.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // ALSA SoC Audio Layer - Samsung I2S Controller driver
  4. //
  5. // Copyright (c) 2010 Samsung Electronics Co. Ltd.
  6. // Jaswinder Singh <[email protected]>
  7. #include <dt-bindings/sound/samsung-i2s.h>
  8. #include <linux/delay.h>
  9. #include <linux/slab.h>
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/pm_runtime.h>
  18. #include <sound/soc.h>
  19. #include <sound/pcm_params.h>
  20. #include <linux/platform_data/asoc-s3c.h>
  21. #include "dma.h"
  22. #include "idma.h"
  23. #include "i2s.h"
  24. #include "i2s-regs.h"
  25. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  26. #define SAMSUNG_I2S_ID_PRIMARY 1
  27. #define SAMSUNG_I2S_ID_SECONDARY 2
  28. struct samsung_i2s_variant_regs {
  29. unsigned int bfs_off;
  30. unsigned int rfs_off;
  31. unsigned int sdf_off;
  32. unsigned int txr_off;
  33. unsigned int rclksrc_off;
  34. unsigned int mss_off;
  35. unsigned int cdclkcon_off;
  36. unsigned int lrp_off;
  37. unsigned int bfs_mask;
  38. unsigned int rfs_mask;
  39. unsigned int ftx0cnt_off;
  40. };
  41. struct samsung_i2s_dai_data {
  42. u32 quirks;
  43. unsigned int pcm_rates;
  44. const struct samsung_i2s_variant_regs *i2s_variant_regs;
  45. };
  46. struct i2s_dai {
  47. /* Platform device for this DAI */
  48. struct platform_device *pdev;
  49. /* Frame clock */
  50. unsigned frmclk;
  51. /*
  52. * Specifically requested RCLK, BCLK by machine driver.
  53. * 0 indicates CPU driver is free to choose any value.
  54. */
  55. unsigned rfs, bfs;
  56. /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
  57. struct i2s_dai *pri_dai;
  58. /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
  59. struct i2s_dai *sec_dai;
  60. #define DAI_OPENED (1 << 0) /* DAI is opened */
  61. #define DAI_MANAGER (1 << 1) /* DAI is the manager */
  62. unsigned mode;
  63. /* Driver for this DAI */
  64. struct snd_soc_dai_driver *drv;
  65. /* DMA parameters */
  66. struct snd_dmaengine_dai_dma_data dma_playback;
  67. struct snd_dmaengine_dai_dma_data dma_capture;
  68. struct snd_dmaengine_dai_dma_data idma_playback;
  69. dma_filter_fn filter;
  70. struct samsung_i2s_priv *priv;
  71. };
  72. struct samsung_i2s_priv {
  73. struct platform_device *pdev;
  74. struct platform_device *pdev_sec;
  75. /* Lock for cross interface checks */
  76. spinlock_t pcm_lock;
  77. /* CPU DAIs and their corresponding drivers */
  78. struct i2s_dai *dai;
  79. struct snd_soc_dai_driver *dai_drv;
  80. int num_dais;
  81. /* The I2S controller's core clock */
  82. struct clk *clk;
  83. /* Clock for generating I2S signals */
  84. struct clk *op_clk;
  85. /* Rate of RCLK source clock */
  86. unsigned long rclk_srcrate;
  87. /* Cache of selected I2S registers for system suspend */
  88. u32 suspend_i2smod;
  89. u32 suspend_i2scon;
  90. u32 suspend_i2spsr;
  91. const struct samsung_i2s_variant_regs *variant_regs;
  92. u32 quirks;
  93. /* The clock provider's data */
  94. struct clk *clk_table[3];
  95. struct clk_onecell_data clk_data;
  96. /* Spinlock protecting member fields below */
  97. spinlock_t lock;
  98. /* Memory mapped SFR region */
  99. void __iomem *addr;
  100. /* A flag indicating the I2S slave mode operation */
  101. bool slave_mode;
  102. };
  103. /* Returns true if this is the 'overlay' stereo DAI */
  104. static inline bool is_secondary(struct i2s_dai *i2s)
  105. {
  106. return i2s->drv->id == SAMSUNG_I2S_ID_SECONDARY;
  107. }
  108. /* If this interface of the controller is transmitting data */
  109. static inline bool tx_active(struct i2s_dai *i2s)
  110. {
  111. u32 active;
  112. if (!i2s)
  113. return false;
  114. active = readl(i2s->priv->addr + I2SCON);
  115. if (is_secondary(i2s))
  116. active &= CON_TXSDMA_ACTIVE;
  117. else
  118. active &= CON_TXDMA_ACTIVE;
  119. return active ? true : false;
  120. }
  121. /* Return pointer to the other DAI */
  122. static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
  123. {
  124. return i2s->pri_dai ? : i2s->sec_dai;
  125. }
  126. /* If the other interface of the controller is transmitting data */
  127. static inline bool other_tx_active(struct i2s_dai *i2s)
  128. {
  129. struct i2s_dai *other = get_other_dai(i2s);
  130. return tx_active(other);
  131. }
  132. /* If any interface of the controller is transmitting data */
  133. static inline bool any_tx_active(struct i2s_dai *i2s)
  134. {
  135. return tx_active(i2s) || other_tx_active(i2s);
  136. }
  137. /* If this interface of the controller is receiving data */
  138. static inline bool rx_active(struct i2s_dai *i2s)
  139. {
  140. u32 active;
  141. if (!i2s)
  142. return false;
  143. active = readl(i2s->priv->addr + I2SCON) & CON_RXDMA_ACTIVE;
  144. return active ? true : false;
  145. }
  146. /* If the other interface of the controller is receiving data */
  147. static inline bool other_rx_active(struct i2s_dai *i2s)
  148. {
  149. struct i2s_dai *other = get_other_dai(i2s);
  150. return rx_active(other);
  151. }
  152. /* If any interface of the controller is receiving data */
  153. static inline bool any_rx_active(struct i2s_dai *i2s)
  154. {
  155. return rx_active(i2s) || other_rx_active(i2s);
  156. }
  157. /* If the other DAI is transmitting or receiving data */
  158. static inline bool other_active(struct i2s_dai *i2s)
  159. {
  160. return other_rx_active(i2s) || other_tx_active(i2s);
  161. }
  162. /* If this DAI is transmitting or receiving data */
  163. static inline bool this_active(struct i2s_dai *i2s)
  164. {
  165. return tx_active(i2s) || rx_active(i2s);
  166. }
  167. /* If the controller is active anyway */
  168. static inline bool any_active(struct i2s_dai *i2s)
  169. {
  170. return this_active(i2s) || other_active(i2s);
  171. }
  172. static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
  173. {
  174. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  175. return &priv->dai[dai->id - 1];
  176. }
  177. static inline bool is_opened(struct i2s_dai *i2s)
  178. {
  179. if (i2s && (i2s->mode & DAI_OPENED))
  180. return true;
  181. else
  182. return false;
  183. }
  184. static inline bool is_manager(struct i2s_dai *i2s)
  185. {
  186. if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
  187. return true;
  188. else
  189. return false;
  190. }
  191. /* Read RCLK of I2S (in multiples of LRCLK) */
  192. static inline unsigned get_rfs(struct i2s_dai *i2s)
  193. {
  194. struct samsung_i2s_priv *priv = i2s->priv;
  195. u32 rfs;
  196. rfs = readl(priv->addr + I2SMOD) >> priv->variant_regs->rfs_off;
  197. rfs &= priv->variant_regs->rfs_mask;
  198. switch (rfs) {
  199. case 7: return 192;
  200. case 6: return 96;
  201. case 5: return 128;
  202. case 4: return 64;
  203. case 3: return 768;
  204. case 2: return 384;
  205. case 1: return 512;
  206. default: return 256;
  207. }
  208. }
  209. /* Write RCLK of I2S (in multiples of LRCLK) */
  210. static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
  211. {
  212. struct samsung_i2s_priv *priv = i2s->priv;
  213. u32 mod = readl(priv->addr + I2SMOD);
  214. int rfs_shift = priv->variant_regs->rfs_off;
  215. mod &= ~(priv->variant_regs->rfs_mask << rfs_shift);
  216. switch (rfs) {
  217. case 192:
  218. mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
  219. break;
  220. case 96:
  221. mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
  222. break;
  223. case 128:
  224. mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
  225. break;
  226. case 64:
  227. mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
  228. break;
  229. case 768:
  230. mod |= (MOD_RCLK_768FS << rfs_shift);
  231. break;
  232. case 512:
  233. mod |= (MOD_RCLK_512FS << rfs_shift);
  234. break;
  235. case 384:
  236. mod |= (MOD_RCLK_384FS << rfs_shift);
  237. break;
  238. default:
  239. mod |= (MOD_RCLK_256FS << rfs_shift);
  240. break;
  241. }
  242. writel(mod, priv->addr + I2SMOD);
  243. }
  244. /* Read bit-clock of I2S (in multiples of LRCLK) */
  245. static inline unsigned get_bfs(struct i2s_dai *i2s)
  246. {
  247. struct samsung_i2s_priv *priv = i2s->priv;
  248. u32 bfs;
  249. bfs = readl(priv->addr + I2SMOD) >> priv->variant_regs->bfs_off;
  250. bfs &= priv->variant_regs->bfs_mask;
  251. switch (bfs) {
  252. case 8: return 256;
  253. case 7: return 192;
  254. case 6: return 128;
  255. case 5: return 96;
  256. case 4: return 64;
  257. case 3: return 24;
  258. case 2: return 16;
  259. case 1: return 48;
  260. default: return 32;
  261. }
  262. }
  263. /* Write bit-clock of I2S (in multiples of LRCLK) */
  264. static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
  265. {
  266. struct samsung_i2s_priv *priv = i2s->priv;
  267. u32 mod = readl(priv->addr + I2SMOD);
  268. int tdm = priv->quirks & QUIRK_SUPPORTS_TDM;
  269. int bfs_shift = priv->variant_regs->bfs_off;
  270. /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
  271. if (!tdm && bfs > 48) {
  272. dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
  273. return;
  274. }
  275. mod &= ~(priv->variant_regs->bfs_mask << bfs_shift);
  276. switch (bfs) {
  277. case 48:
  278. mod |= (MOD_BCLK_48FS << bfs_shift);
  279. break;
  280. case 32:
  281. mod |= (MOD_BCLK_32FS << bfs_shift);
  282. break;
  283. case 24:
  284. mod |= (MOD_BCLK_24FS << bfs_shift);
  285. break;
  286. case 16:
  287. mod |= (MOD_BCLK_16FS << bfs_shift);
  288. break;
  289. case 64:
  290. mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
  291. break;
  292. case 96:
  293. mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
  294. break;
  295. case 128:
  296. mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
  297. break;
  298. case 192:
  299. mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
  300. break;
  301. case 256:
  302. mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
  303. break;
  304. default:
  305. dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
  306. return;
  307. }
  308. writel(mod, priv->addr + I2SMOD);
  309. }
  310. /* Sample size */
  311. static inline int get_blc(struct i2s_dai *i2s)
  312. {
  313. int blc = readl(i2s->priv->addr + I2SMOD);
  314. blc = (blc >> 13) & 0x3;
  315. switch (blc) {
  316. case 2: return 24;
  317. case 1: return 8;
  318. default: return 16;
  319. }
  320. }
  321. /* TX channel control */
  322. static void i2s_txctrl(struct i2s_dai *i2s, int on)
  323. {
  324. struct samsung_i2s_priv *priv = i2s->priv;
  325. void __iomem *addr = priv->addr;
  326. int txr_off = priv->variant_regs->txr_off;
  327. u32 con = readl(addr + I2SCON);
  328. u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
  329. if (on) {
  330. con |= CON_ACTIVE;
  331. con &= ~CON_TXCH_PAUSE;
  332. if (is_secondary(i2s)) {
  333. con |= CON_TXSDMA_ACTIVE;
  334. con &= ~CON_TXSDMA_PAUSE;
  335. } else {
  336. con |= CON_TXDMA_ACTIVE;
  337. con &= ~CON_TXDMA_PAUSE;
  338. }
  339. if (any_rx_active(i2s))
  340. mod |= 2 << txr_off;
  341. else
  342. mod |= 0 << txr_off;
  343. } else {
  344. if (is_secondary(i2s)) {
  345. con |= CON_TXSDMA_PAUSE;
  346. con &= ~CON_TXSDMA_ACTIVE;
  347. } else {
  348. con |= CON_TXDMA_PAUSE;
  349. con &= ~CON_TXDMA_ACTIVE;
  350. }
  351. if (other_tx_active(i2s)) {
  352. writel(con, addr + I2SCON);
  353. return;
  354. }
  355. con |= CON_TXCH_PAUSE;
  356. if (any_rx_active(i2s))
  357. mod |= 1 << txr_off;
  358. else
  359. con &= ~CON_ACTIVE;
  360. }
  361. writel(mod, addr + I2SMOD);
  362. writel(con, addr + I2SCON);
  363. }
  364. /* RX Channel Control */
  365. static void i2s_rxctrl(struct i2s_dai *i2s, int on)
  366. {
  367. struct samsung_i2s_priv *priv = i2s->priv;
  368. void __iomem *addr = priv->addr;
  369. int txr_off = priv->variant_regs->txr_off;
  370. u32 con = readl(addr + I2SCON);
  371. u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
  372. if (on) {
  373. con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
  374. con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
  375. if (any_tx_active(i2s))
  376. mod |= 2 << txr_off;
  377. else
  378. mod |= 1 << txr_off;
  379. } else {
  380. con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
  381. con &= ~CON_RXDMA_ACTIVE;
  382. if (any_tx_active(i2s))
  383. mod |= 0 << txr_off;
  384. else
  385. con &= ~CON_ACTIVE;
  386. }
  387. writel(mod, addr + I2SMOD);
  388. writel(con, addr + I2SCON);
  389. }
  390. /* Flush FIFO of an interface */
  391. static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
  392. {
  393. void __iomem *fic;
  394. u32 val;
  395. if (!i2s)
  396. return;
  397. if (is_secondary(i2s))
  398. fic = i2s->priv->addr + I2SFICS;
  399. else
  400. fic = i2s->priv->addr + I2SFIC;
  401. /* Flush the FIFO */
  402. writel(readl(fic) | flush, fic);
  403. /* Be patient */
  404. val = msecs_to_loops(1) / 1000; /* 1 usec */
  405. while (--val)
  406. cpu_relax();
  407. writel(readl(fic) & ~flush, fic);
  408. }
  409. static int i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int rfs,
  410. int dir)
  411. {
  412. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  413. struct i2s_dai *i2s = to_info(dai);
  414. struct i2s_dai *other = get_other_dai(i2s);
  415. const struct samsung_i2s_variant_regs *i2s_regs = priv->variant_regs;
  416. unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
  417. unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
  418. u32 mod, mask, val = 0;
  419. unsigned long flags;
  420. int ret = 0;
  421. pm_runtime_get_sync(dai->dev);
  422. spin_lock_irqsave(&priv->lock, flags);
  423. mod = readl(priv->addr + I2SMOD);
  424. spin_unlock_irqrestore(&priv->lock, flags);
  425. switch (clk_id) {
  426. case SAMSUNG_I2S_OPCLK:
  427. mask = MOD_OPCLK_MASK;
  428. val = (dir << MOD_OPCLK_SHIFT) & MOD_OPCLK_MASK;
  429. break;
  430. case SAMSUNG_I2S_CDCLK:
  431. mask = 1 << i2s_regs->cdclkcon_off;
  432. /* Shouldn't matter in GATING(CLOCK_IN) mode */
  433. if (dir == SND_SOC_CLOCK_IN)
  434. rfs = 0;
  435. if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
  436. (any_active(i2s) &&
  437. (((dir == SND_SOC_CLOCK_IN)
  438. && !(mod & cdcon_mask)) ||
  439. ((dir == SND_SOC_CLOCK_OUT)
  440. && (mod & cdcon_mask))))) {
  441. dev_err(&i2s->pdev->dev,
  442. "%s:%d Other DAI busy\n", __func__, __LINE__);
  443. ret = -EAGAIN;
  444. goto err;
  445. }
  446. if (dir == SND_SOC_CLOCK_IN)
  447. val = 1 << i2s_regs->cdclkcon_off;
  448. i2s->rfs = rfs;
  449. break;
  450. case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
  451. case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
  452. mask = 1 << i2s_regs->rclksrc_off;
  453. if ((priv->quirks & QUIRK_NO_MUXPSR)
  454. || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
  455. clk_id = 0;
  456. else
  457. clk_id = 1;
  458. if (!any_active(i2s)) {
  459. if (priv->op_clk && !IS_ERR(priv->op_clk)) {
  460. if ((clk_id && !(mod & rsrc_mask)) ||
  461. (!clk_id && (mod & rsrc_mask))) {
  462. clk_disable_unprepare(priv->op_clk);
  463. clk_put(priv->op_clk);
  464. } else {
  465. priv->rclk_srcrate =
  466. clk_get_rate(priv->op_clk);
  467. goto done;
  468. }
  469. }
  470. if (clk_id)
  471. priv->op_clk = clk_get(&i2s->pdev->dev,
  472. "i2s_opclk1");
  473. else
  474. priv->op_clk = clk_get(&i2s->pdev->dev,
  475. "i2s_opclk0");
  476. if (WARN_ON(IS_ERR(priv->op_clk))) {
  477. ret = PTR_ERR(priv->op_clk);
  478. priv->op_clk = NULL;
  479. goto err;
  480. }
  481. ret = clk_prepare_enable(priv->op_clk);
  482. if (ret) {
  483. clk_put(priv->op_clk);
  484. priv->op_clk = NULL;
  485. goto err;
  486. }
  487. priv->rclk_srcrate = clk_get_rate(priv->op_clk);
  488. } else if ((!clk_id && (mod & rsrc_mask))
  489. || (clk_id && !(mod & rsrc_mask))) {
  490. dev_err(&i2s->pdev->dev,
  491. "%s:%d Other DAI busy\n", __func__, __LINE__);
  492. ret = -EAGAIN;
  493. goto err;
  494. } else {
  495. /* Call can't be on the active DAI */
  496. goto done;
  497. }
  498. if (clk_id == 1)
  499. val = 1 << i2s_regs->rclksrc_off;
  500. break;
  501. default:
  502. dev_err(&i2s->pdev->dev, "We don't serve that!\n");
  503. ret = -EINVAL;
  504. goto err;
  505. }
  506. spin_lock_irqsave(&priv->lock, flags);
  507. mod = readl(priv->addr + I2SMOD);
  508. mod = (mod & ~mask) | val;
  509. writel(mod, priv->addr + I2SMOD);
  510. spin_unlock_irqrestore(&priv->lock, flags);
  511. done:
  512. pm_runtime_put(dai->dev);
  513. return 0;
  514. err:
  515. pm_runtime_put(dai->dev);
  516. return ret;
  517. }
  518. static int i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  519. {
  520. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  521. struct i2s_dai *i2s = to_info(dai);
  522. int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
  523. u32 mod, tmp = 0;
  524. unsigned long flags;
  525. lrp_shift = priv->variant_regs->lrp_off;
  526. sdf_shift = priv->variant_regs->sdf_off;
  527. mod_slave = 1 << priv->variant_regs->mss_off;
  528. sdf_mask = MOD_SDF_MASK << sdf_shift;
  529. lrp_rlow = MOD_LR_RLOW << lrp_shift;
  530. /* Format is priority */
  531. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  532. case SND_SOC_DAIFMT_RIGHT_J:
  533. tmp |= lrp_rlow;
  534. tmp |= (MOD_SDF_MSB << sdf_shift);
  535. break;
  536. case SND_SOC_DAIFMT_LEFT_J:
  537. tmp |= lrp_rlow;
  538. tmp |= (MOD_SDF_LSB << sdf_shift);
  539. break;
  540. case SND_SOC_DAIFMT_I2S:
  541. tmp |= (MOD_SDF_IIS << sdf_shift);
  542. break;
  543. default:
  544. dev_err(&i2s->pdev->dev, "Format not supported\n");
  545. return -EINVAL;
  546. }
  547. /*
  548. * INV flag is relative to the FORMAT flag - if set it simply
  549. * flips the polarity specified by the Standard
  550. */
  551. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  552. case SND_SOC_DAIFMT_NB_NF:
  553. break;
  554. case SND_SOC_DAIFMT_NB_IF:
  555. if (tmp & lrp_rlow)
  556. tmp &= ~lrp_rlow;
  557. else
  558. tmp |= lrp_rlow;
  559. break;
  560. default:
  561. dev_err(&i2s->pdev->dev, "Polarity not supported\n");
  562. return -EINVAL;
  563. }
  564. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  565. case SND_SOC_DAIFMT_BC_FC:
  566. tmp |= mod_slave;
  567. break;
  568. case SND_SOC_DAIFMT_BP_FP:
  569. /*
  570. * Set default source clock in Master mode, only when the
  571. * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
  572. * clock configuration assigned in DT is not overwritten.
  573. */
  574. if (priv->rclk_srcrate == 0 && priv->clk_data.clks == NULL)
  575. i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
  576. 0, SND_SOC_CLOCK_IN);
  577. break;
  578. default:
  579. dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
  580. return -EINVAL;
  581. }
  582. pm_runtime_get_sync(dai->dev);
  583. spin_lock_irqsave(&priv->lock, flags);
  584. mod = readl(priv->addr + I2SMOD);
  585. /*
  586. * Don't change the I2S mode if any controller is active on this
  587. * channel.
  588. */
  589. if (any_active(i2s) &&
  590. ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
  591. spin_unlock_irqrestore(&priv->lock, flags);
  592. pm_runtime_put(dai->dev);
  593. dev_err(&i2s->pdev->dev,
  594. "%s:%d Other DAI busy\n", __func__, __LINE__);
  595. return -EAGAIN;
  596. }
  597. mod &= ~(sdf_mask | lrp_rlow | mod_slave);
  598. mod |= tmp;
  599. writel(mod, priv->addr + I2SMOD);
  600. priv->slave_mode = (mod & mod_slave);
  601. spin_unlock_irqrestore(&priv->lock, flags);
  602. pm_runtime_put(dai->dev);
  603. return 0;
  604. }
  605. static int i2s_hw_params(struct snd_pcm_substream *substream,
  606. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  607. {
  608. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  609. struct i2s_dai *i2s = to_info(dai);
  610. u32 mod, mask = 0, val = 0;
  611. struct clk *rclksrc;
  612. unsigned long flags;
  613. WARN_ON(!pm_runtime_active(dai->dev));
  614. if (!is_secondary(i2s))
  615. mask |= (MOD_DC2_EN | MOD_DC1_EN);
  616. switch (params_channels(params)) {
  617. case 6:
  618. val |= MOD_DC2_EN;
  619. fallthrough;
  620. case 4:
  621. val |= MOD_DC1_EN;
  622. break;
  623. case 2:
  624. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  625. i2s->dma_playback.addr_width = 4;
  626. else
  627. i2s->dma_capture.addr_width = 4;
  628. break;
  629. case 1:
  630. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  631. i2s->dma_playback.addr_width = 2;
  632. else
  633. i2s->dma_capture.addr_width = 2;
  634. break;
  635. default:
  636. dev_err(&i2s->pdev->dev, "%d channels not supported\n",
  637. params_channels(params));
  638. return -EINVAL;
  639. }
  640. if (is_secondary(i2s))
  641. mask |= MOD_BLCS_MASK;
  642. else
  643. mask |= MOD_BLCP_MASK;
  644. if (is_manager(i2s))
  645. mask |= MOD_BLC_MASK;
  646. switch (params_width(params)) {
  647. case 8:
  648. if (is_secondary(i2s))
  649. val |= MOD_BLCS_8BIT;
  650. else
  651. val |= MOD_BLCP_8BIT;
  652. if (is_manager(i2s))
  653. val |= MOD_BLC_8BIT;
  654. break;
  655. case 16:
  656. if (is_secondary(i2s))
  657. val |= MOD_BLCS_16BIT;
  658. else
  659. val |= MOD_BLCP_16BIT;
  660. if (is_manager(i2s))
  661. val |= MOD_BLC_16BIT;
  662. break;
  663. case 24:
  664. if (is_secondary(i2s))
  665. val |= MOD_BLCS_24BIT;
  666. else
  667. val |= MOD_BLCP_24BIT;
  668. if (is_manager(i2s))
  669. val |= MOD_BLC_24BIT;
  670. break;
  671. default:
  672. dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
  673. params_format(params));
  674. return -EINVAL;
  675. }
  676. spin_lock_irqsave(&priv->lock, flags);
  677. mod = readl(priv->addr + I2SMOD);
  678. mod = (mod & ~mask) | val;
  679. writel(mod, priv->addr + I2SMOD);
  680. spin_unlock_irqrestore(&priv->lock, flags);
  681. snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
  682. i2s->frmclk = params_rate(params);
  683. rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC];
  684. if (rclksrc && !IS_ERR(rclksrc))
  685. priv->rclk_srcrate = clk_get_rate(rclksrc);
  686. return 0;
  687. }
  688. /* We set constraints on the substream according to the version of I2S */
  689. static int i2s_startup(struct snd_pcm_substream *substream,
  690. struct snd_soc_dai *dai)
  691. {
  692. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  693. struct i2s_dai *i2s = to_info(dai);
  694. struct i2s_dai *other = get_other_dai(i2s);
  695. unsigned long flags;
  696. pm_runtime_get_sync(dai->dev);
  697. spin_lock_irqsave(&priv->pcm_lock, flags);
  698. i2s->mode |= DAI_OPENED;
  699. if (is_manager(other))
  700. i2s->mode &= ~DAI_MANAGER;
  701. else
  702. i2s->mode |= DAI_MANAGER;
  703. if (!any_active(i2s) && (priv->quirks & QUIRK_NEED_RSTCLR))
  704. writel(CON_RSTCLR, i2s->priv->addr + I2SCON);
  705. spin_unlock_irqrestore(&priv->pcm_lock, flags);
  706. return 0;
  707. }
  708. static void i2s_shutdown(struct snd_pcm_substream *substream,
  709. struct snd_soc_dai *dai)
  710. {
  711. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  712. struct i2s_dai *i2s = to_info(dai);
  713. struct i2s_dai *other = get_other_dai(i2s);
  714. unsigned long flags;
  715. spin_lock_irqsave(&priv->pcm_lock, flags);
  716. i2s->mode &= ~DAI_OPENED;
  717. i2s->mode &= ~DAI_MANAGER;
  718. if (is_opened(other))
  719. other->mode |= DAI_MANAGER;
  720. /* Reset any constraint on RFS and BFS */
  721. i2s->rfs = 0;
  722. i2s->bfs = 0;
  723. spin_unlock_irqrestore(&priv->pcm_lock, flags);
  724. pm_runtime_put(dai->dev);
  725. }
  726. static int config_setup(struct i2s_dai *i2s)
  727. {
  728. struct samsung_i2s_priv *priv = i2s->priv;
  729. struct i2s_dai *other = get_other_dai(i2s);
  730. unsigned rfs, bfs, blc;
  731. u32 psr;
  732. blc = get_blc(i2s);
  733. bfs = i2s->bfs;
  734. if (!bfs && other)
  735. bfs = other->bfs;
  736. /* Select least possible multiple(2) if no constraint set */
  737. if (!bfs)
  738. bfs = blc * 2;
  739. rfs = i2s->rfs;
  740. if (!rfs && other)
  741. rfs = other->rfs;
  742. if ((rfs == 256 || rfs == 512) && (blc == 24)) {
  743. dev_err(&i2s->pdev->dev,
  744. "%d-RFS not supported for 24-blc\n", rfs);
  745. return -EINVAL;
  746. }
  747. if (!rfs) {
  748. if (bfs == 16 || bfs == 32)
  749. rfs = 256;
  750. else
  751. rfs = 384;
  752. }
  753. /* If already setup and running */
  754. if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
  755. dev_err(&i2s->pdev->dev,
  756. "%s:%d Other DAI busy\n", __func__, __LINE__);
  757. return -EAGAIN;
  758. }
  759. set_bfs(i2s, bfs);
  760. set_rfs(i2s, rfs);
  761. /* Don't bother with PSR in Slave mode */
  762. if (priv->slave_mode)
  763. return 0;
  764. if (!(priv->quirks & QUIRK_NO_MUXPSR)) {
  765. psr = priv->rclk_srcrate / i2s->frmclk / rfs;
  766. writel(((psr - 1) << 8) | PSR_PSREN, priv->addr + I2SPSR);
  767. dev_dbg(&i2s->pdev->dev,
  768. "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
  769. priv->rclk_srcrate, psr, rfs, bfs);
  770. }
  771. return 0;
  772. }
  773. static int i2s_trigger(struct snd_pcm_substream *substream,
  774. int cmd, struct snd_soc_dai *dai)
  775. {
  776. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  777. int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
  778. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  779. struct i2s_dai *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
  780. unsigned long flags;
  781. switch (cmd) {
  782. case SNDRV_PCM_TRIGGER_START:
  783. case SNDRV_PCM_TRIGGER_RESUME:
  784. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  785. pm_runtime_get_sync(dai->dev);
  786. spin_lock_irqsave(&priv->lock, flags);
  787. if (config_setup(i2s)) {
  788. spin_unlock_irqrestore(&priv->lock, flags);
  789. return -EINVAL;
  790. }
  791. if (capture)
  792. i2s_rxctrl(i2s, 1);
  793. else
  794. i2s_txctrl(i2s, 1);
  795. spin_unlock_irqrestore(&priv->lock, flags);
  796. break;
  797. case SNDRV_PCM_TRIGGER_STOP:
  798. case SNDRV_PCM_TRIGGER_SUSPEND:
  799. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  800. spin_lock_irqsave(&priv->lock, flags);
  801. if (capture) {
  802. i2s_rxctrl(i2s, 0);
  803. i2s_fifo(i2s, FIC_RXFLUSH);
  804. } else {
  805. i2s_txctrl(i2s, 0);
  806. i2s_fifo(i2s, FIC_TXFLUSH);
  807. }
  808. spin_unlock_irqrestore(&priv->lock, flags);
  809. pm_runtime_put(dai->dev);
  810. break;
  811. }
  812. return 0;
  813. }
  814. static int i2s_set_clkdiv(struct snd_soc_dai *dai,
  815. int div_id, int div)
  816. {
  817. struct i2s_dai *i2s = to_info(dai);
  818. struct i2s_dai *other = get_other_dai(i2s);
  819. switch (div_id) {
  820. case SAMSUNG_I2S_DIV_BCLK:
  821. pm_runtime_get_sync(dai->dev);
  822. if ((any_active(i2s) && div && (get_bfs(i2s) != div))
  823. || (other && other->bfs && (other->bfs != div))) {
  824. pm_runtime_put(dai->dev);
  825. dev_err(&i2s->pdev->dev,
  826. "%s:%d Other DAI busy\n", __func__, __LINE__);
  827. return -EAGAIN;
  828. }
  829. i2s->bfs = div;
  830. pm_runtime_put(dai->dev);
  831. break;
  832. default:
  833. dev_err(&i2s->pdev->dev,
  834. "Invalid clock divider(%d)\n", div_id);
  835. return -EINVAL;
  836. }
  837. return 0;
  838. }
  839. static snd_pcm_sframes_t
  840. i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
  841. {
  842. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  843. struct i2s_dai *i2s = to_info(dai);
  844. u32 reg = readl(priv->addr + I2SFIC);
  845. snd_pcm_sframes_t delay;
  846. WARN_ON(!pm_runtime_active(dai->dev));
  847. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  848. delay = FIC_RXCOUNT(reg);
  849. else if (is_secondary(i2s))
  850. delay = FICS_TXCOUNT(readl(priv->addr + I2SFICS));
  851. else
  852. delay = (reg >> priv->variant_regs->ftx0cnt_off) & 0x7f;
  853. return delay;
  854. }
  855. #ifdef CONFIG_PM
  856. static int i2s_suspend(struct snd_soc_component *component)
  857. {
  858. return pm_runtime_force_suspend(component->dev);
  859. }
  860. static int i2s_resume(struct snd_soc_component *component)
  861. {
  862. return pm_runtime_force_resume(component->dev);
  863. }
  864. #else
  865. #define i2s_suspend NULL
  866. #define i2s_resume NULL
  867. #endif
  868. static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
  869. {
  870. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  871. struct i2s_dai *i2s = to_info(dai);
  872. struct i2s_dai *other = get_other_dai(i2s);
  873. unsigned long flags;
  874. pm_runtime_get_sync(dai->dev);
  875. if (is_secondary(i2s)) {
  876. /* If this is probe on the secondary DAI */
  877. snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, NULL);
  878. } else {
  879. snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
  880. &i2s->dma_capture);
  881. if (priv->quirks & QUIRK_NEED_RSTCLR)
  882. writel(CON_RSTCLR, priv->addr + I2SCON);
  883. if (priv->quirks & QUIRK_SUPPORTS_IDMA)
  884. idma_reg_addr_init(priv->addr,
  885. other->idma_playback.addr);
  886. }
  887. /* Reset any constraint on RFS and BFS */
  888. i2s->rfs = 0;
  889. i2s->bfs = 0;
  890. spin_lock_irqsave(&priv->lock, flags);
  891. i2s_txctrl(i2s, 0);
  892. i2s_rxctrl(i2s, 0);
  893. i2s_fifo(i2s, FIC_TXFLUSH);
  894. i2s_fifo(other, FIC_TXFLUSH);
  895. i2s_fifo(i2s, FIC_RXFLUSH);
  896. spin_unlock_irqrestore(&priv->lock, flags);
  897. /* Gate CDCLK by default */
  898. if (!is_opened(other))
  899. i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
  900. 0, SND_SOC_CLOCK_IN);
  901. pm_runtime_put(dai->dev);
  902. return 0;
  903. }
  904. static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
  905. {
  906. struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
  907. struct i2s_dai *i2s = to_info(dai);
  908. unsigned long flags;
  909. pm_runtime_get_sync(dai->dev);
  910. if (!is_secondary(i2s)) {
  911. if (priv->quirks & QUIRK_NEED_RSTCLR) {
  912. spin_lock_irqsave(&priv->lock, flags);
  913. writel(0, priv->addr + I2SCON);
  914. spin_unlock_irqrestore(&priv->lock, flags);
  915. }
  916. }
  917. pm_runtime_put(dai->dev);
  918. return 0;
  919. }
  920. static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
  921. .trigger = i2s_trigger,
  922. .hw_params = i2s_hw_params,
  923. .set_fmt = i2s_set_fmt,
  924. .set_clkdiv = i2s_set_clkdiv,
  925. .set_sysclk = i2s_set_sysclk,
  926. .startup = i2s_startup,
  927. .shutdown = i2s_shutdown,
  928. .delay = i2s_delay,
  929. };
  930. static const struct snd_soc_dapm_widget samsung_i2s_widgets[] = {
  931. /* Backend DAI */
  932. SND_SOC_DAPM_AIF_OUT("Mixer DAI TX", NULL, 0, SND_SOC_NOPM, 0, 0),
  933. SND_SOC_DAPM_AIF_IN("Mixer DAI RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  934. /* Playback Mixer */
  935. SND_SOC_DAPM_MIXER("Playback Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  936. };
  937. static const struct snd_soc_dapm_route samsung_i2s_dapm_routes[] = {
  938. { "Playback Mixer", NULL, "Primary Playback" },
  939. { "Playback Mixer", NULL, "Secondary Playback" },
  940. { "Mixer DAI TX", NULL, "Playback Mixer" },
  941. { "Primary Capture", NULL, "Mixer DAI RX" },
  942. };
  943. static const struct snd_soc_component_driver samsung_i2s_component = {
  944. .name = "samsung-i2s",
  945. .dapm_widgets = samsung_i2s_widgets,
  946. .num_dapm_widgets = ARRAY_SIZE(samsung_i2s_widgets),
  947. .dapm_routes = samsung_i2s_dapm_routes,
  948. .num_dapm_routes = ARRAY_SIZE(samsung_i2s_dapm_routes),
  949. .suspend = i2s_suspend,
  950. .resume = i2s_resume,
  951. .legacy_dai_naming = 1,
  952. };
  953. #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  954. SNDRV_PCM_FMTBIT_S24_LE)
  955. static int i2s_alloc_dais(struct samsung_i2s_priv *priv,
  956. const struct samsung_i2s_dai_data *i2s_dai_data,
  957. int num_dais)
  958. {
  959. static const char *dai_names[] = { "samsung-i2s", "samsung-i2s-sec" };
  960. static const char *stream_names[] = { "Primary Playback",
  961. "Secondary Playback" };
  962. struct snd_soc_dai_driver *dai_drv;
  963. int i;
  964. priv->dai = devm_kcalloc(&priv->pdev->dev, num_dais,
  965. sizeof(struct i2s_dai), GFP_KERNEL);
  966. if (!priv->dai)
  967. return -ENOMEM;
  968. priv->dai_drv = devm_kcalloc(&priv->pdev->dev, num_dais,
  969. sizeof(*dai_drv), GFP_KERNEL);
  970. if (!priv->dai_drv)
  971. return -ENOMEM;
  972. for (i = 0; i < num_dais; i++) {
  973. dai_drv = &priv->dai_drv[i];
  974. dai_drv->probe = samsung_i2s_dai_probe;
  975. dai_drv->remove = samsung_i2s_dai_remove;
  976. dai_drv->symmetric_rate = 1;
  977. dai_drv->ops = &samsung_i2s_dai_ops;
  978. dai_drv->playback.channels_min = 1;
  979. dai_drv->playback.channels_max = 2;
  980. dai_drv->playback.rates = i2s_dai_data->pcm_rates;
  981. dai_drv->playback.formats = SAMSUNG_I2S_FMTS;
  982. dai_drv->playback.stream_name = stream_names[i];
  983. dai_drv->id = i + 1;
  984. dai_drv->name = dai_names[i];
  985. priv->dai[i].drv = &priv->dai_drv[i];
  986. priv->dai[i].pdev = priv->pdev;
  987. }
  988. /* Initialize capture only for the primary DAI */
  989. dai_drv = &priv->dai_drv[SAMSUNG_I2S_ID_PRIMARY - 1];
  990. dai_drv->capture.channels_min = 1;
  991. dai_drv->capture.channels_max = 2;
  992. dai_drv->capture.rates = i2s_dai_data->pcm_rates;
  993. dai_drv->capture.formats = SAMSUNG_I2S_FMTS;
  994. dai_drv->capture.stream_name = "Primary Capture";
  995. return 0;
  996. }
  997. #ifdef CONFIG_PM
  998. static int i2s_runtime_suspend(struct device *dev)
  999. {
  1000. struct samsung_i2s_priv *priv = dev_get_drvdata(dev);
  1001. priv->suspend_i2smod = readl(priv->addr + I2SMOD);
  1002. priv->suspend_i2scon = readl(priv->addr + I2SCON);
  1003. priv->suspend_i2spsr = readl(priv->addr + I2SPSR);
  1004. clk_disable_unprepare(priv->op_clk);
  1005. clk_disable_unprepare(priv->clk);
  1006. return 0;
  1007. }
  1008. static int i2s_runtime_resume(struct device *dev)
  1009. {
  1010. struct samsung_i2s_priv *priv = dev_get_drvdata(dev);
  1011. int ret;
  1012. ret = clk_prepare_enable(priv->clk);
  1013. if (ret)
  1014. return ret;
  1015. if (priv->op_clk) {
  1016. ret = clk_prepare_enable(priv->op_clk);
  1017. if (ret) {
  1018. clk_disable_unprepare(priv->clk);
  1019. return ret;
  1020. }
  1021. }
  1022. writel(priv->suspend_i2scon, priv->addr + I2SCON);
  1023. writel(priv->suspend_i2smod, priv->addr + I2SMOD);
  1024. writel(priv->suspend_i2spsr, priv->addr + I2SPSR);
  1025. return 0;
  1026. }
  1027. #endif /* CONFIG_PM */
  1028. static void i2s_unregister_clocks(struct samsung_i2s_priv *priv)
  1029. {
  1030. int i;
  1031. for (i = 0; i < priv->clk_data.clk_num; i++) {
  1032. if (!IS_ERR(priv->clk_table[i]))
  1033. clk_unregister(priv->clk_table[i]);
  1034. }
  1035. }
  1036. static void i2s_unregister_clock_provider(struct samsung_i2s_priv *priv)
  1037. {
  1038. of_clk_del_provider(priv->pdev->dev.of_node);
  1039. i2s_unregister_clocks(priv);
  1040. }
  1041. static int i2s_register_clock_provider(struct samsung_i2s_priv *priv)
  1042. {
  1043. const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" };
  1044. const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
  1045. const char *p_names[2] = { NULL };
  1046. struct device *dev = &priv->pdev->dev;
  1047. const struct samsung_i2s_variant_regs *reg_info = priv->variant_regs;
  1048. const char *i2s_clk_name[ARRAY_SIZE(i2s_clk_desc)];
  1049. struct clk *rclksrc;
  1050. int ret, i;
  1051. /* Register the clock provider only if it's expected in the DTB */
  1052. if (!of_find_property(dev->of_node, "#clock-cells", NULL))
  1053. return 0;
  1054. /* Get the RCLKSRC mux clock parent clock names */
  1055. for (i = 0; i < ARRAY_SIZE(p_names); i++) {
  1056. rclksrc = clk_get(dev, clk_name[i]);
  1057. if (IS_ERR(rclksrc))
  1058. continue;
  1059. p_names[i] = __clk_get_name(rclksrc);
  1060. clk_put(rclksrc);
  1061. }
  1062. for (i = 0; i < ARRAY_SIZE(i2s_clk_desc); i++) {
  1063. i2s_clk_name[i] = devm_kasprintf(dev, GFP_KERNEL, "%s_%s",
  1064. dev_name(dev), i2s_clk_desc[i]);
  1065. if (!i2s_clk_name[i])
  1066. return -ENOMEM;
  1067. }
  1068. if (!(priv->quirks & QUIRK_NO_MUXPSR)) {
  1069. /* Activate the prescaler */
  1070. u32 val = readl(priv->addr + I2SPSR);
  1071. writel(val | PSR_PSREN, priv->addr + I2SPSR);
  1072. priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
  1073. i2s_clk_name[CLK_I2S_RCLK_SRC], p_names,
  1074. ARRAY_SIZE(p_names),
  1075. CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
  1076. priv->addr + I2SMOD, reg_info->rclksrc_off,
  1077. 1, 0, &priv->lock);
  1078. priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
  1079. i2s_clk_name[CLK_I2S_RCLK_PSR],
  1080. i2s_clk_name[CLK_I2S_RCLK_SRC],
  1081. CLK_SET_RATE_PARENT,
  1082. priv->addr + I2SPSR, 8, 6, 0, &priv->lock);
  1083. p_names[0] = i2s_clk_name[CLK_I2S_RCLK_PSR];
  1084. priv->clk_data.clk_num = 2;
  1085. }
  1086. priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev,
  1087. i2s_clk_name[CLK_I2S_CDCLK], p_names[0],
  1088. CLK_SET_RATE_PARENT,
  1089. priv->addr + I2SMOD, reg_info->cdclkcon_off,
  1090. CLK_GATE_SET_TO_DISABLE, &priv->lock);
  1091. priv->clk_data.clk_num += 1;
  1092. priv->clk_data.clks = priv->clk_table;
  1093. ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
  1094. &priv->clk_data);
  1095. if (ret < 0) {
  1096. dev_err(dev, "failed to add clock provider: %d\n", ret);
  1097. i2s_unregister_clocks(priv);
  1098. }
  1099. return ret;
  1100. }
  1101. /* Create platform device for the secondary PCM */
  1102. static int i2s_create_secondary_device(struct samsung_i2s_priv *priv)
  1103. {
  1104. struct platform_device *pdev_sec;
  1105. const char *devname;
  1106. int ret;
  1107. devname = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, "%s-sec",
  1108. dev_name(&priv->pdev->dev));
  1109. if (!devname)
  1110. return -ENOMEM;
  1111. pdev_sec = platform_device_alloc(devname, -1);
  1112. if (!pdev_sec)
  1113. return -ENOMEM;
  1114. pdev_sec->driver_override = kstrdup("samsung-i2s", GFP_KERNEL);
  1115. if (!pdev_sec->driver_override) {
  1116. platform_device_put(pdev_sec);
  1117. return -ENOMEM;
  1118. }
  1119. ret = platform_device_add(pdev_sec);
  1120. if (ret < 0) {
  1121. platform_device_put(pdev_sec);
  1122. return ret;
  1123. }
  1124. ret = device_attach(&pdev_sec->dev);
  1125. if (ret <= 0) {
  1126. platform_device_unregister(priv->pdev_sec);
  1127. dev_info(&pdev_sec->dev, "device_attach() failed\n");
  1128. return ret;
  1129. }
  1130. priv->pdev_sec = pdev_sec;
  1131. return 0;
  1132. }
  1133. static void i2s_delete_secondary_device(struct samsung_i2s_priv *priv)
  1134. {
  1135. platform_device_unregister(priv->pdev_sec);
  1136. priv->pdev_sec = NULL;
  1137. }
  1138. static int samsung_i2s_probe(struct platform_device *pdev)
  1139. {
  1140. struct i2s_dai *pri_dai, *sec_dai = NULL;
  1141. struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
  1142. u32 regs_base, idma_addr = 0;
  1143. struct device_node *np = pdev->dev.of_node;
  1144. const struct samsung_i2s_dai_data *i2s_dai_data;
  1145. const struct platform_device_id *id;
  1146. struct samsung_i2s_priv *priv;
  1147. struct resource *res;
  1148. int num_dais, ret;
  1149. if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
  1150. i2s_dai_data = of_device_get_match_data(&pdev->dev);
  1151. } else {
  1152. id = platform_get_device_id(pdev);
  1153. /* Nothing to do if it is the secondary device probe */
  1154. if (!id)
  1155. return 0;
  1156. i2s_dai_data = (struct samsung_i2s_dai_data *)id->driver_data;
  1157. }
  1158. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  1159. if (!priv)
  1160. return -ENOMEM;
  1161. if (np) {
  1162. priv->quirks = i2s_dai_data->quirks;
  1163. } else {
  1164. if (!i2s_pdata) {
  1165. dev_err(&pdev->dev, "Missing platform data\n");
  1166. return -EINVAL;
  1167. }
  1168. priv->quirks = i2s_pdata->type.quirks;
  1169. }
  1170. num_dais = (priv->quirks & QUIRK_SEC_DAI) ? 2 : 1;
  1171. priv->pdev = pdev;
  1172. priv->variant_regs = i2s_dai_data->i2s_variant_regs;
  1173. ret = i2s_alloc_dais(priv, i2s_dai_data, num_dais);
  1174. if (ret < 0)
  1175. return ret;
  1176. pri_dai = &priv->dai[SAMSUNG_I2S_ID_PRIMARY - 1];
  1177. spin_lock_init(&priv->lock);
  1178. spin_lock_init(&priv->pcm_lock);
  1179. if (!np) {
  1180. pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
  1181. pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
  1182. pri_dai->filter = i2s_pdata->dma_filter;
  1183. idma_addr = i2s_pdata->type.idma_addr;
  1184. } else {
  1185. if (of_property_read_u32(np, "samsung,idma-addr",
  1186. &idma_addr)) {
  1187. if (priv->quirks & QUIRK_SUPPORTS_IDMA) {
  1188. dev_info(&pdev->dev, "idma address is not"\
  1189. "specified");
  1190. }
  1191. }
  1192. }
  1193. priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  1194. if (IS_ERR(priv->addr))
  1195. return PTR_ERR(priv->addr);
  1196. regs_base = res->start;
  1197. priv->clk = devm_clk_get(&pdev->dev, "iis");
  1198. if (IS_ERR(priv->clk)) {
  1199. dev_err(&pdev->dev, "Failed to get iis clock\n");
  1200. return PTR_ERR(priv->clk);
  1201. }
  1202. ret = clk_prepare_enable(priv->clk);
  1203. if (ret != 0) {
  1204. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  1205. return ret;
  1206. }
  1207. pri_dai->dma_playback.addr = regs_base + I2STXD;
  1208. pri_dai->dma_capture.addr = regs_base + I2SRXD;
  1209. pri_dai->dma_playback.chan_name = "tx";
  1210. pri_dai->dma_capture.chan_name = "rx";
  1211. pri_dai->dma_playback.addr_width = 4;
  1212. pri_dai->dma_capture.addr_width = 4;
  1213. pri_dai->priv = priv;
  1214. if (priv->quirks & QUIRK_PRI_6CHAN)
  1215. pri_dai->drv->playback.channels_max = 6;
  1216. ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
  1217. "tx", "rx", NULL);
  1218. if (ret < 0)
  1219. goto err_disable_clk;
  1220. if (priv->quirks & QUIRK_SEC_DAI) {
  1221. sec_dai = &priv->dai[SAMSUNG_I2S_ID_SECONDARY - 1];
  1222. sec_dai->dma_playback.addr = regs_base + I2STXDS;
  1223. sec_dai->dma_playback.chan_name = "tx-sec";
  1224. if (!np) {
  1225. sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
  1226. sec_dai->filter = i2s_pdata->dma_filter;
  1227. }
  1228. sec_dai->dma_playback.addr_width = 4;
  1229. sec_dai->idma_playback.addr = idma_addr;
  1230. sec_dai->pri_dai = pri_dai;
  1231. sec_dai->priv = priv;
  1232. pri_dai->sec_dai = sec_dai;
  1233. ret = i2s_create_secondary_device(priv);
  1234. if (ret < 0)
  1235. goto err_disable_clk;
  1236. ret = samsung_asoc_dma_platform_register(&priv->pdev_sec->dev,
  1237. sec_dai->filter, "tx-sec", NULL,
  1238. &pdev->dev);
  1239. if (ret < 0)
  1240. goto err_del_sec;
  1241. }
  1242. if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
  1243. dev_err(&pdev->dev, "Unable to configure gpio\n");
  1244. ret = -EINVAL;
  1245. goto err_del_sec;
  1246. }
  1247. dev_set_drvdata(&pdev->dev, priv);
  1248. ret = devm_snd_soc_register_component(&pdev->dev,
  1249. &samsung_i2s_component,
  1250. priv->dai_drv, num_dais);
  1251. if (ret < 0)
  1252. goto err_del_sec;
  1253. pm_runtime_set_active(&pdev->dev);
  1254. pm_runtime_enable(&pdev->dev);
  1255. ret = i2s_register_clock_provider(priv);
  1256. if (ret < 0)
  1257. goto err_disable_pm;
  1258. priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]);
  1259. return 0;
  1260. err_disable_pm:
  1261. pm_runtime_disable(&pdev->dev);
  1262. err_del_sec:
  1263. i2s_delete_secondary_device(priv);
  1264. err_disable_clk:
  1265. clk_disable_unprepare(priv->clk);
  1266. return ret;
  1267. }
  1268. static int samsung_i2s_remove(struct platform_device *pdev)
  1269. {
  1270. struct samsung_i2s_priv *priv = dev_get_drvdata(&pdev->dev);
  1271. /* The secondary device has no driver data assigned */
  1272. if (!priv)
  1273. return 0;
  1274. pm_runtime_get_sync(&pdev->dev);
  1275. pm_runtime_disable(&pdev->dev);
  1276. i2s_unregister_clock_provider(priv);
  1277. i2s_delete_secondary_device(priv);
  1278. clk_disable_unprepare(priv->clk);
  1279. pm_runtime_put_noidle(&pdev->dev);
  1280. return 0;
  1281. }
  1282. static const struct samsung_i2s_variant_regs i2sv3_regs = {
  1283. .bfs_off = 1,
  1284. .rfs_off = 3,
  1285. .sdf_off = 5,
  1286. .txr_off = 8,
  1287. .rclksrc_off = 10,
  1288. .mss_off = 11,
  1289. .cdclkcon_off = 12,
  1290. .lrp_off = 7,
  1291. .bfs_mask = 0x3,
  1292. .rfs_mask = 0x3,
  1293. .ftx0cnt_off = 8,
  1294. };
  1295. static const struct samsung_i2s_variant_regs i2sv6_regs = {
  1296. .bfs_off = 0,
  1297. .rfs_off = 4,
  1298. .sdf_off = 6,
  1299. .txr_off = 8,
  1300. .rclksrc_off = 10,
  1301. .mss_off = 11,
  1302. .cdclkcon_off = 12,
  1303. .lrp_off = 15,
  1304. .bfs_mask = 0xf,
  1305. .rfs_mask = 0x3,
  1306. .ftx0cnt_off = 8,
  1307. };
  1308. static const struct samsung_i2s_variant_regs i2sv7_regs = {
  1309. .bfs_off = 0,
  1310. .rfs_off = 4,
  1311. .sdf_off = 7,
  1312. .txr_off = 9,
  1313. .rclksrc_off = 11,
  1314. .mss_off = 12,
  1315. .cdclkcon_off = 22,
  1316. .lrp_off = 15,
  1317. .bfs_mask = 0xf,
  1318. .rfs_mask = 0x7,
  1319. .ftx0cnt_off = 0,
  1320. };
  1321. static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
  1322. .bfs_off = 0,
  1323. .rfs_off = 3,
  1324. .sdf_off = 6,
  1325. .txr_off = 8,
  1326. .rclksrc_off = 10,
  1327. .mss_off = 11,
  1328. .cdclkcon_off = 12,
  1329. .lrp_off = 15,
  1330. .bfs_mask = 0x7,
  1331. .rfs_mask = 0x7,
  1332. .ftx0cnt_off = 8,
  1333. };
  1334. static const struct samsung_i2s_dai_data i2sv3_dai_type = {
  1335. .quirks = QUIRK_NO_MUXPSR,
  1336. .pcm_rates = SNDRV_PCM_RATE_8000_96000,
  1337. .i2s_variant_regs = &i2sv3_regs,
  1338. };
  1339. static const struct samsung_i2s_dai_data i2sv5_dai_type __maybe_unused = {
  1340. .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
  1341. QUIRK_SUPPORTS_IDMA,
  1342. .pcm_rates = SNDRV_PCM_RATE_8000_96000,
  1343. .i2s_variant_regs = &i2sv3_regs,
  1344. };
  1345. static const struct samsung_i2s_dai_data i2sv6_dai_type __maybe_unused = {
  1346. .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
  1347. QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
  1348. .pcm_rates = SNDRV_PCM_RATE_8000_96000,
  1349. .i2s_variant_regs = &i2sv6_regs,
  1350. };
  1351. static const struct samsung_i2s_dai_data i2sv7_dai_type __maybe_unused = {
  1352. .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
  1353. QUIRK_SUPPORTS_TDM,
  1354. .pcm_rates = SNDRV_PCM_RATE_8000_192000,
  1355. .i2s_variant_regs = &i2sv7_regs,
  1356. };
  1357. static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 __maybe_unused = {
  1358. .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
  1359. .pcm_rates = SNDRV_PCM_RATE_8000_96000,
  1360. .i2s_variant_regs = &i2sv5_i2s1_regs,
  1361. };
  1362. static const struct platform_device_id samsung_i2s_driver_ids[] = {
  1363. {
  1364. .name = "samsung-i2s",
  1365. .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
  1366. },
  1367. {},
  1368. };
  1369. MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
  1370. #ifdef CONFIG_OF
  1371. static const struct of_device_id exynos_i2s_match[] = {
  1372. {
  1373. .compatible = "samsung,s3c6410-i2s",
  1374. .data = &i2sv3_dai_type,
  1375. }, {
  1376. .compatible = "samsung,s5pv210-i2s",
  1377. .data = &i2sv5_dai_type,
  1378. }, {
  1379. .compatible = "samsung,exynos5420-i2s",
  1380. .data = &i2sv6_dai_type,
  1381. }, {
  1382. .compatible = "samsung,exynos7-i2s",
  1383. .data = &i2sv7_dai_type,
  1384. }, {
  1385. .compatible = "samsung,exynos7-i2s1",
  1386. .data = &i2sv5_dai_type_i2s1,
  1387. },
  1388. {},
  1389. };
  1390. MODULE_DEVICE_TABLE(of, exynos_i2s_match);
  1391. #endif
  1392. static const struct dev_pm_ops samsung_i2s_pm = {
  1393. SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
  1394. i2s_runtime_resume, NULL)
  1395. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1396. pm_runtime_force_resume)
  1397. };
  1398. static struct platform_driver samsung_i2s_driver = {
  1399. .probe = samsung_i2s_probe,
  1400. .remove = samsung_i2s_remove,
  1401. .id_table = samsung_i2s_driver_ids,
  1402. .driver = {
  1403. .name = "samsung-i2s",
  1404. .of_match_table = of_match_ptr(exynos_i2s_match),
  1405. .pm = &samsung_i2s_pm,
  1406. },
  1407. };
  1408. module_platform_driver(samsung_i2s_driver);
  1409. /* Module information */
  1410. MODULE_AUTHOR("Jaswinder Singh, <[email protected]>");
  1411. MODULE_DESCRIPTION("Samsung I2S Interface");
  1412. MODULE_ALIAS("platform:samsung-i2s");
  1413. MODULE_LICENSE("GPL");