rockchip_pdm.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
  4. *
  5. * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
  6. */
  7. #include <linux/module.h>
  8. #include <linux/clk.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/rational.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset.h>
  15. #include <sound/dmaengine_pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include "rockchip_pdm.h"
  18. #define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */
  19. #define PDM_SIGNOFF_CLK_RATE (100000000)
  20. #define PDM_PATH_MAX (4)
  21. enum rk_pdm_version {
  22. RK_PDM_RK3229,
  23. RK_PDM_RK3308,
  24. RK_PDM_RV1126,
  25. };
  26. struct rk_pdm_dev {
  27. struct device *dev;
  28. struct clk *clk;
  29. struct clk *hclk;
  30. struct regmap *regmap;
  31. struct snd_dmaengine_dai_dma_data capture_dma_data;
  32. struct reset_control *reset;
  33. enum rk_pdm_version version;
  34. };
  35. struct rk_pdm_clkref {
  36. unsigned int sr;
  37. unsigned int clk;
  38. unsigned int clk_out;
  39. };
  40. struct rk_pdm_ds_ratio {
  41. unsigned int ratio;
  42. unsigned int sr;
  43. };
  44. static struct rk_pdm_clkref clkref[] = {
  45. { 8000, 40960000, 2048000 },
  46. { 11025, 56448000, 2822400 },
  47. { 12000, 61440000, 3072000 },
  48. { 8000, 98304000, 2048000 },
  49. { 12000, 98304000, 3072000 },
  50. };
  51. static struct rk_pdm_ds_ratio ds_ratio[] = {
  52. { 0, 192000 },
  53. { 0, 176400 },
  54. { 0, 128000 },
  55. { 1, 96000 },
  56. { 1, 88200 },
  57. { 1, 64000 },
  58. { 2, 48000 },
  59. { 2, 44100 },
  60. { 2, 32000 },
  61. { 3, 24000 },
  62. { 3, 22050 },
  63. { 3, 16000 },
  64. { 4, 12000 },
  65. { 4, 11025 },
  66. { 4, 8000 },
  67. };
  68. static unsigned int get_pdm_clk(struct rk_pdm_dev *pdm, unsigned int sr,
  69. unsigned int *clk_src, unsigned int *clk_out)
  70. {
  71. unsigned int i, count, clk, div, rate;
  72. clk = 0;
  73. if (!sr)
  74. return clk;
  75. count = ARRAY_SIZE(clkref);
  76. for (i = 0; i < count; i++) {
  77. if (sr % clkref[i].sr)
  78. continue;
  79. div = sr / clkref[i].sr;
  80. if ((div & (div - 1)) == 0) {
  81. *clk_out = clkref[i].clk_out;
  82. rate = clk_round_rate(pdm->clk, clkref[i].clk);
  83. if (rate != clkref[i].clk)
  84. continue;
  85. clk = clkref[i].clk;
  86. *clk_src = clkref[i].clk;
  87. break;
  88. }
  89. }
  90. if (!clk) {
  91. clk = clk_round_rate(pdm->clk, PDM_SIGNOFF_CLK_RATE);
  92. *clk_src = clk;
  93. }
  94. return clk;
  95. }
  96. static unsigned int get_pdm_ds_ratio(unsigned int sr)
  97. {
  98. unsigned int i, count, ratio;
  99. ratio = 0;
  100. if (!sr)
  101. return ratio;
  102. count = ARRAY_SIZE(ds_ratio);
  103. for (i = 0; i < count; i++) {
  104. if (sr == ds_ratio[i].sr)
  105. ratio = ds_ratio[i].ratio;
  106. }
  107. return ratio;
  108. }
  109. static unsigned int get_pdm_cic_ratio(unsigned int clk)
  110. {
  111. switch (clk) {
  112. case 4096000:
  113. case 5644800:
  114. case 6144000:
  115. return 0;
  116. case 2048000:
  117. case 2822400:
  118. case 3072000:
  119. return 1;
  120. case 1024000:
  121. case 1411200:
  122. case 1536000:
  123. return 2;
  124. default:
  125. return 1;
  126. }
  127. }
  128. static unsigned int samplerate_to_bit(unsigned int samplerate)
  129. {
  130. switch (samplerate) {
  131. case 8000:
  132. case 11025:
  133. case 12000:
  134. return 0;
  135. case 16000:
  136. case 22050:
  137. case 24000:
  138. return 1;
  139. case 32000:
  140. return 2;
  141. case 44100:
  142. case 48000:
  143. return 3;
  144. case 64000:
  145. case 88200:
  146. case 96000:
  147. return 4;
  148. case 128000:
  149. case 176400:
  150. case 192000:
  151. return 5;
  152. default:
  153. return 1;
  154. }
  155. }
  156. static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
  157. {
  158. return snd_soc_dai_get_drvdata(dai);
  159. }
  160. static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on)
  161. {
  162. if (on) {
  163. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
  164. PDM_DMA_RD_MSK, PDM_DMA_RD_EN);
  165. regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
  166. PDM_RX_MASK, PDM_RX_START);
  167. } else {
  168. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
  169. PDM_DMA_RD_MSK, PDM_DMA_RD_DIS);
  170. regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
  171. PDM_RX_MASK | PDM_RX_CLR_MASK,
  172. PDM_RX_STOP | PDM_RX_CLR_WR);
  173. }
  174. }
  175. static int rockchip_pdm_hw_params(struct snd_pcm_substream *substream,
  176. struct snd_pcm_hw_params *params,
  177. struct snd_soc_dai *dai)
  178. {
  179. struct rk_pdm_dev *pdm = to_info(dai);
  180. unsigned int val = 0;
  181. unsigned int clk_rate, clk_div, samplerate;
  182. unsigned int clk_src, clk_out = 0;
  183. unsigned long m, n;
  184. bool change;
  185. int ret;
  186. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  187. return 0;
  188. samplerate = params_rate(params);
  189. clk_rate = get_pdm_clk(pdm, samplerate, &clk_src, &clk_out);
  190. if (!clk_rate)
  191. return -EINVAL;
  192. ret = clk_set_rate(pdm->clk, clk_src);
  193. if (ret)
  194. return -EINVAL;
  195. if (pdm->version == RK_PDM_RK3308 ||
  196. pdm->version == RK_PDM_RV1126) {
  197. rational_best_approximation(clk_out, clk_src,
  198. GENMASK(16 - 1, 0),
  199. GENMASK(16 - 1, 0),
  200. &m, &n);
  201. val = (m << PDM_FD_NUMERATOR_SFT) |
  202. (n << PDM_FD_DENOMINATOR_SFT);
  203. regmap_update_bits_check(pdm->regmap, PDM_CTRL1,
  204. PDM_FD_NUMERATOR_MSK |
  205. PDM_FD_DENOMINATOR_MSK,
  206. val, &change);
  207. if (change) {
  208. reset_control_assert(pdm->reset);
  209. reset_control_deassert(pdm->reset);
  210. rockchip_pdm_rxctrl(pdm, 0);
  211. }
  212. clk_div = n / m;
  213. if (clk_div >= 40)
  214. val = PDM_CLK_FD_RATIO_40;
  215. else if (clk_div <= 35)
  216. val = PDM_CLK_FD_RATIO_35;
  217. else
  218. return -EINVAL;
  219. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL,
  220. PDM_CLK_FD_RATIO_MSK,
  221. val);
  222. }
  223. if (pdm->version == RK_PDM_RV1126) {
  224. val = get_pdm_cic_ratio(clk_out);
  225. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val);
  226. val = samplerate_to_bit(samplerate);
  227. regmap_update_bits(pdm->regmap, PDM_CTRL0,
  228. PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val));
  229. } else {
  230. val = get_pdm_ds_ratio(samplerate);
  231. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
  232. }
  233. regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
  234. PDM_HPF_CF_MSK, PDM_HPF_60HZ);
  235. regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
  236. PDM_HPF_LE | PDM_HPF_RE, PDM_HPF_LE | PDM_HPF_RE);
  237. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CLK_EN, PDM_CLK_EN);
  238. if (pdm->version != RK_PDM_RK3229)
  239. regmap_update_bits(pdm->regmap, PDM_CTRL0,
  240. PDM_MODE_MSK, PDM_MODE_LJ);
  241. val = 0;
  242. switch (params_format(params)) {
  243. case SNDRV_PCM_FORMAT_S8:
  244. val |= PDM_VDW(8);
  245. break;
  246. case SNDRV_PCM_FORMAT_S16_LE:
  247. val |= PDM_VDW(16);
  248. break;
  249. case SNDRV_PCM_FORMAT_S20_3LE:
  250. val |= PDM_VDW(20);
  251. break;
  252. case SNDRV_PCM_FORMAT_S24_LE:
  253. val |= PDM_VDW(24);
  254. break;
  255. case SNDRV_PCM_FORMAT_S32_LE:
  256. val |= PDM_VDW(32);
  257. break;
  258. default:
  259. return -EINVAL;
  260. }
  261. switch (params_channels(params)) {
  262. case 8:
  263. val |= PDM_PATH3_EN;
  264. fallthrough;
  265. case 6:
  266. val |= PDM_PATH2_EN;
  267. fallthrough;
  268. case 4:
  269. val |= PDM_PATH1_EN;
  270. fallthrough;
  271. case 2:
  272. val |= PDM_PATH0_EN;
  273. break;
  274. default:
  275. dev_err(pdm->dev, "invalid channel: %d\n",
  276. params_channels(params));
  277. return -EINVAL;
  278. }
  279. regmap_update_bits(pdm->regmap, PDM_CTRL0,
  280. PDM_PATH_MSK | PDM_VDW_MSK,
  281. val);
  282. /* all channels share the single FIFO */
  283. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RDL_MSK,
  284. PDM_DMA_RDL(8 * params_channels(params)));
  285. return 0;
  286. }
  287. static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
  288. unsigned int fmt)
  289. {
  290. struct rk_pdm_dev *pdm = to_info(cpu_dai);
  291. unsigned int mask = 0, val = 0;
  292. mask = PDM_CKP_MSK;
  293. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  294. case SND_SOC_DAIFMT_NB_NF:
  295. val = PDM_CKP_NORMAL;
  296. break;
  297. case SND_SOC_DAIFMT_IB_NF:
  298. val = PDM_CKP_INVERTED;
  299. break;
  300. default:
  301. return -EINVAL;
  302. }
  303. pm_runtime_get_sync(cpu_dai->dev);
  304. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val);
  305. pm_runtime_put(cpu_dai->dev);
  306. return 0;
  307. }
  308. static int rockchip_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
  309. struct snd_soc_dai *dai)
  310. {
  311. struct rk_pdm_dev *pdm = to_info(dai);
  312. int ret = 0;
  313. switch (cmd) {
  314. case SNDRV_PCM_TRIGGER_START:
  315. case SNDRV_PCM_TRIGGER_RESUME:
  316. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  317. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  318. rockchip_pdm_rxctrl(pdm, 1);
  319. break;
  320. case SNDRV_PCM_TRIGGER_SUSPEND:
  321. case SNDRV_PCM_TRIGGER_STOP:
  322. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  323. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  324. rockchip_pdm_rxctrl(pdm, 0);
  325. break;
  326. default:
  327. ret = -EINVAL;
  328. break;
  329. }
  330. return ret;
  331. }
  332. static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
  333. {
  334. struct rk_pdm_dev *pdm = to_info(dai);
  335. dai->capture_dma_data = &pdm->capture_dma_data;
  336. return 0;
  337. }
  338. static const struct snd_soc_dai_ops rockchip_pdm_dai_ops = {
  339. .set_fmt = rockchip_pdm_set_fmt,
  340. .trigger = rockchip_pdm_trigger,
  341. .hw_params = rockchip_pdm_hw_params,
  342. };
  343. #define ROCKCHIP_PDM_RATES SNDRV_PCM_RATE_8000_192000
  344. #define ROCKCHIP_PDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  345. SNDRV_PCM_FMTBIT_S20_3LE | \
  346. SNDRV_PCM_FMTBIT_S24_LE | \
  347. SNDRV_PCM_FMTBIT_S32_LE)
  348. static struct snd_soc_dai_driver rockchip_pdm_dai = {
  349. .probe = rockchip_pdm_dai_probe,
  350. .capture = {
  351. .stream_name = "Capture",
  352. .channels_min = 2,
  353. .channels_max = 8,
  354. .rates = ROCKCHIP_PDM_RATES,
  355. .formats = ROCKCHIP_PDM_FORMATS,
  356. },
  357. .ops = &rockchip_pdm_dai_ops,
  358. .symmetric_rate = 1,
  359. };
  360. static const struct snd_soc_component_driver rockchip_pdm_component = {
  361. .name = "rockchip-pdm",
  362. .legacy_dai_naming = 1,
  363. };
  364. static int rockchip_pdm_runtime_suspend(struct device *dev)
  365. {
  366. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  367. clk_disable_unprepare(pdm->clk);
  368. clk_disable_unprepare(pdm->hclk);
  369. return 0;
  370. }
  371. static int rockchip_pdm_runtime_resume(struct device *dev)
  372. {
  373. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  374. int ret;
  375. ret = clk_prepare_enable(pdm->clk);
  376. if (ret) {
  377. dev_err(pdm->dev, "clock enable failed %d\n", ret);
  378. return ret;
  379. }
  380. ret = clk_prepare_enable(pdm->hclk);
  381. if (ret) {
  382. clk_disable_unprepare(pdm->clk);
  383. dev_err(pdm->dev, "hclock enable failed %d\n", ret);
  384. return ret;
  385. }
  386. return 0;
  387. }
  388. static bool rockchip_pdm_wr_reg(struct device *dev, unsigned int reg)
  389. {
  390. switch (reg) {
  391. case PDM_SYSCONFIG:
  392. case PDM_CTRL0:
  393. case PDM_CTRL1:
  394. case PDM_CLK_CTRL:
  395. case PDM_HPF_CTRL:
  396. case PDM_FIFO_CTRL:
  397. case PDM_DMA_CTRL:
  398. case PDM_INT_EN:
  399. case PDM_INT_CLR:
  400. case PDM_DATA_VALID:
  401. return true;
  402. default:
  403. return false;
  404. }
  405. }
  406. static bool rockchip_pdm_rd_reg(struct device *dev, unsigned int reg)
  407. {
  408. switch (reg) {
  409. case PDM_SYSCONFIG:
  410. case PDM_CTRL0:
  411. case PDM_CTRL1:
  412. case PDM_CLK_CTRL:
  413. case PDM_HPF_CTRL:
  414. case PDM_FIFO_CTRL:
  415. case PDM_DMA_CTRL:
  416. case PDM_INT_EN:
  417. case PDM_INT_CLR:
  418. case PDM_INT_ST:
  419. case PDM_DATA_VALID:
  420. case PDM_RXFIFO_DATA:
  421. case PDM_VERSION:
  422. return true;
  423. default:
  424. return false;
  425. }
  426. }
  427. static bool rockchip_pdm_volatile_reg(struct device *dev, unsigned int reg)
  428. {
  429. switch (reg) {
  430. case PDM_SYSCONFIG:
  431. case PDM_FIFO_CTRL:
  432. case PDM_INT_CLR:
  433. case PDM_INT_ST:
  434. case PDM_RXFIFO_DATA:
  435. return true;
  436. default:
  437. return false;
  438. }
  439. }
  440. static bool rockchip_pdm_precious_reg(struct device *dev, unsigned int reg)
  441. {
  442. switch (reg) {
  443. case PDM_RXFIFO_DATA:
  444. return true;
  445. default:
  446. return false;
  447. }
  448. }
  449. static const struct reg_default rockchip_pdm_reg_defaults[] = {
  450. { PDM_CTRL0, 0x78000017 },
  451. { PDM_CTRL1, 0x0bb8ea60 },
  452. { PDM_CLK_CTRL, 0x0000e401 },
  453. { PDM_DMA_CTRL, 0x0000001f },
  454. };
  455. static const struct regmap_config rockchip_pdm_regmap_config = {
  456. .reg_bits = 32,
  457. .reg_stride = 4,
  458. .val_bits = 32,
  459. .max_register = PDM_VERSION,
  460. .reg_defaults = rockchip_pdm_reg_defaults,
  461. .num_reg_defaults = ARRAY_SIZE(rockchip_pdm_reg_defaults),
  462. .writeable_reg = rockchip_pdm_wr_reg,
  463. .readable_reg = rockchip_pdm_rd_reg,
  464. .volatile_reg = rockchip_pdm_volatile_reg,
  465. .precious_reg = rockchip_pdm_precious_reg,
  466. .cache_type = REGCACHE_FLAT,
  467. };
  468. static const struct of_device_id rockchip_pdm_match[] __maybe_unused = {
  469. { .compatible = "rockchip,pdm",
  470. .data = (void *)RK_PDM_RK3229 },
  471. { .compatible = "rockchip,px30-pdm",
  472. .data = (void *)RK_PDM_RK3308 },
  473. { .compatible = "rockchip,rk1808-pdm",
  474. .data = (void *)RK_PDM_RK3308 },
  475. { .compatible = "rockchip,rk3308-pdm",
  476. .data = (void *)RK_PDM_RK3308 },
  477. { .compatible = "rockchip,rk3568-pdm",
  478. .data = (void *)RK_PDM_RV1126 },
  479. { .compatible = "rockchip,rv1126-pdm",
  480. .data = (void *)RK_PDM_RV1126 },
  481. {},
  482. };
  483. MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
  484. static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node)
  485. {
  486. unsigned int path[PDM_PATH_MAX];
  487. int cnt = 0, ret = 0, i = 0, val = 0, msk = 0;
  488. cnt = of_count_phandle_with_args(node, "rockchip,path-map",
  489. NULL);
  490. if (cnt != PDM_PATH_MAX)
  491. return cnt;
  492. ret = of_property_read_u32_array(node, "rockchip,path-map",
  493. path, cnt);
  494. if (ret)
  495. return ret;
  496. for (i = 0; i < cnt; i++) {
  497. if (path[i] >= PDM_PATH_MAX)
  498. return -EINVAL;
  499. msk |= PDM_PATH_MASK(i);
  500. val |= PDM_PATH(i, path[i]);
  501. }
  502. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val);
  503. return 0;
  504. }
  505. static int rockchip_pdm_probe(struct platform_device *pdev)
  506. {
  507. struct device_node *node = pdev->dev.of_node;
  508. const struct of_device_id *match;
  509. struct rk_pdm_dev *pdm;
  510. struct resource *res;
  511. void __iomem *regs;
  512. int ret;
  513. pdm = devm_kzalloc(&pdev->dev, sizeof(*pdm), GFP_KERNEL);
  514. if (!pdm)
  515. return -ENOMEM;
  516. match = of_match_device(rockchip_pdm_match, &pdev->dev);
  517. if (match)
  518. pdm->version = (enum rk_pdm_version)match->data;
  519. if (pdm->version == RK_PDM_RK3308) {
  520. pdm->reset = devm_reset_control_get(&pdev->dev, "pdm-m");
  521. if (IS_ERR(pdm->reset))
  522. return PTR_ERR(pdm->reset);
  523. }
  524. regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  525. if (IS_ERR(regs))
  526. return PTR_ERR(regs);
  527. pdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
  528. &rockchip_pdm_regmap_config);
  529. if (IS_ERR(pdm->regmap))
  530. return PTR_ERR(pdm->regmap);
  531. pdm->capture_dma_data.addr = res->start + PDM_RXFIFO_DATA;
  532. pdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  533. pdm->capture_dma_data.maxburst = PDM_DMA_BURST_SIZE;
  534. pdm->dev = &pdev->dev;
  535. dev_set_drvdata(&pdev->dev, pdm);
  536. pdm->clk = devm_clk_get(&pdev->dev, "pdm_clk");
  537. if (IS_ERR(pdm->clk))
  538. return PTR_ERR(pdm->clk);
  539. pdm->hclk = devm_clk_get(&pdev->dev, "pdm_hclk");
  540. if (IS_ERR(pdm->hclk))
  541. return PTR_ERR(pdm->hclk);
  542. ret = clk_prepare_enable(pdm->hclk);
  543. if (ret)
  544. return ret;
  545. pm_runtime_enable(&pdev->dev);
  546. if (!pm_runtime_enabled(&pdev->dev)) {
  547. ret = rockchip_pdm_runtime_resume(&pdev->dev);
  548. if (ret)
  549. goto err_pm_disable;
  550. }
  551. ret = devm_snd_soc_register_component(&pdev->dev,
  552. &rockchip_pdm_component,
  553. &rockchip_pdm_dai, 1);
  554. if (ret) {
  555. dev_err(&pdev->dev, "could not register dai: %d\n", ret);
  556. goto err_suspend;
  557. }
  558. rockchip_pdm_rxctrl(pdm, 0);
  559. ret = rockchip_pdm_path_parse(pdm, node);
  560. if (ret != 0 && ret != -ENOENT)
  561. goto err_suspend;
  562. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  563. if (ret) {
  564. dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
  565. goto err_suspend;
  566. }
  567. return 0;
  568. err_suspend:
  569. if (!pm_runtime_status_suspended(&pdev->dev))
  570. rockchip_pdm_runtime_suspend(&pdev->dev);
  571. err_pm_disable:
  572. pm_runtime_disable(&pdev->dev);
  573. clk_disable_unprepare(pdm->hclk);
  574. return ret;
  575. }
  576. static int rockchip_pdm_remove(struct platform_device *pdev)
  577. {
  578. struct rk_pdm_dev *pdm = dev_get_drvdata(&pdev->dev);
  579. pm_runtime_disable(&pdev->dev);
  580. if (!pm_runtime_status_suspended(&pdev->dev))
  581. rockchip_pdm_runtime_suspend(&pdev->dev);
  582. clk_disable_unprepare(pdm->clk);
  583. clk_disable_unprepare(pdm->hclk);
  584. return 0;
  585. }
  586. #ifdef CONFIG_PM_SLEEP
  587. static int rockchip_pdm_suspend(struct device *dev)
  588. {
  589. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  590. regcache_mark_dirty(pdm->regmap);
  591. return 0;
  592. }
  593. static int rockchip_pdm_resume(struct device *dev)
  594. {
  595. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  596. int ret;
  597. ret = pm_runtime_resume_and_get(dev);
  598. if (ret < 0)
  599. return ret;
  600. ret = regcache_sync(pdm->regmap);
  601. pm_runtime_put(dev);
  602. return ret;
  603. }
  604. #endif
  605. static const struct dev_pm_ops rockchip_pdm_pm_ops = {
  606. SET_RUNTIME_PM_OPS(rockchip_pdm_runtime_suspend,
  607. rockchip_pdm_runtime_resume, NULL)
  608. SET_SYSTEM_SLEEP_PM_OPS(rockchip_pdm_suspend, rockchip_pdm_resume)
  609. };
  610. static struct platform_driver rockchip_pdm_driver = {
  611. .probe = rockchip_pdm_probe,
  612. .remove = rockchip_pdm_remove,
  613. .driver = {
  614. .name = "rockchip-pdm",
  615. .of_match_table = of_match_ptr(rockchip_pdm_match),
  616. .pm = &rockchip_pdm_pm_ops,
  617. },
  618. };
  619. module_platform_driver(rockchip_pdm_driver);
  620. MODULE_AUTHOR("Sugar <[email protected]>");
  621. MODULE_DESCRIPTION("Rockchip PDM Controller Driver");
  622. MODULE_LICENSE("GPL v2");