lpass-cpu.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
  4. *
  5. * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <sound/pcm.h>
  14. #include <sound/pcm_params.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dai.h>
  18. #include "lpass-lpaif-reg.h"
  19. #include "lpass.h"
  20. #define LPASS_CPU_MAX_MI2S_LINES 4
  21. #define LPASS_CPU_I2S_SD0_MASK BIT(0)
  22. #define LPASS_CPU_I2S_SD1_MASK BIT(1)
  23. #define LPASS_CPU_I2S_SD2_MASK BIT(2)
  24. #define LPASS_CPU_I2S_SD3_MASK BIT(3)
  25. #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
  26. #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
  27. #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
  28. #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
  29. #define LPASS_REG_READ 1
  30. #define LPASS_REG_WRITE 0
  31. /*
  32. * Channel maps for Quad channel playbacks on MI2S Secondary
  33. */
  34. static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = {
  35. { .channels = 4,
  36. .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL,
  37. SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } },
  38. { }
  39. };
  40. static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
  41. struct lpaif_i2sctl *i2sctl, struct regmap *map)
  42. {
  43. struct lpass_data *drvdata = dev_get_drvdata(dev);
  44. struct lpass_variant *v = drvdata->variant;
  45. i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
  46. i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
  47. i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
  48. i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
  49. i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
  50. i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
  51. i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
  52. i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
  53. i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
  54. if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
  55. IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
  56. IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
  57. IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
  58. IS_ERR(i2sctl->bitwidth))
  59. return -EINVAL;
  60. return 0;
  61. }
  62. static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  63. unsigned int freq, int dir)
  64. {
  65. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  66. int ret;
  67. ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
  68. if (ret)
  69. dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
  70. freq, ret);
  71. return ret;
  72. }
  73. static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
  74. struct snd_soc_dai *dai)
  75. {
  76. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  77. int ret;
  78. ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
  79. if (ret) {
  80. dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
  81. return ret;
  82. }
  83. ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  84. if (ret) {
  85. dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  86. clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  87. return ret;
  88. }
  89. return 0;
  90. }
  91. static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
  92. struct snd_soc_dai *dai)
  93. {
  94. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  95. struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
  96. unsigned int id = dai->driver->id;
  97. clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
  98. /*
  99. * Ensure LRCLK is disabled even in device node validation.
  100. * Will not impact if disabled in lpass_cpu_daiops_trigger()
  101. * suspend.
  102. */
  103. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  104. regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
  105. else
  106. regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
  107. /*
  108. * BCLK may not be enabled if lpass_cpu_daiops_prepare is called before
  109. * lpass_cpu_daiops_shutdown. It's paired with the clk_enable in
  110. * lpass_cpu_daiops_prepare.
  111. */
  112. if (drvdata->mi2s_was_prepared[dai->driver->id]) {
  113. drvdata->mi2s_was_prepared[dai->driver->id] = false;
  114. clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
  115. }
  116. clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
  117. }
  118. static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
  119. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  120. {
  121. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  122. struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
  123. unsigned int id = dai->driver->id;
  124. snd_pcm_format_t format = params_format(params);
  125. unsigned int channels = params_channels(params);
  126. unsigned int rate = params_rate(params);
  127. unsigned int mode;
  128. unsigned int regval;
  129. int bitwidth, ret;
  130. bitwidth = snd_pcm_format_width(format);
  131. if (bitwidth < 0) {
  132. dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
  133. return bitwidth;
  134. }
  135. ret = regmap_fields_write(i2sctl->loopback, id,
  136. LPAIF_I2SCTL_LOOPBACK_DISABLE);
  137. if (ret) {
  138. dev_err(dai->dev, "error updating loopback field: %d\n", ret);
  139. return ret;
  140. }
  141. ret = regmap_fields_write(i2sctl->wssrc, id,
  142. LPAIF_I2SCTL_WSSRC_INTERNAL);
  143. if (ret) {
  144. dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
  145. return ret;
  146. }
  147. switch (bitwidth) {
  148. case 16:
  149. regval = LPAIF_I2SCTL_BITWIDTH_16;
  150. break;
  151. case 24:
  152. regval = LPAIF_I2SCTL_BITWIDTH_24;
  153. break;
  154. case 32:
  155. regval = LPAIF_I2SCTL_BITWIDTH_32;
  156. break;
  157. default:
  158. dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
  159. return -EINVAL;
  160. }
  161. ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
  162. if (ret) {
  163. dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
  164. return ret;
  165. }
  166. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  167. mode = drvdata->mi2s_playback_sd_mode[id];
  168. else
  169. mode = drvdata->mi2s_capture_sd_mode[id];
  170. if (!mode) {
  171. dev_err(dai->dev, "no line is assigned\n");
  172. return -EINVAL;
  173. }
  174. switch (channels) {
  175. case 1:
  176. case 2:
  177. switch (mode) {
  178. case LPAIF_I2SCTL_MODE_QUAD01:
  179. case LPAIF_I2SCTL_MODE_6CH:
  180. case LPAIF_I2SCTL_MODE_8CH:
  181. mode = LPAIF_I2SCTL_MODE_SD0;
  182. break;
  183. case LPAIF_I2SCTL_MODE_QUAD23:
  184. mode = LPAIF_I2SCTL_MODE_SD2;
  185. break;
  186. }
  187. break;
  188. case 4:
  189. if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
  190. dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
  191. mode);
  192. return -EINVAL;
  193. }
  194. switch (mode) {
  195. case LPAIF_I2SCTL_MODE_6CH:
  196. case LPAIF_I2SCTL_MODE_8CH:
  197. mode = LPAIF_I2SCTL_MODE_QUAD01;
  198. break;
  199. }
  200. break;
  201. case 6:
  202. if (mode < LPAIF_I2SCTL_MODE_6CH) {
  203. dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
  204. mode);
  205. return -EINVAL;
  206. }
  207. switch (mode) {
  208. case LPAIF_I2SCTL_MODE_8CH:
  209. mode = LPAIF_I2SCTL_MODE_6CH;
  210. break;
  211. }
  212. break;
  213. case 8:
  214. if (mode < LPAIF_I2SCTL_MODE_8CH) {
  215. dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
  216. mode);
  217. return -EINVAL;
  218. }
  219. break;
  220. default:
  221. dev_err(dai->dev, "invalid channels given: %u\n", channels);
  222. return -EINVAL;
  223. }
  224. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  225. ret = regmap_fields_write(i2sctl->spkmode, id,
  226. LPAIF_I2SCTL_SPKMODE(mode));
  227. if (ret) {
  228. dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
  229. ret);
  230. return ret;
  231. }
  232. if (channels >= 2)
  233. ret = regmap_fields_write(i2sctl->spkmono, id,
  234. LPAIF_I2SCTL_SPKMONO_STEREO);
  235. else
  236. ret = regmap_fields_write(i2sctl->spkmono, id,
  237. LPAIF_I2SCTL_SPKMONO_MONO);
  238. } else {
  239. ret = regmap_fields_write(i2sctl->micmode, id,
  240. LPAIF_I2SCTL_MICMODE(mode));
  241. if (ret) {
  242. dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
  243. ret);
  244. return ret;
  245. }
  246. if (channels >= 2)
  247. ret = regmap_fields_write(i2sctl->micmono, id,
  248. LPAIF_I2SCTL_MICMONO_STEREO);
  249. else
  250. ret = regmap_fields_write(i2sctl->micmono, id,
  251. LPAIF_I2SCTL_MICMONO_MONO);
  252. }
  253. if (ret) {
  254. dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
  255. ret);
  256. return ret;
  257. }
  258. ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
  259. rate * bitwidth * 2);
  260. if (ret) {
  261. dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
  262. rate * bitwidth * 2, ret);
  263. return ret;
  264. }
  265. return 0;
  266. }
  267. static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
  268. int cmd, struct snd_soc_dai *dai)
  269. {
  270. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  271. struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
  272. unsigned int id = dai->driver->id;
  273. int ret = -EINVAL;
  274. switch (cmd) {
  275. case SNDRV_PCM_TRIGGER_START:
  276. case SNDRV_PCM_TRIGGER_RESUME:
  277. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  278. /*
  279. * Ensure lpass BCLK/LRCLK is enabled during
  280. * device resume as lpass_cpu_daiops_prepare() is not called
  281. * after the device resumes. We don't check mi2s_was_prepared before
  282. * enable/disable BCLK in trigger events because:
  283. * 1. These trigger events are paired, so the BCLK
  284. * enable_count is balanced.
  285. * 2. the BCLK can be shared (ex: headset and headset mic),
  286. * we need to increase the enable_count so that we don't
  287. * turn off the shared BCLK while other devices are using
  288. * it.
  289. */
  290. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  291. ret = regmap_fields_write(i2sctl->spken, id,
  292. LPAIF_I2SCTL_SPKEN_ENABLE);
  293. } else {
  294. ret = regmap_fields_write(i2sctl->micen, id,
  295. LPAIF_I2SCTL_MICEN_ENABLE);
  296. }
  297. if (ret)
  298. dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
  299. ret);
  300. ret = clk_enable(drvdata->mi2s_bit_clk[id]);
  301. if (ret) {
  302. dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  303. clk_disable(drvdata->mi2s_osr_clk[id]);
  304. return ret;
  305. }
  306. break;
  307. case SNDRV_PCM_TRIGGER_STOP:
  308. case SNDRV_PCM_TRIGGER_SUSPEND:
  309. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  310. /*
  311. * To ensure lpass BCLK/LRCLK is disabled during
  312. * device suspend.
  313. */
  314. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  315. ret = regmap_fields_write(i2sctl->spken, id,
  316. LPAIF_I2SCTL_SPKEN_DISABLE);
  317. } else {
  318. ret = regmap_fields_write(i2sctl->micen, id,
  319. LPAIF_I2SCTL_MICEN_DISABLE);
  320. }
  321. if (ret)
  322. dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
  323. ret);
  324. clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
  325. break;
  326. }
  327. return ret;
  328. }
  329. static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
  330. struct snd_soc_dai *dai)
  331. {
  332. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  333. struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
  334. unsigned int id = dai->driver->id;
  335. int ret;
  336. /*
  337. * Ensure lpass BCLK/LRCLK is enabled bit before playback/capture
  338. * data flow starts. This allows other codec to have some delay before
  339. * the data flow.
  340. * (ex: to drop start up pop noise before capture starts).
  341. */
  342. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  343. ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
  344. else
  345. ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
  346. if (ret) {
  347. dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
  348. return ret;
  349. }
  350. /*
  351. * Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can
  352. * be called multiple times. It's paired with the clk_disable in
  353. * lpass_cpu_daiops_shutdown.
  354. */
  355. if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
  356. ret = clk_enable(drvdata->mi2s_bit_clk[id]);
  357. if (ret) {
  358. dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
  359. return ret;
  360. }
  361. drvdata->mi2s_was_prepared[dai->driver->id] = true;
  362. }
  363. return 0;
  364. }
  365. const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
  366. .set_sysclk = lpass_cpu_daiops_set_sysclk,
  367. .startup = lpass_cpu_daiops_startup,
  368. .shutdown = lpass_cpu_daiops_shutdown,
  369. .hw_params = lpass_cpu_daiops_hw_params,
  370. .trigger = lpass_cpu_daiops_trigger,
  371. .prepare = lpass_cpu_daiops_prepare,
  372. };
  373. EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
  374. int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd,
  375. struct snd_soc_dai *dai)
  376. {
  377. int ret;
  378. struct snd_soc_dai_driver *drv = dai->driver;
  379. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  380. if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) {
  381. ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,
  382. lpass_quad_chmaps, drv->playback.channels_max, 0,
  383. NULL);
  384. if (ret < 0)
  385. return ret;
  386. }
  387. return 0;
  388. }
  389. EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new);
  390. int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
  391. {
  392. struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
  393. int ret;
  394. /* ensure audio hardware is disabled */
  395. ret = regmap_write(drvdata->lpaif_map,
  396. LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
  397. if (ret)
  398. dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
  399. return ret;
  400. }
  401. EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
  402. static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
  403. const struct of_phandle_args *args,
  404. const char **dai_name)
  405. {
  406. struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
  407. struct lpass_variant *variant = drvdata->variant;
  408. int id = args->args[0];
  409. int ret = -EINVAL;
  410. int i;
  411. for (i = 0; i < variant->num_dai; i++) {
  412. if (variant->dai_driver[i].id == id) {
  413. *dai_name = variant->dai_driver[i].name;
  414. ret = 0;
  415. break;
  416. }
  417. }
  418. return ret;
  419. }
  420. static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
  421. .name = "lpass-cpu",
  422. .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
  423. .legacy_dai_naming = 1,
  424. };
  425. static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
  426. {
  427. struct lpass_data *drvdata = dev_get_drvdata(dev);
  428. struct lpass_variant *v = drvdata->variant;
  429. int i;
  430. for (i = 0; i < v->i2s_ports; ++i)
  431. if (reg == LPAIF_I2SCTL_REG(v, i))
  432. return true;
  433. for (i = 0; i < v->irq_ports; ++i) {
  434. if (reg == LPAIF_IRQEN_REG(v, i))
  435. return true;
  436. if (reg == LPAIF_IRQCLEAR_REG(v, i))
  437. return true;
  438. }
  439. for (i = 0; i < v->rdma_channels; ++i) {
  440. if (reg == LPAIF_RDMACTL_REG(v, i))
  441. return true;
  442. if (reg == LPAIF_RDMABASE_REG(v, i))
  443. return true;
  444. if (reg == LPAIF_RDMABUFF_REG(v, i))
  445. return true;
  446. if (reg == LPAIF_RDMAPER_REG(v, i))
  447. return true;
  448. }
  449. for (i = 0; i < v->wrdma_channels; ++i) {
  450. if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
  451. return true;
  452. if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
  453. return true;
  454. if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
  455. return true;
  456. if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
  457. return true;
  458. }
  459. return false;
  460. }
  461. static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
  462. {
  463. struct lpass_data *drvdata = dev_get_drvdata(dev);
  464. struct lpass_variant *v = drvdata->variant;
  465. int i;
  466. for (i = 0; i < v->i2s_ports; ++i)
  467. if (reg == LPAIF_I2SCTL_REG(v, i))
  468. return true;
  469. for (i = 0; i < v->irq_ports; ++i) {
  470. if (reg == LPAIF_IRQCLEAR_REG(v, i))
  471. return true;
  472. if (reg == LPAIF_IRQEN_REG(v, i))
  473. return true;
  474. if (reg == LPAIF_IRQSTAT_REG(v, i))
  475. return true;
  476. }
  477. for (i = 0; i < v->rdma_channels; ++i) {
  478. if (reg == LPAIF_RDMACTL_REG(v, i))
  479. return true;
  480. if (reg == LPAIF_RDMABASE_REG(v, i))
  481. return true;
  482. if (reg == LPAIF_RDMABUFF_REG(v, i))
  483. return true;
  484. if (reg == LPAIF_RDMACURR_REG(v, i))
  485. return true;
  486. if (reg == LPAIF_RDMAPER_REG(v, i))
  487. return true;
  488. }
  489. for (i = 0; i < v->wrdma_channels; ++i) {
  490. if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
  491. return true;
  492. if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
  493. return true;
  494. if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
  495. return true;
  496. if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
  497. return true;
  498. if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
  499. return true;
  500. }
  501. return false;
  502. }
  503. static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
  504. {
  505. struct lpass_data *drvdata = dev_get_drvdata(dev);
  506. struct lpass_variant *v = drvdata->variant;
  507. int i;
  508. for (i = 0; i < v->irq_ports; ++i) {
  509. if (reg == LPAIF_IRQCLEAR_REG(v, i))
  510. return true;
  511. if (reg == LPAIF_IRQSTAT_REG(v, i))
  512. return true;
  513. }
  514. for (i = 0; i < v->rdma_channels; ++i)
  515. if (reg == LPAIF_RDMACURR_REG(v, i))
  516. return true;
  517. for (i = 0; i < v->wrdma_channels; ++i)
  518. if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
  519. return true;
  520. return false;
  521. }
  522. static struct regmap_config lpass_cpu_regmap_config = {
  523. .name = "lpass_cpu",
  524. .reg_bits = 32,
  525. .reg_stride = 4,
  526. .val_bits = 32,
  527. .writeable_reg = lpass_cpu_regmap_writeable,
  528. .readable_reg = lpass_cpu_regmap_readable,
  529. .volatile_reg = lpass_cpu_regmap_volatile,
  530. .cache_type = REGCACHE_FLAT,
  531. };
  532. static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
  533. {
  534. struct lpass_data *drvdata = dev_get_drvdata(dev);
  535. struct lpass_variant *v = drvdata->variant;
  536. unsigned int i;
  537. struct lpass_hdmi_tx_ctl *tx_ctl;
  538. struct regmap_field *legacy_en;
  539. struct lpass_vbit_ctrl *vbit_ctl;
  540. struct regmap_field *tx_parity;
  541. struct lpass_dp_metadata_ctl *meta_ctl;
  542. struct lpass_sstream_ctl *sstream_ctl;
  543. struct regmap_field *ch_msb;
  544. struct regmap_field *ch_lsb;
  545. struct lpass_hdmitx_dmactl *tx_dmactl;
  546. int rval;
  547. tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
  548. if (!tx_ctl)
  549. return -ENOMEM;
  550. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
  551. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
  552. drvdata->tx_ctl = tx_ctl;
  553. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
  554. drvdata->hdmitx_legacy_en = legacy_en;
  555. vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
  556. if (!vbit_ctl)
  557. return -ENOMEM;
  558. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
  559. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
  560. drvdata->vbit_ctl = vbit_ctl;
  561. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
  562. drvdata->hdmitx_parity_calc_en = tx_parity;
  563. meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
  564. if (!meta_ctl)
  565. return -ENOMEM;
  566. rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
  567. if (rval)
  568. return rval;
  569. drvdata->meta_ctl = meta_ctl;
  570. sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
  571. if (!sstream_ctl)
  572. return -ENOMEM;
  573. rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
  574. if (rval)
  575. return rval;
  576. drvdata->sstream_ctl = sstream_ctl;
  577. for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
  578. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
  579. drvdata->hdmitx_ch_msb[i] = ch_msb;
  580. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
  581. drvdata->hdmitx_ch_lsb[i] = ch_lsb;
  582. tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
  583. if (!tx_dmactl)
  584. return -ENOMEM;
  585. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
  586. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
  587. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
  588. QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
  589. drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
  590. }
  591. return 0;
  592. }
  593. static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
  594. {
  595. struct lpass_data *drvdata = dev_get_drvdata(dev);
  596. struct lpass_variant *v = drvdata->variant;
  597. int i;
  598. if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
  599. return true;
  600. if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
  601. return true;
  602. if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
  603. return true;
  604. if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
  605. return true;
  606. if (reg == LPASS_HDMI_TX_DP_ADDR(v))
  607. return true;
  608. if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
  609. return true;
  610. if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
  611. return true;
  612. if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
  613. return true;
  614. for (i = 0; i < v->hdmi_rdma_channels; i++) {
  615. if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
  616. return true;
  617. if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
  618. return true;
  619. if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
  620. return true;
  621. }
  622. for (i = 0; i < v->hdmi_rdma_channels; ++i) {
  623. if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
  624. return true;
  625. if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
  626. return true;
  627. if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
  628. return true;
  629. if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
  630. return true;
  631. }
  632. return false;
  633. }
  634. static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
  635. {
  636. struct lpass_data *drvdata = dev_get_drvdata(dev);
  637. struct lpass_variant *v = drvdata->variant;
  638. int i;
  639. if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
  640. return true;
  641. if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
  642. return true;
  643. if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
  644. return true;
  645. for (i = 0; i < v->hdmi_rdma_channels; i++) {
  646. if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
  647. return true;
  648. if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
  649. return true;
  650. if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
  651. return true;
  652. }
  653. if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
  654. return true;
  655. if (reg == LPASS_HDMI_TX_DP_ADDR(v))
  656. return true;
  657. if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
  658. return true;
  659. if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
  660. return true;
  661. if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
  662. return true;
  663. for (i = 0; i < v->hdmi_rdma_channels; ++i) {
  664. if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
  665. return true;
  666. if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
  667. return true;
  668. if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
  669. return true;
  670. if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
  671. return true;
  672. if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
  673. return true;
  674. }
  675. return false;
  676. }
  677. static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
  678. {
  679. struct lpass_data *drvdata = dev_get_drvdata(dev);
  680. struct lpass_variant *v = drvdata->variant;
  681. int i;
  682. if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
  683. return true;
  684. if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
  685. return true;
  686. if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
  687. return true;
  688. if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
  689. return true;
  690. for (i = 0; i < v->hdmi_rdma_channels; ++i) {
  691. if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
  692. return true;
  693. if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
  694. return true;
  695. if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
  696. return true;
  697. if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
  698. return true;
  699. }
  700. return false;
  701. }
  702. static struct regmap_config lpass_hdmi_regmap_config = {
  703. .name = "lpass_hdmi",
  704. .reg_bits = 32,
  705. .reg_stride = 4,
  706. .val_bits = 32,
  707. .writeable_reg = lpass_hdmi_regmap_writeable,
  708. .readable_reg = lpass_hdmi_regmap_readable,
  709. .volatile_reg = lpass_hdmi_regmap_volatile,
  710. .cache_type = REGCACHE_FLAT,
  711. };
  712. static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
  713. {
  714. struct lpass_data *drvdata = dev_get_drvdata(dev);
  715. struct lpass_variant *v = drvdata->variant;
  716. int i;
  717. for (i = 0; i < v->rxtx_irq_ports; ++i) {
  718. if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
  719. return true;
  720. if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
  721. return true;
  722. if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
  723. return true;
  724. }
  725. for (i = 0; i < v->rxtx_rdma_channels; ++i) {
  726. if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
  727. return true;
  728. if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
  729. return true;
  730. if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
  731. return true;
  732. if (rw == LPASS_REG_READ) {
  733. if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  734. return true;
  735. }
  736. if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
  737. return true;
  738. if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
  739. return true;
  740. }
  741. for (i = 0; i < v->rxtx_wrdma_channels; ++i) {
  742. if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
  743. LPASS_CDC_DMA_TX3))
  744. return true;
  745. if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
  746. LPASS_CDC_DMA_TX3))
  747. return true;
  748. if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
  749. LPASS_CDC_DMA_TX3))
  750. return true;
  751. if (rw == LPASS_REG_READ) {
  752. if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  753. return true;
  754. }
  755. if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
  756. LPASS_CDC_DMA_TX3))
  757. return true;
  758. if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
  759. LPASS_CDC_DMA_TX3))
  760. return true;
  761. }
  762. return false;
  763. }
  764. static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg)
  765. {
  766. return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);
  767. }
  768. static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg)
  769. {
  770. return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);
  771. }
  772. static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg)
  773. {
  774. struct lpass_data *drvdata = dev_get_drvdata(dev);
  775. struct lpass_variant *v = drvdata->variant;
  776. int i;
  777. for (i = 0; i < v->rxtx_irq_ports; ++i) {
  778. if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
  779. return true;
  780. if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
  781. return true;
  782. }
  783. for (i = 0; i < v->rxtx_rdma_channels; ++i)
  784. if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
  785. return true;
  786. for (i = 0; i < v->rxtx_wrdma_channels; ++i)
  787. if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
  788. LPASS_CDC_DMA_TX3))
  789. return true;
  790. return false;
  791. }
  792. static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
  793. {
  794. struct lpass_data *drvdata = dev_get_drvdata(dev);
  795. struct lpass_variant *v = drvdata->variant;
  796. int i;
  797. for (i = 0; i < v->va_irq_ports; ++i) {
  798. if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
  799. return true;
  800. if (reg == LPAIF_VA_IRQEN_REG(v, i))
  801. return true;
  802. if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
  803. return true;
  804. }
  805. for (i = 0; i < v->va_wrdma_channels; ++i) {
  806. if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
  807. LPASS_CDC_DMA_VA_TX0))
  808. return true;
  809. if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
  810. LPASS_CDC_DMA_VA_TX0))
  811. return true;
  812. if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
  813. LPASS_CDC_DMA_VA_TX0))
  814. return true;
  815. if (rw == LPASS_REG_READ) {
  816. if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
  817. LPASS_CDC_DMA_VA_TX0))
  818. return true;
  819. }
  820. if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
  821. LPASS_CDC_DMA_VA_TX0))
  822. return true;
  823. if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
  824. LPASS_CDC_DMA_VA_TX0))
  825. return true;
  826. }
  827. return false;
  828. }
  829. static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg)
  830. {
  831. return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);
  832. }
  833. static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg)
  834. {
  835. return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);
  836. }
  837. static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg)
  838. {
  839. struct lpass_data *drvdata = dev_get_drvdata(dev);
  840. struct lpass_variant *v = drvdata->variant;
  841. int i;
  842. for (i = 0; i < v->va_irq_ports; ++i) {
  843. if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
  844. return true;
  845. if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
  846. return true;
  847. }
  848. for (i = 0; i < v->va_wrdma_channels; ++i) {
  849. if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
  850. LPASS_CDC_DMA_VA_TX0))
  851. return true;
  852. }
  853. return false;
  854. }
  855. static struct regmap_config lpass_rxtx_regmap_config = {
  856. .reg_bits = 32,
  857. .reg_stride = 4,
  858. .val_bits = 32,
  859. .writeable_reg = lpass_rxtx_regmap_writeable,
  860. .readable_reg = lpass_rxtx_regmap_readable,
  861. .volatile_reg = lpass_rxtx_regmap_volatile,
  862. .cache_type = REGCACHE_FLAT,
  863. };
  864. static struct regmap_config lpass_va_regmap_config = {
  865. .reg_bits = 32,
  866. .reg_stride = 4,
  867. .val_bits = 32,
  868. .writeable_reg = lpass_va_regmap_writeable,
  869. .readable_reg = lpass_va_regmap_readable,
  870. .volatile_reg = lpass_va_regmap_volatile,
  871. .cache_type = REGCACHE_FLAT,
  872. };
  873. static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
  874. struct device_node *node,
  875. const char *name)
  876. {
  877. unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
  878. unsigned int sd_line_mask = 0;
  879. int num_lines, i;
  880. num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
  881. LPASS_CPU_MAX_MI2S_LINES);
  882. if (num_lines < 0)
  883. return LPAIF_I2SCTL_MODE_NONE;
  884. for (i = 0; i < num_lines; i++)
  885. sd_line_mask |= BIT(lines[i]);
  886. switch (sd_line_mask) {
  887. case LPASS_CPU_I2S_SD0_MASK:
  888. return LPAIF_I2SCTL_MODE_SD0;
  889. case LPASS_CPU_I2S_SD1_MASK:
  890. return LPAIF_I2SCTL_MODE_SD1;
  891. case LPASS_CPU_I2S_SD2_MASK:
  892. return LPAIF_I2SCTL_MODE_SD2;
  893. case LPASS_CPU_I2S_SD3_MASK:
  894. return LPAIF_I2SCTL_MODE_SD3;
  895. case LPASS_CPU_I2S_SD0_1_MASK:
  896. return LPAIF_I2SCTL_MODE_QUAD01;
  897. case LPASS_CPU_I2S_SD2_3_MASK:
  898. return LPAIF_I2SCTL_MODE_QUAD23;
  899. case LPASS_CPU_I2S_SD0_1_2_MASK:
  900. return LPAIF_I2SCTL_MODE_6CH;
  901. case LPASS_CPU_I2S_SD0_1_2_3_MASK:
  902. return LPAIF_I2SCTL_MODE_8CH;
  903. default:
  904. dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
  905. return LPAIF_I2SCTL_MODE_NONE;
  906. }
  907. }
  908. static void of_lpass_cpu_parse_dai_data(struct device *dev,
  909. struct lpass_data *data)
  910. {
  911. struct device_node *node;
  912. int ret, i, id;
  913. /* Allow all channels by default for backwards compatibility */
  914. for (i = 0; i < data->variant->num_dai; i++) {
  915. id = data->variant->dai_driver[i].id;
  916. data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
  917. data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
  918. }
  919. for_each_child_of_node(dev->of_node, node) {
  920. ret = of_property_read_u32(node, "reg", &id);
  921. if (ret || id < 0) {
  922. dev_err(dev, "valid dai id not found: %d\n", ret);
  923. continue;
  924. }
  925. if (id == LPASS_DP_RX) {
  926. data->hdmi_port_enable = 1;
  927. } else if (is_cdc_dma_port(id)) {
  928. data->codec_dma_enable = 1;
  929. } else {
  930. data->mi2s_playback_sd_mode[id] =
  931. of_lpass_cpu_parse_sd_lines(dev, node,
  932. "qcom,playback-sd-lines");
  933. data->mi2s_capture_sd_mode[id] =
  934. of_lpass_cpu_parse_sd_lines(dev, node,
  935. "qcom,capture-sd-lines");
  936. }
  937. }
  938. }
  939. static int of_lpass_cdc_dma_clks_parse(struct device *dev,
  940. struct lpass_data *data)
  941. {
  942. data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0");
  943. if (IS_ERR(data->codec_mem0))
  944. return PTR_ERR(data->codec_mem0);
  945. data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1");
  946. if (IS_ERR(data->codec_mem1))
  947. return PTR_ERR(data->codec_mem1);
  948. data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2");
  949. if (IS_ERR(data->codec_mem2))
  950. return PTR_ERR(data->codec_mem2);
  951. data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0");
  952. if (IS_ERR(data->va_mem0))
  953. return PTR_ERR(data->va_mem0);
  954. return 0;
  955. }
  956. int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
  957. {
  958. struct lpass_data *drvdata;
  959. struct device_node *dsp_of_node;
  960. struct resource *res;
  961. struct lpass_variant *variant;
  962. struct device *dev = &pdev->dev;
  963. const struct of_device_id *match;
  964. int ret, i, dai_id;
  965. dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
  966. if (dsp_of_node) {
  967. dev_err(dev, "DSP exists and holds audio resources\n");
  968. of_node_put(dsp_of_node);
  969. return -EBUSY;
  970. }
  971. drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
  972. if (!drvdata)
  973. return -ENOMEM;
  974. platform_set_drvdata(pdev, drvdata);
  975. match = of_match_device(dev->driver->of_match_table, dev);
  976. if (!match || !match->data)
  977. return -EINVAL;
  978. if (of_device_is_compatible(dev->of_node, "qcom,lpass-cpu-apq8016")) {
  979. dev_warn(dev, "%s compatible is deprecated\n",
  980. match->compatible);
  981. }
  982. drvdata->variant = (struct lpass_variant *)match->data;
  983. variant = drvdata->variant;
  984. of_lpass_cpu_parse_dai_data(dev, drvdata);
  985. if (drvdata->codec_dma_enable) {
  986. drvdata->rxtx_lpaif =
  987. devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif");
  988. if (IS_ERR(drvdata->rxtx_lpaif))
  989. return PTR_ERR(drvdata->rxtx_lpaif);
  990. drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif");
  991. if (IS_ERR(drvdata->va_lpaif))
  992. return PTR_ERR(drvdata->va_lpaif);
  993. lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant,
  994. variant->rxtx_wrdma_channels +
  995. variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);
  996. drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif,
  997. &lpass_rxtx_regmap_config);
  998. if (IS_ERR(drvdata->rxtx_lpaif_map))
  999. return PTR_ERR(drvdata->rxtx_lpaif_map);
  1000. lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant,
  1001. variant->va_wrdma_channels +
  1002. variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);
  1003. drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif,
  1004. &lpass_va_regmap_config);
  1005. if (IS_ERR(drvdata->va_lpaif_map))
  1006. return PTR_ERR(drvdata->va_lpaif_map);
  1007. ret = of_lpass_cdc_dma_clks_parse(dev, drvdata);
  1008. if (ret) {
  1009. dev_err(dev, "failed to get cdc dma clocks %d\n", ret);
  1010. return ret;
  1011. }
  1012. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm");
  1013. drvdata->rxtx_cdc_dma_lpm_buf = res->start;
  1014. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm");
  1015. drvdata->va_cdc_dma_lpm_buf = res->start;
  1016. }
  1017. drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");
  1018. if (IS_ERR(drvdata->lpaif))
  1019. return PTR_ERR(drvdata->lpaif);
  1020. lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
  1021. variant->wrdma_channels +
  1022. variant->wrdma_channel_start);
  1023. drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
  1024. &lpass_cpu_regmap_config);
  1025. if (IS_ERR(drvdata->lpaif_map)) {
  1026. dev_err(dev, "error initializing regmap: %ld\n",
  1027. PTR_ERR(drvdata->lpaif_map));
  1028. return PTR_ERR(drvdata->lpaif_map);
  1029. }
  1030. if (drvdata->hdmi_port_enable) {
  1031. drvdata->hdmiif = devm_platform_ioremap_resource_byname(pdev, "lpass-hdmiif");
  1032. if (IS_ERR(drvdata->hdmiif))
  1033. return PTR_ERR(drvdata->hdmiif);
  1034. lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
  1035. variant->hdmi_rdma_channels - 1);
  1036. drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
  1037. &lpass_hdmi_regmap_config);
  1038. if (IS_ERR(drvdata->hdmiif_map)) {
  1039. dev_err(dev, "error initializing regmap: %ld\n",
  1040. PTR_ERR(drvdata->hdmiif_map));
  1041. return PTR_ERR(drvdata->hdmiif_map);
  1042. }
  1043. }
  1044. if (variant->init) {
  1045. ret = variant->init(pdev);
  1046. if (ret) {
  1047. dev_err(dev, "error initializing variant: %d\n", ret);
  1048. return ret;
  1049. }
  1050. }
  1051. for (i = 0; i < variant->num_dai; i++) {
  1052. dai_id = variant->dai_driver[i].id;
  1053. if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))
  1054. continue;
  1055. drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
  1056. variant->dai_osr_clk_names[i]);
  1057. drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
  1058. variant->dai_bit_clk_names[i]);
  1059. if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
  1060. dev_err(dev,
  1061. "error getting %s: %ld\n",
  1062. variant->dai_bit_clk_names[i],
  1063. PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
  1064. return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
  1065. }
  1066. if (drvdata->mi2s_playback_sd_mode[dai_id] ==
  1067. LPAIF_I2SCTL_MODE_QUAD01) {
  1068. variant->dai_driver[dai_id].playback.channels_min = 4;
  1069. variant->dai_driver[dai_id].playback.channels_max = 4;
  1070. }
  1071. }
  1072. /* Allocation for i2sctl regmap fields */
  1073. drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
  1074. GFP_KERNEL);
  1075. /* Initialize bitfields for dai I2SCTL register */
  1076. ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
  1077. drvdata->lpaif_map);
  1078. if (ret) {
  1079. dev_err(dev, "error init i2sctl field: %d\n", ret);
  1080. return ret;
  1081. }
  1082. if (drvdata->hdmi_port_enable) {
  1083. ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
  1084. if (ret) {
  1085. dev_err(dev, "%s error hdmi init failed\n", __func__);
  1086. return ret;
  1087. }
  1088. }
  1089. ret = devm_snd_soc_register_component(dev,
  1090. &lpass_cpu_comp_driver,
  1091. variant->dai_driver,
  1092. variant->num_dai);
  1093. if (ret) {
  1094. dev_err(dev, "error registering cpu driver: %d\n", ret);
  1095. goto err;
  1096. }
  1097. ret = asoc_qcom_lpass_platform_register(pdev);
  1098. if (ret) {
  1099. dev_err(dev, "error registering platform driver: %d\n", ret);
  1100. goto err;
  1101. }
  1102. err:
  1103. return ret;
  1104. }
  1105. EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
  1106. int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
  1107. {
  1108. struct lpass_data *drvdata = platform_get_drvdata(pdev);
  1109. if (drvdata->variant->exit)
  1110. drvdata->variant->exit(pdev);
  1111. return 0;
  1112. }
  1113. EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
  1114. void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
  1115. {
  1116. struct lpass_data *drvdata = platform_get_drvdata(pdev);
  1117. if (drvdata->variant->exit)
  1118. drvdata->variant->exit(pdev);
  1119. }
  1120. EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
  1121. MODULE_DESCRIPTION("QTi LPASS CPU Driver");
  1122. MODULE_LICENSE("GPL v2");