pxa2xx-i2s.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  4. *
  5. * Copyright 2005 Wolfson Microelectronics PLC.
  6. * Author: Liam Girdwood
  7. * [email protected]
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/device.h>
  12. #include <linux/delay.h>
  13. #include <linux/clk.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/initval.h>
  19. #include <sound/soc.h>
  20. #include <sound/pxa2xx-lib.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include <linux/platform_data/asoc-pxa.h>
  23. #include "pxa2xx-i2s.h"
  24. /*
  25. * I2S Controller Register and Bit Definitions
  26. */
  27. #define SACR0 (0x0000) /* Global Control Register */
  28. #define SACR1 (0x0004) /* Serial Audio I 2 S/MSB-Justified Control Register */
  29. #define SASR0 (0x000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
  30. #define SAIMR (0x0014) /* Serial Audio Interrupt Mask Register */
  31. #define SAICR (0x0018) /* Serial Audio Interrupt Clear Register */
  32. #define SADIV (0x0060) /* Audio Clock Divider Register. */
  33. #define SADR (0x0080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
  34. #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
  35. #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
  36. #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
  37. #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
  38. #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
  39. #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
  40. #define SACR0_ENB (1 << 0) /* Enable I2S Link */
  41. #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
  42. #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
  43. #define SACR1_DREC (1 << 3) /* Disable Recording Function */
  44. #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
  45. #define SASR0_I2SOFF (1 << 7) /* Controller Status */
  46. #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
  47. #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
  48. #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
  49. #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
  50. #define SASR0_BSY (1 << 2) /* I2S Busy */
  51. #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
  52. #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
  53. #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
  54. #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
  55. #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
  56. #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
  57. #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
  58. #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
  59. struct pxa_i2s_port {
  60. u32 sadiv;
  61. u32 sacr0;
  62. u32 sacr1;
  63. u32 saimr;
  64. int master;
  65. u32 fmt;
  66. };
  67. static struct pxa_i2s_port pxa_i2s;
  68. static struct clk *clk_i2s;
  69. static int clk_ena = 0;
  70. static void __iomem *i2s_reg_base;
  71. static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
  72. .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  73. .chan_name = "tx",
  74. .maxburst = 32,
  75. };
  76. static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
  77. .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  78. .chan_name = "rx",
  79. .maxburst = 32,
  80. };
  81. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
  82. struct snd_soc_dai *dai)
  83. {
  84. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  85. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  86. if (IS_ERR(clk_i2s))
  87. return PTR_ERR(clk_i2s);
  88. if (!snd_soc_dai_active(cpu_dai))
  89. writel(0, i2s_reg_base + SACR0);
  90. return 0;
  91. }
  92. /* wait for I2S controller to be ready */
  93. static int pxa_i2s_wait(void)
  94. {
  95. int i;
  96. /* flush the Rx FIFO */
  97. for (i = 0; i < 16; i++)
  98. readl(i2s_reg_base + SADR);
  99. return 0;
  100. }
  101. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  102. unsigned int fmt)
  103. {
  104. /* interface format */
  105. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  106. case SND_SOC_DAIFMT_I2S:
  107. pxa_i2s.fmt = 0;
  108. break;
  109. case SND_SOC_DAIFMT_LEFT_J:
  110. pxa_i2s.fmt = SACR1_AMSL;
  111. break;
  112. }
  113. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  114. case SND_SOC_DAIFMT_BP_FP:
  115. pxa_i2s.master = 1;
  116. break;
  117. case SND_SOC_DAIFMT_BC_FP:
  118. pxa_i2s.master = 0;
  119. break;
  120. default:
  121. break;
  122. }
  123. return 0;
  124. }
  125. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  126. int clk_id, unsigned int freq, int dir)
  127. {
  128. if (clk_id != PXA2XX_I2S_SYSCLK)
  129. return -ENODEV;
  130. return 0;
  131. }
  132. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  133. struct snd_pcm_hw_params *params,
  134. struct snd_soc_dai *dai)
  135. {
  136. struct snd_dmaengine_dai_dma_data *dma_data;
  137. if (WARN_ON(IS_ERR(clk_i2s)))
  138. return -EINVAL;
  139. clk_prepare_enable(clk_i2s);
  140. clk_ena = 1;
  141. pxa_i2s_wait();
  142. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  143. dma_data = &pxa2xx_i2s_pcm_stereo_out;
  144. else
  145. dma_data = &pxa2xx_i2s_pcm_stereo_in;
  146. snd_soc_dai_set_dma_data(dai, substream, dma_data);
  147. /* is port used by another stream */
  148. if (!(SACR0 & SACR0_ENB)) {
  149. writel(0, i2s_reg_base + SACR0);
  150. if (pxa_i2s.master)
  151. writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0);
  152. writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0);
  153. writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1);
  154. }
  155. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  156. writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR);
  157. else
  158. writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR);
  159. switch (params_rate(params)) {
  160. case 8000:
  161. writel(0x48, i2s_reg_base + SADIV);
  162. break;
  163. case 11025:
  164. writel(0x34, i2s_reg_base + SADIV);
  165. break;
  166. case 16000:
  167. writel(0x24, i2s_reg_base + SADIV);
  168. break;
  169. case 22050:
  170. writel(0x1a, i2s_reg_base + SADIV);
  171. break;
  172. case 44100:
  173. writel(0xd, i2s_reg_base + SADIV);
  174. break;
  175. case 48000:
  176. writel(0xc, i2s_reg_base + SADIV);
  177. break;
  178. case 96000: /* not in manual and possibly slightly inaccurate */
  179. writel(0x6, i2s_reg_base + SADIV);
  180. break;
  181. }
  182. return 0;
  183. }
  184. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  185. struct snd_soc_dai *dai)
  186. {
  187. int ret = 0;
  188. switch (cmd) {
  189. case SNDRV_PCM_TRIGGER_START:
  190. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  191. writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1);
  192. else
  193. writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1);
  194. writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0);
  195. break;
  196. case SNDRV_PCM_TRIGGER_RESUME:
  197. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  198. case SNDRV_PCM_TRIGGER_STOP:
  199. case SNDRV_PCM_TRIGGER_SUSPEND:
  200. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  201. break;
  202. default:
  203. ret = -EINVAL;
  204. }
  205. return ret;
  206. }
  207. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
  208. struct snd_soc_dai *dai)
  209. {
  210. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  211. writel(readl(i2s_reg_base + SACR1) | (SACR1_DRPL), i2s_reg_base + SACR1);
  212. writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_TFS), i2s_reg_base + SAIMR);
  213. } else {
  214. writel(readl(i2s_reg_base + SACR1) | (SACR1_DREC), i2s_reg_base + SACR1);
  215. writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_RFS), i2s_reg_base + SAIMR);
  216. }
  217. if ((readl(i2s_reg_base + SACR1) & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
  218. writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
  219. pxa_i2s_wait();
  220. if (clk_ena) {
  221. clk_disable_unprepare(clk_i2s);
  222. clk_ena = 0;
  223. }
  224. }
  225. }
  226. #ifdef CONFIG_PM
  227. static int pxa2xx_soc_pcm_suspend(struct snd_soc_component *component)
  228. {
  229. /* store registers */
  230. pxa_i2s.sacr0 = readl(i2s_reg_base + SACR0);
  231. pxa_i2s.sacr1 = readl(i2s_reg_base + SACR1);
  232. pxa_i2s.saimr = readl(i2s_reg_base + SAIMR);
  233. pxa_i2s.sadiv = readl(i2s_reg_base + SADIV);
  234. /* deactivate link */
  235. writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
  236. pxa_i2s_wait();
  237. return 0;
  238. }
  239. static int pxa2xx_soc_pcm_resume(struct snd_soc_component *component)
  240. {
  241. pxa_i2s_wait();
  242. writel(pxa_i2s.sacr0 & ~SACR0_ENB, i2s_reg_base + SACR0);
  243. writel(pxa_i2s.sacr1, i2s_reg_base + SACR1);
  244. writel(pxa_i2s.saimr, i2s_reg_base + SAIMR);
  245. writel(pxa_i2s.sadiv, i2s_reg_base + SADIV);
  246. writel(pxa_i2s.sacr0, i2s_reg_base + SACR0);
  247. return 0;
  248. }
  249. #else
  250. #define pxa2xx_soc_pcm_suspend NULL
  251. #define pxa2xx_soc_pcm_resume NULL
  252. #endif
  253. static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
  254. {
  255. clk_i2s = clk_get(dai->dev, "I2SCLK");
  256. if (IS_ERR(clk_i2s))
  257. return PTR_ERR(clk_i2s);
  258. /*
  259. * PXA Developer's Manual:
  260. * If SACR0[ENB] is toggled in the middle of a normal operation,
  261. * the SACR0[RST] bit must also be set and cleared to reset all
  262. * I2S controller registers.
  263. */
  264. writel(SACR0_RST, i2s_reg_base + SACR0);
  265. writel(0, i2s_reg_base + SACR0);
  266. /* Make sure RPL and REC are disabled */
  267. writel(SACR1_DRPL | SACR1_DREC, i2s_reg_base + SACR1);
  268. /* Along with FIFO servicing */
  269. writel(readl(i2s_reg_base + SAIMR) & (~(SAIMR_RFS | SAIMR_TFS)), i2s_reg_base + SAIMR);
  270. snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
  271. &pxa2xx_i2s_pcm_stereo_in);
  272. return 0;
  273. }
  274. static int pxa2xx_i2s_remove(struct snd_soc_dai *dai)
  275. {
  276. clk_put(clk_i2s);
  277. clk_i2s = ERR_PTR(-ENOENT);
  278. return 0;
  279. }
  280. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  281. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  282. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  283. static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
  284. .startup = pxa2xx_i2s_startup,
  285. .shutdown = pxa2xx_i2s_shutdown,
  286. .trigger = pxa2xx_i2s_trigger,
  287. .hw_params = pxa2xx_i2s_hw_params,
  288. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  289. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  290. };
  291. static struct snd_soc_dai_driver pxa_i2s_dai = {
  292. .probe = pxa2xx_i2s_probe,
  293. .remove = pxa2xx_i2s_remove,
  294. .playback = {
  295. .channels_min = 2,
  296. .channels_max = 2,
  297. .rates = PXA2XX_I2S_RATES,
  298. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  299. .capture = {
  300. .channels_min = 2,
  301. .channels_max = 2,
  302. .rates = PXA2XX_I2S_RATES,
  303. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  304. .ops = &pxa_i2s_dai_ops,
  305. .symmetric_rate = 1,
  306. };
  307. static const struct snd_soc_component_driver pxa_i2s_component = {
  308. .name = "pxa-i2s",
  309. .pcm_construct = pxa2xx_soc_pcm_new,
  310. .open = pxa2xx_soc_pcm_open,
  311. .close = pxa2xx_soc_pcm_close,
  312. .hw_params = pxa2xx_soc_pcm_hw_params,
  313. .prepare = pxa2xx_soc_pcm_prepare,
  314. .trigger = pxa2xx_soc_pcm_trigger,
  315. .pointer = pxa2xx_soc_pcm_pointer,
  316. .suspend = pxa2xx_soc_pcm_suspend,
  317. .resume = pxa2xx_soc_pcm_resume,
  318. .legacy_dai_naming = 1,
  319. };
  320. static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
  321. {
  322. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  323. if (!res) {
  324. dev_err(&pdev->dev, "missing MMIO resource\n");
  325. return -ENXIO;
  326. }
  327. i2s_reg_base = devm_ioremap_resource(&pdev->dev, res);
  328. if (IS_ERR(i2s_reg_base)) {
  329. dev_err(&pdev->dev, "ioremap failed\n");
  330. return PTR_ERR(i2s_reg_base);
  331. }
  332. pxa2xx_i2s_pcm_stereo_out.addr = res->start + SADR;
  333. pxa2xx_i2s_pcm_stereo_in.addr = res->start + SADR;
  334. return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
  335. &pxa_i2s_dai, 1);
  336. }
  337. static struct platform_driver pxa2xx_i2s_driver = {
  338. .probe = pxa2xx_i2s_drv_probe,
  339. .driver = {
  340. .name = "pxa2xx-i2s",
  341. },
  342. };
  343. static int __init pxa2xx_i2s_init(void)
  344. {
  345. clk_i2s = ERR_PTR(-ENOENT);
  346. return platform_driver_register(&pxa2xx_i2s_driver);
  347. }
  348. static void __exit pxa2xx_i2s_exit(void)
  349. {
  350. platform_driver_unregister(&pxa2xx_i2s_driver);
  351. }
  352. module_init(pxa2xx_i2s_init);
  353. module_exit(pxa2xx_i2s_exit);
  354. /* Module information */
  355. MODULE_AUTHOR("Liam Girdwood, [email protected]");
  356. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  357. MODULE_LICENSE("GPL");
  358. MODULE_ALIAS("platform:pxa2xx-i2s");