mxs-saif.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/init.h>
  7. #include <linux/of.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/time.h>
  17. #include <sound/core.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include "mxs-saif.h"
  22. #define MXS_SET_ADDR 0x4
  23. #define MXS_CLR_ADDR 0x8
  24. static struct mxs_saif *mxs_saif[2];
  25. /*
  26. * SAIF is a little different with other normal SOC DAIs on clock using.
  27. *
  28. * For MXS, two SAIF modules are instantiated on-chip.
  29. * Each SAIF has a set of clock pins and can be operating in master
  30. * mode simultaneously if they are connected to different off-chip codecs.
  31. * Also, one of the two SAIFs can master or drive the clock pins while the
  32. * other SAIF, in slave mode, receives clocking from the master SAIF.
  33. * This also means that both SAIFs must operate at the same sample rate.
  34. *
  35. * We abstract this as each saif has a master, the master could be
  36. * itself or other saifs. In the generic saif driver, saif does not need
  37. * to know the different clkmux. Saif only needs to know who is its master
  38. * and operating its master to generate the proper clock rate for it.
  39. * The master id is provided in mach-specific layer according to different
  40. * clkmux setting.
  41. */
  42. static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  43. int clk_id, unsigned int freq, int dir)
  44. {
  45. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  46. switch (clk_id) {
  47. case MXS_SAIF_MCLK:
  48. saif->mclk = freq;
  49. break;
  50. default:
  51. return -EINVAL;
  52. }
  53. return 0;
  54. }
  55. /*
  56. * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
  57. * is provided by other SAIF, we provide a interface here to get its master
  58. * from its master_id.
  59. * Note that the master could be itself.
  60. */
  61. static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
  62. {
  63. return mxs_saif[saif->master_id];
  64. }
  65. /*
  66. * Set SAIF clock and MCLK
  67. */
  68. static int mxs_saif_set_clk(struct mxs_saif *saif,
  69. unsigned int mclk,
  70. unsigned int rate)
  71. {
  72. u32 scr;
  73. int ret;
  74. struct mxs_saif *master_saif;
  75. dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
  76. /* Set master saif to generate proper clock */
  77. master_saif = mxs_saif_get_master(saif);
  78. if (!master_saif)
  79. return -EINVAL;
  80. dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
  81. /* Checking if can playback and capture simutaneously */
  82. if (master_saif->ongoing && rate != master_saif->cur_rate) {
  83. dev_err(saif->dev,
  84. "can not change clock, master saif%d(rate %d) is ongoing\n",
  85. master_saif->id, master_saif->cur_rate);
  86. return -EINVAL;
  87. }
  88. scr = __raw_readl(master_saif->base + SAIF_CTRL);
  89. scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
  90. scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  91. /*
  92. * Set SAIF clock
  93. *
  94. * The SAIF clock should be either 384*fs or 512*fs.
  95. * If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
  96. * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
  97. * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
  98. *
  99. * If MCLK is not used, we just set saif clk to 512*fs.
  100. */
  101. ret = clk_prepare_enable(master_saif->clk);
  102. if (ret)
  103. return ret;
  104. if (master_saif->mclk_in_use) {
  105. switch (mclk / rate) {
  106. case 32:
  107. case 64:
  108. case 128:
  109. case 256:
  110. case 512:
  111. scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  112. ret = clk_set_rate(master_saif->clk, 512 * rate);
  113. break;
  114. case 48:
  115. case 96:
  116. case 192:
  117. case 384:
  118. scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
  119. ret = clk_set_rate(master_saif->clk, 384 * rate);
  120. break;
  121. default:
  122. /* SAIF MCLK should be a sub-rate of 512x or 384x */
  123. clk_disable_unprepare(master_saif->clk);
  124. return -EINVAL;
  125. }
  126. } else {
  127. ret = clk_set_rate(master_saif->clk, 512 * rate);
  128. scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  129. }
  130. clk_disable_unprepare(master_saif->clk);
  131. if (ret)
  132. return ret;
  133. master_saif->cur_rate = rate;
  134. if (!master_saif->mclk_in_use) {
  135. __raw_writel(scr, master_saif->base + SAIF_CTRL);
  136. return 0;
  137. }
  138. /*
  139. * Program the over-sample rate for MCLK output
  140. *
  141. * The available MCLK range is 32x, 48x... 512x. The rate
  142. * could be from 8kHz to 192kH.
  143. */
  144. switch (mclk / rate) {
  145. case 32:
  146. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
  147. break;
  148. case 64:
  149. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
  150. break;
  151. case 128:
  152. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
  153. break;
  154. case 256:
  155. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
  156. break;
  157. case 512:
  158. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
  159. break;
  160. case 48:
  161. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
  162. break;
  163. case 96:
  164. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
  165. break;
  166. case 192:
  167. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
  168. break;
  169. case 384:
  170. scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
  171. break;
  172. default:
  173. return -EINVAL;
  174. }
  175. __raw_writel(scr, master_saif->base + SAIF_CTRL);
  176. return 0;
  177. }
  178. /*
  179. * Put and disable MCLK.
  180. */
  181. int mxs_saif_put_mclk(unsigned int saif_id)
  182. {
  183. struct mxs_saif *saif = mxs_saif[saif_id];
  184. u32 stat;
  185. if (!saif)
  186. return -EINVAL;
  187. stat = __raw_readl(saif->base + SAIF_STAT);
  188. if (stat & BM_SAIF_STAT_BUSY) {
  189. dev_err(saif->dev, "error: busy\n");
  190. return -EBUSY;
  191. }
  192. clk_disable_unprepare(saif->clk);
  193. /* disable MCLK output */
  194. __raw_writel(BM_SAIF_CTRL_CLKGATE,
  195. saif->base + SAIF_CTRL + MXS_SET_ADDR);
  196. __raw_writel(BM_SAIF_CTRL_RUN,
  197. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  198. saif->mclk_in_use = 0;
  199. return 0;
  200. }
  201. EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
  202. /*
  203. * Get MCLK and set clock rate, then enable it
  204. *
  205. * This interface is used for codecs who are using MCLK provided
  206. * by saif.
  207. */
  208. int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
  209. unsigned int rate)
  210. {
  211. struct mxs_saif *saif = mxs_saif[saif_id];
  212. u32 stat;
  213. int ret;
  214. struct mxs_saif *master_saif;
  215. if (!saif)
  216. return -EINVAL;
  217. /* Clear Reset */
  218. __raw_writel(BM_SAIF_CTRL_SFTRST,
  219. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  220. /* FIXME: need clear clk gate for register r/w */
  221. __raw_writel(BM_SAIF_CTRL_CLKGATE,
  222. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  223. master_saif = mxs_saif_get_master(saif);
  224. if (saif != master_saif) {
  225. dev_err(saif->dev, "can not get mclk from a non-master saif\n");
  226. return -EINVAL;
  227. }
  228. stat = __raw_readl(saif->base + SAIF_STAT);
  229. if (stat & BM_SAIF_STAT_BUSY) {
  230. dev_err(saif->dev, "error: busy\n");
  231. return -EBUSY;
  232. }
  233. saif->mclk_in_use = 1;
  234. ret = mxs_saif_set_clk(saif, mclk, rate);
  235. if (ret)
  236. return ret;
  237. ret = clk_prepare_enable(saif->clk);
  238. if (ret)
  239. return ret;
  240. /* enable MCLK output */
  241. __raw_writel(BM_SAIF_CTRL_RUN,
  242. saif->base + SAIF_CTRL + MXS_SET_ADDR);
  243. return 0;
  244. }
  245. EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
  246. /*
  247. * SAIF DAI format configuration.
  248. * Should only be called when port is inactive.
  249. */
  250. static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  251. {
  252. u32 scr, stat;
  253. u32 scr0;
  254. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  255. stat = __raw_readl(saif->base + SAIF_STAT);
  256. if (stat & BM_SAIF_STAT_BUSY) {
  257. dev_err(cpu_dai->dev, "error: busy\n");
  258. return -EBUSY;
  259. }
  260. /* If SAIF1 is configured as slave, the clk gate needs to be cleared
  261. * before the register can be written.
  262. */
  263. if (saif->id != saif->master_id) {
  264. __raw_writel(BM_SAIF_CTRL_SFTRST,
  265. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  266. __raw_writel(BM_SAIF_CTRL_CLKGATE,
  267. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  268. }
  269. scr0 = __raw_readl(saif->base + SAIF_CTRL);
  270. scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
  271. & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
  272. scr = 0;
  273. /* DAI mode */
  274. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  275. case SND_SOC_DAIFMT_I2S:
  276. /* data frame low 1clk before data */
  277. scr |= BM_SAIF_CTRL_DELAY;
  278. scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
  279. break;
  280. case SND_SOC_DAIFMT_LEFT_J:
  281. /* data frame high with data */
  282. scr &= ~BM_SAIF_CTRL_DELAY;
  283. scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
  284. scr &= ~BM_SAIF_CTRL_JUSTIFY;
  285. break;
  286. default:
  287. return -EINVAL;
  288. }
  289. /* DAI clock inversion */
  290. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  291. case SND_SOC_DAIFMT_IB_IF:
  292. scr |= BM_SAIF_CTRL_BITCLK_EDGE;
  293. scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
  294. break;
  295. case SND_SOC_DAIFMT_IB_NF:
  296. scr |= BM_SAIF_CTRL_BITCLK_EDGE;
  297. scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
  298. break;
  299. case SND_SOC_DAIFMT_NB_IF:
  300. scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
  301. scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
  302. break;
  303. case SND_SOC_DAIFMT_NB_NF:
  304. scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
  305. scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
  306. break;
  307. }
  308. /*
  309. * Note: We simply just support master mode since SAIF TX can only
  310. * work as master.
  311. * Here the master is relative to codec side.
  312. * Saif internally could be slave when working on EXTMASTER mode.
  313. * We just hide this to machine driver.
  314. */
  315. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  316. case SND_SOC_DAIFMT_BP_FP:
  317. if (saif->id == saif->master_id)
  318. scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
  319. else
  320. scr |= BM_SAIF_CTRL_SLAVE_MODE;
  321. __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
  322. break;
  323. default:
  324. return -EINVAL;
  325. }
  326. return 0;
  327. }
  328. static int mxs_saif_startup(struct snd_pcm_substream *substream,
  329. struct snd_soc_dai *cpu_dai)
  330. {
  331. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  332. int ret;
  333. /* clear error status to 0 for each re-open */
  334. saif->fifo_underrun = 0;
  335. saif->fifo_overrun = 0;
  336. /* Clear Reset for normal operations */
  337. __raw_writel(BM_SAIF_CTRL_SFTRST,
  338. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  339. /* clear clock gate */
  340. __raw_writel(BM_SAIF_CTRL_CLKGATE,
  341. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  342. ret = clk_prepare(saif->clk);
  343. if (ret)
  344. return ret;
  345. return 0;
  346. }
  347. static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
  348. struct snd_soc_dai *cpu_dai)
  349. {
  350. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  351. clk_unprepare(saif->clk);
  352. }
  353. /*
  354. * Should only be called when port is inactive.
  355. * although can be called multiple times by upper layers.
  356. */
  357. static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
  358. struct snd_pcm_hw_params *params,
  359. struct snd_soc_dai *cpu_dai)
  360. {
  361. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  362. struct mxs_saif *master_saif;
  363. u32 scr, stat;
  364. int ret;
  365. master_saif = mxs_saif_get_master(saif);
  366. if (!master_saif)
  367. return -EINVAL;
  368. /* mclk should already be set */
  369. if (!saif->mclk && saif->mclk_in_use) {
  370. dev_err(cpu_dai->dev, "set mclk first\n");
  371. return -EINVAL;
  372. }
  373. stat = __raw_readl(saif->base + SAIF_STAT);
  374. if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
  375. dev_err(cpu_dai->dev, "error: busy\n");
  376. return -EBUSY;
  377. }
  378. /*
  379. * Set saif clk based on sample rate.
  380. * If mclk is used, we also set mclk, if not, saif->mclk is
  381. * default 0, means not used.
  382. */
  383. ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
  384. if (ret) {
  385. dev_err(cpu_dai->dev, "unable to get proper clk\n");
  386. return ret;
  387. }
  388. if (saif != master_saif) {
  389. /*
  390. * Set an initial clock rate for the saif internal logic to work
  391. * properly. This is important when working in EXTMASTER mode
  392. * that uses the other saif's BITCLK&LRCLK but it still needs a
  393. * basic clock which should be fast enough for the internal
  394. * logic.
  395. */
  396. ret = clk_enable(saif->clk);
  397. if (ret)
  398. return ret;
  399. ret = clk_set_rate(saif->clk, 24000000);
  400. clk_disable(saif->clk);
  401. if (ret)
  402. return ret;
  403. ret = clk_prepare(master_saif->clk);
  404. if (ret)
  405. return ret;
  406. }
  407. scr = __raw_readl(saif->base + SAIF_CTRL);
  408. scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
  409. scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
  410. switch (params_format(params)) {
  411. case SNDRV_PCM_FORMAT_S16_LE:
  412. scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
  413. break;
  414. case SNDRV_PCM_FORMAT_S20_3LE:
  415. scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
  416. scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
  417. break;
  418. case SNDRV_PCM_FORMAT_S24_LE:
  419. scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
  420. scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
  421. break;
  422. default:
  423. return -EINVAL;
  424. }
  425. /* Tx/Rx config */
  426. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  427. /* enable TX mode */
  428. scr &= ~BM_SAIF_CTRL_READ_MODE;
  429. } else {
  430. /* enable RX mode */
  431. scr |= BM_SAIF_CTRL_READ_MODE;
  432. }
  433. __raw_writel(scr, saif->base + SAIF_CTRL);
  434. return 0;
  435. }
  436. static int mxs_saif_prepare(struct snd_pcm_substream *substream,
  437. struct snd_soc_dai *cpu_dai)
  438. {
  439. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  440. /* enable FIFO error irqs */
  441. __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
  442. saif->base + SAIF_CTRL + MXS_SET_ADDR);
  443. return 0;
  444. }
  445. static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
  446. struct snd_soc_dai *cpu_dai)
  447. {
  448. struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  449. struct mxs_saif *master_saif;
  450. u32 delay;
  451. int ret;
  452. master_saif = mxs_saif_get_master(saif);
  453. if (!master_saif)
  454. return -EINVAL;
  455. switch (cmd) {
  456. case SNDRV_PCM_TRIGGER_START:
  457. case SNDRV_PCM_TRIGGER_RESUME:
  458. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  459. if (saif->state == MXS_SAIF_STATE_RUNNING)
  460. return 0;
  461. dev_dbg(cpu_dai->dev, "start\n");
  462. ret = clk_enable(master_saif->clk);
  463. if (ret) {
  464. dev_err(saif->dev, "Failed to enable master clock\n");
  465. return ret;
  466. }
  467. /*
  468. * If the saif's master is not itself, we also need to enable
  469. * itself clk for its internal basic logic to work.
  470. */
  471. if (saif != master_saif) {
  472. ret = clk_enable(saif->clk);
  473. if (ret) {
  474. dev_err(saif->dev, "Failed to enable master clock\n");
  475. clk_disable(master_saif->clk);
  476. return ret;
  477. }
  478. __raw_writel(BM_SAIF_CTRL_RUN,
  479. saif->base + SAIF_CTRL + MXS_SET_ADDR);
  480. }
  481. if (!master_saif->mclk_in_use)
  482. __raw_writel(BM_SAIF_CTRL_RUN,
  483. master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
  484. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  485. /*
  486. * write data to saif data register to trigger
  487. * the transfer.
  488. * For 24-bit format the 32-bit FIFO register stores
  489. * only one channel, so we need to write twice.
  490. * This is also safe for the other non 24-bit formats.
  491. */
  492. __raw_writel(0, saif->base + SAIF_DATA);
  493. __raw_writel(0, saif->base + SAIF_DATA);
  494. } else {
  495. /*
  496. * read data from saif data register to trigger
  497. * the receive.
  498. * For 24-bit format the 32-bit FIFO register stores
  499. * only one channel, so we need to read twice.
  500. * This is also safe for the other non 24-bit formats.
  501. */
  502. __raw_readl(saif->base + SAIF_DATA);
  503. __raw_readl(saif->base + SAIF_DATA);
  504. }
  505. master_saif->ongoing = 1;
  506. saif->state = MXS_SAIF_STATE_RUNNING;
  507. dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
  508. __raw_readl(saif->base + SAIF_CTRL),
  509. __raw_readl(saif->base + SAIF_STAT));
  510. dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
  511. __raw_readl(master_saif->base + SAIF_CTRL),
  512. __raw_readl(master_saif->base + SAIF_STAT));
  513. break;
  514. case SNDRV_PCM_TRIGGER_SUSPEND:
  515. case SNDRV_PCM_TRIGGER_STOP:
  516. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  517. if (saif->state == MXS_SAIF_STATE_STOPPED)
  518. return 0;
  519. dev_dbg(cpu_dai->dev, "stop\n");
  520. /* wait a while for the current sample to complete */
  521. delay = USEC_PER_SEC / master_saif->cur_rate;
  522. if (!master_saif->mclk_in_use) {
  523. __raw_writel(BM_SAIF_CTRL_RUN,
  524. master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  525. udelay(delay);
  526. }
  527. clk_disable(master_saif->clk);
  528. if (saif != master_saif) {
  529. __raw_writel(BM_SAIF_CTRL_RUN,
  530. saif->base + SAIF_CTRL + MXS_CLR_ADDR);
  531. udelay(delay);
  532. clk_disable(saif->clk);
  533. }
  534. master_saif->ongoing = 0;
  535. saif->state = MXS_SAIF_STATE_STOPPED;
  536. break;
  537. default:
  538. return -EINVAL;
  539. }
  540. return 0;
  541. }
  542. #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
  543. #define MXS_SAIF_FORMATS \
  544. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  545. SNDRV_PCM_FMTBIT_S24_LE)
  546. static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
  547. .startup = mxs_saif_startup,
  548. .shutdown = mxs_saif_shutdown,
  549. .trigger = mxs_saif_trigger,
  550. .prepare = mxs_saif_prepare,
  551. .hw_params = mxs_saif_hw_params,
  552. .set_sysclk = mxs_saif_set_dai_sysclk,
  553. .set_fmt = mxs_saif_set_dai_fmt,
  554. };
  555. static struct snd_soc_dai_driver mxs_saif_dai = {
  556. .name = "mxs-saif",
  557. .playback = {
  558. .channels_min = 2,
  559. .channels_max = 2,
  560. .rates = MXS_SAIF_RATES,
  561. .formats = MXS_SAIF_FORMATS,
  562. },
  563. .capture = {
  564. .channels_min = 2,
  565. .channels_max = 2,
  566. .rates = MXS_SAIF_RATES,
  567. .formats = MXS_SAIF_FORMATS,
  568. },
  569. .ops = &mxs_saif_dai_ops,
  570. };
  571. static const struct snd_soc_component_driver mxs_saif_component = {
  572. .name = "mxs-saif",
  573. .legacy_dai_naming = 1,
  574. };
  575. static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
  576. {
  577. struct mxs_saif *saif = dev_id;
  578. unsigned int stat;
  579. stat = __raw_readl(saif->base + SAIF_STAT);
  580. if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
  581. BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
  582. return IRQ_NONE;
  583. if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
  584. dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
  585. __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
  586. saif->base + SAIF_STAT + MXS_CLR_ADDR);
  587. }
  588. if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
  589. dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
  590. __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
  591. saif->base + SAIF_STAT + MXS_CLR_ADDR);
  592. }
  593. dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
  594. __raw_readl(saif->base + SAIF_CTRL),
  595. __raw_readl(saif->base + SAIF_STAT));
  596. return IRQ_HANDLED;
  597. }
  598. static int mxs_saif_mclk_init(struct platform_device *pdev)
  599. {
  600. struct mxs_saif *saif = platform_get_drvdata(pdev);
  601. struct device_node *np = pdev->dev.of_node;
  602. struct clk *clk;
  603. int ret;
  604. clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
  605. __clk_get_name(saif->clk), 0,
  606. saif->base + SAIF_CTRL,
  607. BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
  608. 0, NULL);
  609. if (IS_ERR(clk)) {
  610. ret = PTR_ERR(clk);
  611. if (ret == -EEXIST)
  612. return 0;
  613. dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
  614. return PTR_ERR(clk);
  615. }
  616. ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
  617. if (ret)
  618. return ret;
  619. return 0;
  620. }
  621. static int mxs_saif_probe(struct platform_device *pdev)
  622. {
  623. struct device_node *np = pdev->dev.of_node;
  624. struct mxs_saif *saif;
  625. int irq, ret;
  626. struct device_node *master;
  627. saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
  628. if (!saif)
  629. return -ENOMEM;
  630. ret = of_alias_get_id(np, "saif");
  631. if (ret < 0)
  632. return ret;
  633. else
  634. saif->id = ret;
  635. if (saif->id >= ARRAY_SIZE(mxs_saif)) {
  636. dev_err(&pdev->dev, "get wrong saif id\n");
  637. return -EINVAL;
  638. }
  639. /*
  640. * If there is no "fsl,saif-master" phandle, it's a saif
  641. * master. Otherwise, it's a slave and its phandle points
  642. * to the master.
  643. */
  644. master = of_parse_phandle(np, "fsl,saif-master", 0);
  645. if (!master) {
  646. saif->master_id = saif->id;
  647. } else {
  648. ret = of_alias_get_id(master, "saif");
  649. of_node_put(master);
  650. if (ret < 0)
  651. return ret;
  652. else
  653. saif->master_id = ret;
  654. if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
  655. dev_err(&pdev->dev, "get wrong master id\n");
  656. return -EINVAL;
  657. }
  658. }
  659. mxs_saif[saif->id] = saif;
  660. saif->clk = devm_clk_get(&pdev->dev, NULL);
  661. if (IS_ERR(saif->clk)) {
  662. ret = PTR_ERR(saif->clk);
  663. dev_err(&pdev->dev, "Cannot get the clock: %d\n",
  664. ret);
  665. return ret;
  666. }
  667. saif->base = devm_platform_ioremap_resource(pdev, 0);
  668. if (IS_ERR(saif->base))
  669. return PTR_ERR(saif->base);
  670. irq = platform_get_irq(pdev, 0);
  671. if (irq < 0)
  672. return irq;
  673. saif->dev = &pdev->dev;
  674. ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
  675. dev_name(&pdev->dev), saif);
  676. if (ret) {
  677. dev_err(&pdev->dev, "failed to request irq\n");
  678. return ret;
  679. }
  680. platform_set_drvdata(pdev, saif);
  681. /* We only support saif0 being tx and clock master */
  682. if (saif->id == 0) {
  683. ret = mxs_saif_mclk_init(pdev);
  684. if (ret)
  685. dev_warn(&pdev->dev, "failed to init clocks\n");
  686. }
  687. ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
  688. &mxs_saif_dai, 1);
  689. if (ret) {
  690. dev_err(&pdev->dev, "register DAI failed\n");
  691. return ret;
  692. }
  693. ret = mxs_pcm_platform_register(&pdev->dev);
  694. if (ret) {
  695. dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
  696. return ret;
  697. }
  698. return 0;
  699. }
  700. static const struct of_device_id mxs_saif_dt_ids[] = {
  701. { .compatible = "fsl,imx28-saif", },
  702. { /* sentinel */ }
  703. };
  704. MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
  705. static struct platform_driver mxs_saif_driver = {
  706. .probe = mxs_saif_probe,
  707. .driver = {
  708. .name = "mxs-saif",
  709. .of_match_table = mxs_saif_dt_ids,
  710. },
  711. };
  712. module_platform_driver(mxs_saif_driver);
  713. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  714. MODULE_DESCRIPTION("MXS ASoC SAIF driver");
  715. MODULE_LICENSE("GPL");
  716. MODULE_ALIAS("platform:mxs-saif");