axg-pdm.c 17 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <[email protected]>
  5. #include <linux/clk.h>
  6. #include <linux/module.h>
  7. #include <linux/of_irq.h>
  8. #include <linux/of_platform.h>
  9. #include <linux/regmap.h>
  10. #include <sound/soc.h>
  11. #include <sound/soc-dai.h>
  12. #include <sound/pcm_params.h>
  13. #define PDM_CTRL 0x00
  14. #define PDM_CTRL_EN BIT(31)
  15. #define PDM_CTRL_OUT_MODE BIT(29)
  16. #define PDM_CTRL_BYPASS_MODE BIT(28)
  17. #define PDM_CTRL_RST_FIFO BIT(16)
  18. #define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8)
  19. #define PDM_CTRL_CHAN_RSTN(x) ((x) << 8)
  20. #define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0)
  21. #define PDM_CTRL_CHAN_EN(x) ((x) << 0)
  22. #define PDM_HCIC_CTRL1 0x04
  23. #define PDM_FILTER_EN BIT(31)
  24. #define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24)
  25. #define PDM_HCIC_CTRL1_GAIN_SFT(x) ((x) << 24)
  26. #define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16)
  27. #define PDM_HCIC_CTRL1_GAIN_MULT(x) ((x) << 16)
  28. #define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4)
  29. #define PDM_HCIC_CTRL1_DSR(x) ((x) << 4)
  30. #define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0)
  31. #define PDM_HCIC_CTRL1_STAGE_NUM(x) ((x) << 0)
  32. #define PDM_HCIC_CTRL2 0x08
  33. #define PDM_F1_CTRL 0x0c
  34. #define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16)
  35. #define PDM_LPF_ROUND_MODE(x) ((x) << 16)
  36. #define PDM_LPF_DSR_MASK GENMASK(15, 12)
  37. #define PDM_LPF_DSR(x) ((x) << 12)
  38. #define PDM_LPF_STAGE_NUM_MASK GENMASK(8, 0)
  39. #define PDM_LPF_STAGE_NUM(x) ((x) << 0)
  40. #define PDM_LPF_MAX_STAGE 336
  41. #define PDM_LPF_NUM 3
  42. #define PDM_F2_CTRL 0x10
  43. #define PDM_F3_CTRL 0x14
  44. #define PDM_HPF_CTRL 0x18
  45. #define PDM_HPF_SFT_STEPS_MASK GENMASK(20, 16)
  46. #define PDM_HPF_SFT_STEPS(x) ((x) << 16)
  47. #define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0)
  48. #define PDM_HPF_OUT_FACTOR(x) ((x) << 0)
  49. #define PDM_CHAN_CTRL 0x1c
  50. #define PDM_CHAN_CTRL_POINTER_WIDTH 8
  51. #define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1)
  52. #define PDM_CHAN_CTRL_NUM 4
  53. #define PDM_CHAN_CTRL1 0x20
  54. #define PDM_COEFF_ADDR 0x24
  55. #define PDM_COEFF_DATA 0x28
  56. #define PDM_CLKG_CTRL 0x2c
  57. #define PDM_STS 0x30
  58. struct axg_pdm_lpf {
  59. unsigned int ds;
  60. unsigned int round_mode;
  61. const unsigned int *tap;
  62. unsigned int tap_num;
  63. };
  64. struct axg_pdm_hcic {
  65. unsigned int shift;
  66. unsigned int mult;
  67. unsigned int steps;
  68. unsigned int ds;
  69. };
  70. struct axg_pdm_hpf {
  71. unsigned int out_factor;
  72. unsigned int steps;
  73. };
  74. struct axg_pdm_filters {
  75. struct axg_pdm_hcic hcic;
  76. struct axg_pdm_hpf hpf;
  77. struct axg_pdm_lpf lpf[PDM_LPF_NUM];
  78. };
  79. struct axg_pdm_cfg {
  80. const struct axg_pdm_filters *filters;
  81. unsigned int sys_rate;
  82. };
  83. struct axg_pdm {
  84. const struct axg_pdm_cfg *cfg;
  85. struct regmap *map;
  86. struct clk *dclk;
  87. struct clk *sysclk;
  88. struct clk *pclk;
  89. };
  90. static void axg_pdm_enable(struct regmap *map)
  91. {
  92. /* Reset AFIFO */
  93. regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, PDM_CTRL_RST_FIFO);
  94. regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, 0);
  95. /* Enable PDM */
  96. regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, PDM_CTRL_EN);
  97. }
  98. static void axg_pdm_disable(struct regmap *map)
  99. {
  100. regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, 0);
  101. }
  102. static void axg_pdm_filters_enable(struct regmap *map, bool enable)
  103. {
  104. unsigned int val = enable ? PDM_FILTER_EN : 0;
  105. regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val);
  106. regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val);
  107. regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val);
  108. regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val);
  109. regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val);
  110. }
  111. static int axg_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
  112. struct snd_soc_dai *dai)
  113. {
  114. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  115. switch (cmd) {
  116. case SNDRV_PCM_TRIGGER_START:
  117. case SNDRV_PCM_TRIGGER_RESUME:
  118. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  119. axg_pdm_enable(priv->map);
  120. return 0;
  121. case SNDRV_PCM_TRIGGER_STOP:
  122. case SNDRV_PCM_TRIGGER_SUSPEND:
  123. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  124. axg_pdm_disable(priv->map);
  125. return 0;
  126. default:
  127. return -EINVAL;
  128. }
  129. }
  130. static unsigned int axg_pdm_get_os(struct axg_pdm *priv)
  131. {
  132. const struct axg_pdm_filters *filters = priv->cfg->filters;
  133. unsigned int os = filters->hcic.ds;
  134. int i;
  135. /*
  136. * The global oversampling factor is defined by the down sampling
  137. * factor applied by each filter (HCIC and LPFs)
  138. */
  139. for (i = 0; i < PDM_LPF_NUM; i++)
  140. os *= filters->lpf[i].ds;
  141. return os;
  142. }
  143. static int axg_pdm_set_sysclk(struct axg_pdm *priv, unsigned int os,
  144. unsigned int rate)
  145. {
  146. unsigned int sys_rate = os * 2 * rate * PDM_CHAN_CTRL_POINTER_MAX;
  147. /*
  148. * Set the default system clock rate unless it is too fast for
  149. * for the requested sample rate. In this case, the sample pointer
  150. * counter could overflow so set a lower system clock rate
  151. */
  152. if (sys_rate < priv->cfg->sys_rate)
  153. return clk_set_rate(priv->sysclk, sys_rate);
  154. return clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
  155. }
  156. static int axg_pdm_set_sample_pointer(struct axg_pdm *priv)
  157. {
  158. unsigned int spmax, sp, val;
  159. int i;
  160. /* Max sample counter value per half period of dclk */
  161. spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk),
  162. clk_get_rate(priv->dclk) * 2);
  163. /* Check if sysclk is not too fast - should not happen */
  164. if (WARN_ON(spmax > PDM_CHAN_CTRL_POINTER_MAX))
  165. return -EINVAL;
  166. /* Capture the data when we are at 75% of the half period */
  167. sp = spmax * 3 / 4;
  168. for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++)
  169. val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i);
  170. regmap_write(priv->map, PDM_CHAN_CTRL, val);
  171. regmap_write(priv->map, PDM_CHAN_CTRL1, val);
  172. return 0;
  173. }
  174. static void axg_pdm_set_channel_mask(struct axg_pdm *priv,
  175. unsigned int channels)
  176. {
  177. unsigned int mask = GENMASK(channels - 1, 0);
  178. /* Put all channel in reset */
  179. regmap_update_bits(priv->map, PDM_CTRL,
  180. PDM_CTRL_CHAN_RSTN_MASK, 0);
  181. /* Take the necessary channels out of reset and enable them */
  182. regmap_update_bits(priv->map, PDM_CTRL,
  183. PDM_CTRL_CHAN_RSTN_MASK |
  184. PDM_CTRL_CHAN_EN_MASK,
  185. PDM_CTRL_CHAN_RSTN(mask) |
  186. PDM_CTRL_CHAN_EN(mask));
  187. }
  188. static int axg_pdm_hw_params(struct snd_pcm_substream *substream,
  189. struct snd_pcm_hw_params *params,
  190. struct snd_soc_dai *dai)
  191. {
  192. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  193. unsigned int os = axg_pdm_get_os(priv);
  194. unsigned int rate = params_rate(params);
  195. unsigned int val;
  196. int ret;
  197. switch (params_width(params)) {
  198. case 24:
  199. val = PDM_CTRL_OUT_MODE;
  200. break;
  201. case 32:
  202. val = 0;
  203. break;
  204. default:
  205. dev_err(dai->dev, "unsupported sample width\n");
  206. return -EINVAL;
  207. }
  208. regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val);
  209. ret = axg_pdm_set_sysclk(priv, os, rate);
  210. if (ret) {
  211. dev_err(dai->dev, "failed to set system clock\n");
  212. return ret;
  213. }
  214. ret = clk_set_rate(priv->dclk, rate * os);
  215. if (ret) {
  216. dev_err(dai->dev, "failed to set dclk\n");
  217. return ret;
  218. }
  219. ret = axg_pdm_set_sample_pointer(priv);
  220. if (ret) {
  221. dev_err(dai->dev, "invalid clock setting\n");
  222. return ret;
  223. }
  224. axg_pdm_set_channel_mask(priv, params_channels(params));
  225. return 0;
  226. }
  227. static int axg_pdm_startup(struct snd_pcm_substream *substream,
  228. struct snd_soc_dai *dai)
  229. {
  230. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  231. int ret;
  232. ret = clk_prepare_enable(priv->dclk);
  233. if (ret) {
  234. dev_err(dai->dev, "enabling dclk failed\n");
  235. return ret;
  236. }
  237. /* Enable the filters */
  238. axg_pdm_filters_enable(priv->map, true);
  239. return ret;
  240. }
  241. static void axg_pdm_shutdown(struct snd_pcm_substream *substream,
  242. struct snd_soc_dai *dai)
  243. {
  244. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  245. axg_pdm_filters_enable(priv->map, false);
  246. clk_disable_unprepare(priv->dclk);
  247. }
  248. static const struct snd_soc_dai_ops axg_pdm_dai_ops = {
  249. .trigger = axg_pdm_trigger,
  250. .hw_params = axg_pdm_hw_params,
  251. .startup = axg_pdm_startup,
  252. .shutdown = axg_pdm_shutdown,
  253. };
  254. static void axg_pdm_set_hcic_ctrl(struct axg_pdm *priv)
  255. {
  256. const struct axg_pdm_hcic *hcic = &priv->cfg->filters->hcic;
  257. unsigned int val;
  258. val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps);
  259. val |= PDM_HCIC_CTRL1_DSR(hcic->ds);
  260. val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult);
  261. val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift);
  262. regmap_update_bits(priv->map, PDM_HCIC_CTRL1,
  263. PDM_HCIC_CTRL1_STAGE_NUM_MASK |
  264. PDM_HCIC_CTRL1_DSR_MASK |
  265. PDM_HCIC_CTRL1_GAIN_MULT_MASK |
  266. PDM_HCIC_CTRL1_GAIN_SFT_MASK,
  267. val);
  268. }
  269. static void axg_pdm_set_lpf_ctrl(struct axg_pdm *priv, unsigned int index)
  270. {
  271. const struct axg_pdm_lpf *lpf = &priv->cfg->filters->lpf[index];
  272. unsigned int offset = index * regmap_get_reg_stride(priv->map)
  273. + PDM_F1_CTRL;
  274. unsigned int val;
  275. val = PDM_LPF_STAGE_NUM(lpf->tap_num);
  276. val |= PDM_LPF_DSR(lpf->ds);
  277. val |= PDM_LPF_ROUND_MODE(lpf->round_mode);
  278. regmap_update_bits(priv->map, offset,
  279. PDM_LPF_STAGE_NUM_MASK |
  280. PDM_LPF_DSR_MASK |
  281. PDM_LPF_ROUND_MODE_MASK,
  282. val);
  283. }
  284. static void axg_pdm_set_hpf_ctrl(struct axg_pdm *priv)
  285. {
  286. const struct axg_pdm_hpf *hpf = &priv->cfg->filters->hpf;
  287. unsigned int val;
  288. val = PDM_HPF_OUT_FACTOR(hpf->out_factor);
  289. val |= PDM_HPF_SFT_STEPS(hpf->steps);
  290. regmap_update_bits(priv->map, PDM_HPF_CTRL,
  291. PDM_HPF_OUT_FACTOR_MASK |
  292. PDM_HPF_SFT_STEPS_MASK,
  293. val);
  294. }
  295. static int axg_pdm_set_lpf_filters(struct axg_pdm *priv)
  296. {
  297. const struct axg_pdm_lpf *lpf = priv->cfg->filters->lpf;
  298. unsigned int count = 0;
  299. int i, j;
  300. for (i = 0; i < PDM_LPF_NUM; i++)
  301. count += lpf[i].tap_num;
  302. /* Make sure the coeffs fit in the memory */
  303. if (count >= PDM_LPF_MAX_STAGE)
  304. return -EINVAL;
  305. /* Set the initial APB bus register address */
  306. regmap_write(priv->map, PDM_COEFF_ADDR, 0);
  307. /* Set the tap filter values of all 3 filters */
  308. for (i = 0; i < PDM_LPF_NUM; i++) {
  309. axg_pdm_set_lpf_ctrl(priv, i);
  310. for (j = 0; j < lpf[i].tap_num; j++)
  311. regmap_write(priv->map, PDM_COEFF_DATA, lpf[i].tap[j]);
  312. }
  313. return 0;
  314. }
  315. static int axg_pdm_dai_probe(struct snd_soc_dai *dai)
  316. {
  317. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  318. int ret;
  319. ret = clk_prepare_enable(priv->pclk);
  320. if (ret) {
  321. dev_err(dai->dev, "enabling pclk failed\n");
  322. return ret;
  323. }
  324. /*
  325. * sysclk must be set and enabled as well to access the pdm registers
  326. * Accessing the register w/o it will give a bus error.
  327. */
  328. ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
  329. if (ret) {
  330. dev_err(dai->dev, "setting sysclk failed\n");
  331. goto err_pclk;
  332. }
  333. ret = clk_prepare_enable(priv->sysclk);
  334. if (ret) {
  335. dev_err(dai->dev, "enabling sysclk failed\n");
  336. goto err_pclk;
  337. }
  338. /* Make sure the device is initially disabled */
  339. axg_pdm_disable(priv->map);
  340. /* Make sure filter bypass is disabled */
  341. regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_BYPASS_MODE, 0);
  342. /* Load filter settings */
  343. axg_pdm_set_hcic_ctrl(priv);
  344. axg_pdm_set_hpf_ctrl(priv);
  345. ret = axg_pdm_set_lpf_filters(priv);
  346. if (ret) {
  347. dev_err(dai->dev, "invalid filter configuration\n");
  348. goto err_sysclk;
  349. }
  350. return 0;
  351. err_sysclk:
  352. clk_disable_unprepare(priv->sysclk);
  353. err_pclk:
  354. clk_disable_unprepare(priv->pclk);
  355. return ret;
  356. }
  357. static int axg_pdm_dai_remove(struct snd_soc_dai *dai)
  358. {
  359. struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
  360. clk_disable_unprepare(priv->sysclk);
  361. clk_disable_unprepare(priv->pclk);
  362. return 0;
  363. }
  364. static struct snd_soc_dai_driver axg_pdm_dai_drv = {
  365. .name = "PDM",
  366. .capture = {
  367. .stream_name = "Capture",
  368. .channels_min = 1,
  369. .channels_max = 8,
  370. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  371. .rate_min = 5512,
  372. .rate_max = 48000,
  373. .formats = (SNDRV_PCM_FMTBIT_S24_LE |
  374. SNDRV_PCM_FMTBIT_S32_LE),
  375. },
  376. .ops = &axg_pdm_dai_ops,
  377. .probe = axg_pdm_dai_probe,
  378. .remove = axg_pdm_dai_remove,
  379. };
  380. static const struct snd_soc_component_driver axg_pdm_component_drv = {
  381. .legacy_dai_naming = 1,
  382. };
  383. static const struct regmap_config axg_pdm_regmap_cfg = {
  384. .reg_bits = 32,
  385. .val_bits = 32,
  386. .reg_stride = 4,
  387. .max_register = PDM_STS,
  388. };
  389. static const unsigned int lpf1_default_tap[] = {
  390. 0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45,
  391. 0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21,
  392. 0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212,
  393. 0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa,
  394. 0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef,
  395. 0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077,
  396. 0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690,
  397. 0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3,
  398. 0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686,
  399. 0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812,
  400. 0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60,
  401. 0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000,
  402. 0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e,
  403. 0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c,
  404. 0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece,
  405. 0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645,
  406. 0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9,
  407. 0xffffb2, 0x000014,
  408. };
  409. static const unsigned int lpf2_default_tap[] = {
  410. 0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818,
  411. 0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41,
  412. 0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0,
  413. 0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000,
  414. 0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93,
  415. 0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12,
  416. 0x0002c1, 0xfff004, 0x00050a,
  417. };
  418. static const unsigned int lpf3_default_tap[] = {
  419. 0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000,
  420. 0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7,
  421. 0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000,
  422. 0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0,
  423. 0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000,
  424. 0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7,
  425. 0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000,
  426. 0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45,
  427. 0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000,
  428. 0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c,
  429. 0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000,
  430. 0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216,
  431. 0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000,
  432. 0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d,
  433. 0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000,
  434. 0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368,
  435. 0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000,
  436. 0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb,
  437. 0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000,
  438. 0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c,
  439. 0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000,
  440. 0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46,
  441. 0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000,
  442. 0x000081, 0x000000,
  443. };
  444. /*
  445. * These values are sane defaults for the axg platform:
  446. * - OS = 64
  447. * - Latency = 38700 (?)
  448. *
  449. * TODO: There is a lot of different HCIC, LPFs and HPF configurations possible.
  450. * the configuration may depend on the dmic used by the platform, the
  451. * expected tradeoff between latency and quality, etc ... If/When other
  452. * settings are required, we should add a fw interface to this driver to
  453. * load new filter settings.
  454. */
  455. static const struct axg_pdm_filters axg_default_filters = {
  456. .hcic = {
  457. .shift = 0x15,
  458. .mult = 0x80,
  459. .steps = 7,
  460. .ds = 8,
  461. },
  462. .hpf = {
  463. .out_factor = 0x8000,
  464. .steps = 13,
  465. },
  466. .lpf = {
  467. [0] = {
  468. .ds = 2,
  469. .round_mode = 1,
  470. .tap = lpf1_default_tap,
  471. .tap_num = ARRAY_SIZE(lpf1_default_tap),
  472. },
  473. [1] = {
  474. .ds = 2,
  475. .round_mode = 0,
  476. .tap = lpf2_default_tap,
  477. .tap_num = ARRAY_SIZE(lpf2_default_tap),
  478. },
  479. [2] = {
  480. .ds = 2,
  481. .round_mode = 1,
  482. .tap = lpf3_default_tap,
  483. .tap_num = ARRAY_SIZE(lpf3_default_tap)
  484. },
  485. },
  486. };
  487. static const struct axg_pdm_cfg axg_pdm_config = {
  488. .filters = &axg_default_filters,
  489. .sys_rate = 250000000,
  490. };
  491. static const struct of_device_id axg_pdm_of_match[] = {
  492. {
  493. .compatible = "amlogic,axg-pdm",
  494. .data = &axg_pdm_config,
  495. }, {}
  496. };
  497. MODULE_DEVICE_TABLE(of, axg_pdm_of_match);
  498. static int axg_pdm_probe(struct platform_device *pdev)
  499. {
  500. struct device *dev = &pdev->dev;
  501. struct axg_pdm *priv;
  502. void __iomem *regs;
  503. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  504. if (!priv)
  505. return -ENOMEM;
  506. platform_set_drvdata(pdev, priv);
  507. priv->cfg = of_device_get_match_data(dev);
  508. if (!priv->cfg) {
  509. dev_err(dev, "failed to match device\n");
  510. return -ENODEV;
  511. }
  512. regs = devm_platform_ioremap_resource(pdev, 0);
  513. if (IS_ERR(regs))
  514. return PTR_ERR(regs);
  515. priv->map = devm_regmap_init_mmio(dev, regs, &axg_pdm_regmap_cfg);
  516. if (IS_ERR(priv->map)) {
  517. dev_err(dev, "failed to init regmap: %ld\n",
  518. PTR_ERR(priv->map));
  519. return PTR_ERR(priv->map);
  520. }
  521. priv->pclk = devm_clk_get(dev, "pclk");
  522. if (IS_ERR(priv->pclk))
  523. return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
  524. priv->dclk = devm_clk_get(dev, "dclk");
  525. if (IS_ERR(priv->dclk))
  526. return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n");
  527. priv->sysclk = devm_clk_get(dev, "sysclk");
  528. if (IS_ERR(priv->sysclk))
  529. return dev_err_probe(dev, PTR_ERR(priv->sysclk), "failed to get dclk\n");
  530. return devm_snd_soc_register_component(dev, &axg_pdm_component_drv,
  531. &axg_pdm_dai_drv, 1);
  532. }
  533. static struct platform_driver axg_pdm_pdrv = {
  534. .probe = axg_pdm_probe,
  535. .driver = {
  536. .name = "axg-pdm",
  537. .of_match_table = axg_pdm_of_match,
  538. },
  539. };
  540. module_platform_driver(axg_pdm_pdrv);
  541. MODULE_DESCRIPTION("Amlogic AXG PDM Input driver");
  542. MODULE_AUTHOR("Jerome Brunet <[email protected]>");
  543. MODULE_LICENSE("GPL v2");