mt8192-dai-pcm.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // MediaTek ALSA SoC Audio DAI I2S Control
  4. //
  5. // Copyright (c) 2020 MediaTek Inc.
  6. // Author: Shane Chien <[email protected]>
  7. //
  8. #include <linux/regmap.h>
  9. #include <sound/pcm_params.h>
  10. #include "mt8192-afe-common.h"
  11. #include "mt8192-interconnection.h"
  12. enum AUD_TX_LCH_RPT {
  13. AUD_TX_LCH_RPT_NO_REPEAT = 0,
  14. AUD_TX_LCH_RPT_REPEAT = 1
  15. };
  16. enum AUD_VBT_16K_MODE {
  17. AUD_VBT_16K_MODE_DISABLE = 0,
  18. AUD_VBT_16K_MODE_ENABLE = 1
  19. };
  20. enum AUD_EXT_MODEM {
  21. AUD_EXT_MODEM_SELECT_INTERNAL = 0,
  22. AUD_EXT_MODEM_SELECT_EXTERNAL = 1
  23. };
  24. enum AUD_PCM_SYNC_TYPE {
  25. /* bck sync length = 1 */
  26. AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
  27. /* bck sync length = PCM_INTF_CON1[9:13] */
  28. AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
  29. };
  30. enum AUD_BT_MODE {
  31. AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
  32. AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
  33. };
  34. enum AUD_PCM_AFIFO_SRC {
  35. /* slave mode & external modem uses different crystal */
  36. AUD_PCM_AFIFO_ASRC = 0,
  37. /* slave mode & external modem uses the same crystal */
  38. AUD_PCM_AFIFO_AFIFO = 1
  39. };
  40. enum AUD_PCM_CLOCK_SOURCE {
  41. AUD_PCM_CLOCK_MASTER_MODE = 0,
  42. AUD_PCM_CLOCK_SLAVE_MODE = 1
  43. };
  44. enum AUD_PCM_WLEN {
  45. AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
  46. AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
  47. };
  48. enum AUD_PCM_MODE {
  49. AUD_PCM_MODE_PCM_MODE_8K = 0,
  50. AUD_PCM_MODE_PCM_MODE_16K = 1,
  51. AUD_PCM_MODE_PCM_MODE_32K = 2,
  52. AUD_PCM_MODE_PCM_MODE_48K = 3,
  53. };
  54. enum AUD_PCM_FMT {
  55. AUD_PCM_FMT_I2S = 0,
  56. AUD_PCM_FMT_EIAJ = 1,
  57. AUD_PCM_FMT_PCM_MODE_A = 2,
  58. AUD_PCM_FMT_PCM_MODE_B = 3
  59. };
  60. enum AUD_BCLK_OUT_INV {
  61. AUD_BCLK_OUT_INV_NO_INVERSE = 0,
  62. AUD_BCLK_OUT_INV_INVERSE = 1
  63. };
  64. enum AUD_PCM_EN {
  65. AUD_PCM_EN_DISABLE = 0,
  66. AUD_PCM_EN_ENABLE = 1
  67. };
  68. /* dai component */
  69. static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
  70. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
  71. I_ADDA_UL_CH1, 1, 0),
  72. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
  73. I_DL2_CH1, 1, 0),
  74. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN7_1,
  75. I_DL4_CH1, 1, 0),
  76. };
  77. static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
  78. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
  79. I_ADDA_UL_CH2, 1, 0),
  80. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
  81. I_DL2_CH2, 1, 0),
  82. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN8_1,
  83. I_DL4_CH2, 1, 0),
  84. };
  85. static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
  86. SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN27,
  87. I_I2S0_CH1, 1, 0),
  88. SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN27,
  89. I_I2S0_CH2, 1, 0),
  90. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
  91. I_DL1_CH1, 1, 0),
  92. SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN27,
  93. I_I2S2_CH1, 1, 0),
  94. SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN27,
  95. I_I2S2_CH2, 1, 0),
  96. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN27_1,
  97. I_DL4_CH1, 1, 0),
  98. };
  99. static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
  100. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
  101. I_ADDA_UL_CH1, 1, 0),
  102. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN17,
  103. I_ADDA_UL_CH2, 1, 0),
  104. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN17,
  105. I_ADDA_UL_CH3, 1, 0),
  106. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
  107. I_DL2_CH1, 1, 0),
  108. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN17_1,
  109. I_DL4_CH1, 1, 0),
  110. };
  111. static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
  112. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN18,
  113. I_ADDA_UL_CH1, 1, 0),
  114. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
  115. I_ADDA_UL_CH2, 1, 0),
  116. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN18,
  117. I_ADDA_UL_CH3, 1, 0),
  118. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
  119. I_DL2_CH2, 1, 0),
  120. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN18_1,
  121. I_DL4_CH2, 1, 0),
  122. };
  123. static const struct snd_kcontrol_new mtk_pcm_2_playback_ch3_mix[] = {
  124. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN23,
  125. I_ADDA_UL_CH3, 1, 0),
  126. };
  127. static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
  128. SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN24,
  129. I_I2S0_CH1, 1, 0),
  130. SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN24,
  131. I_I2S0_CH2, 1, 0),
  132. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
  133. I_DL1_CH1, 1, 0),
  134. SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN24,
  135. I_I2S2_CH1, 1, 0),
  136. SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN24,
  137. I_I2S2_CH2, 1, 0),
  138. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN24_1,
  139. I_DL4_CH1, 1, 0),
  140. };
  141. static const struct snd_kcontrol_new mtk_pcm_2_playback_ch5_mix[] = {
  142. SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN25,
  143. I_I2S0_CH2, 1, 0),
  144. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN25,
  145. I_DL1_CH2, 1, 0),
  146. SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN25,
  147. I_I2S2_CH2, 1, 0),
  148. SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN25_1,
  149. I_DL4_CH2, 1, 0),
  150. };
  151. static int mtk_pcm_en_event(struct snd_soc_dapm_widget *w,
  152. struct snd_kcontrol *kcontrol,
  153. int event)
  154. {
  155. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  156. struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
  157. dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
  158. __func__, w->name, event);
  159. return 0;
  160. }
  161. static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
  162. /* inter-connections */
  163. SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
  164. mtk_pcm_1_playback_ch1_mix,
  165. ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
  166. SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
  167. mtk_pcm_1_playback_ch2_mix,
  168. ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
  169. SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
  170. mtk_pcm_1_playback_ch4_mix,
  171. ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
  172. SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
  173. mtk_pcm_2_playback_ch1_mix,
  174. ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
  175. SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
  176. mtk_pcm_2_playback_ch2_mix,
  177. ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
  178. SND_SOC_DAPM_MIXER("PCM_2_PB_CH3", SND_SOC_NOPM, 0, 0,
  179. mtk_pcm_2_playback_ch3_mix,
  180. ARRAY_SIZE(mtk_pcm_2_playback_ch3_mix)),
  181. SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
  182. mtk_pcm_2_playback_ch4_mix,
  183. ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
  184. SND_SOC_DAPM_MIXER("PCM_2_PB_CH5", SND_SOC_NOPM, 0, 0,
  185. mtk_pcm_2_playback_ch5_mix,
  186. ARRAY_SIZE(mtk_pcm_2_playback_ch5_mix)),
  187. SND_SOC_DAPM_SUPPLY("PCM_1_EN",
  188. PCM_INTF_CON1, PCM_EN_SFT, 0,
  189. mtk_pcm_en_event,
  190. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  191. SND_SOC_DAPM_SUPPLY("PCM_2_EN",
  192. PCM2_INTF_CON, PCM2_EN_SFT, 0,
  193. mtk_pcm_en_event,
  194. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  195. SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
  196. SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
  197. SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
  198. SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
  199. };
  200. static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
  201. {"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
  202. {"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
  203. {"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
  204. {"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
  205. {"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
  206. {"PCM 2 Playback", NULL, "PCM_2_PB_CH3"},
  207. {"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
  208. {"PCM 2 Playback", NULL, "PCM_2_PB_CH5"},
  209. {"PCM 1 Playback", NULL, "PCM_1_EN"},
  210. {"PCM 2 Playback", NULL, "PCM_2_EN"},
  211. {"PCM 1 Capture", NULL, "PCM_1_EN"},
  212. {"PCM 2 Capture", NULL, "PCM_2_EN"},
  213. {"AFE_TO_MD1", NULL, "PCM 2 Playback"},
  214. {"AFE_TO_MD2", NULL, "PCM 1 Playback"},
  215. {"PCM 2 Capture", NULL, "MD1_TO_AFE"},
  216. {"PCM 1 Capture", NULL, "MD2_TO_AFE"},
  217. {"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
  218. {"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
  219. {"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
  220. {"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
  221. {"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
  222. {"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
  223. {"PCM_1_PB_CH1", "DL4_CH1", "DL4"},
  224. {"PCM_1_PB_CH2", "DL4_CH2", "DL4"},
  225. {"PCM_1_PB_CH4", "DL4_CH1", "DL4"},
  226. {"PCM_2_PB_CH1", "DL4_CH1", "DL4"},
  227. {"PCM_2_PB_CH2", "DL4_CH2", "DL4"},
  228. {"PCM_2_PB_CH4", "DL4_CH1", "DL4"},
  229. {"PCM_1_PB_CH4", "I2S0_CH1", "I2S0"},
  230. {"PCM_2_PB_CH4", "I2S2_CH1", "I2S2"},
  231. {"PCM_2_PB_CH5", "DL1_CH2", "DL1"},
  232. {"PCM_2_PB_CH5", "DL4_CH2", "DL4"},
  233. {"PCM_2_PB_CH5", "I2S0_CH2", "I2S0"},
  234. {"PCM_2_PB_CH5", "I2S2_CH2", "I2S2"},
  235. };
  236. /* dai ops */
  237. static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
  238. struct snd_pcm_hw_params *params,
  239. struct snd_soc_dai *dai)
  240. {
  241. struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
  242. unsigned int rate = params_rate(params);
  243. unsigned int rate_reg = mt8192_rate_transform(afe->dev, rate, dai->id);
  244. unsigned int pcm_con = 0;
  245. dev_info(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
  246. __func__,
  247. dai->id,
  248. substream->stream,
  249. rate,
  250. rate_reg,
  251. dai->playback_widget->active,
  252. dai->capture_widget->active);
  253. if (dai->playback_widget->active || dai->capture_widget->active)
  254. return 0;
  255. switch (dai->id) {
  256. case MT8192_DAI_PCM_1:
  257. pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
  258. pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
  259. pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
  260. pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
  261. pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
  262. pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
  263. pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
  264. pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
  265. pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
  266. pcm_con |= rate_reg << PCM_MODE_SFT;
  267. pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
  268. regmap_update_bits(afe->regmap, PCM_INTF_CON1,
  269. 0xfffffffe, pcm_con);
  270. break;
  271. case MT8192_DAI_PCM_2:
  272. pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
  273. pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
  274. pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
  275. pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
  276. pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
  277. pcm_con |= rate_reg << PCM2_MODE_SFT;
  278. pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
  279. regmap_update_bits(afe->regmap, PCM2_INTF_CON,
  280. 0xfffffffe, pcm_con);
  281. break;
  282. default:
  283. dev_warn(afe->dev, "%s(), id %d not support\n",
  284. __func__, dai->id);
  285. return -EINVAL;
  286. }
  287. return 0;
  288. }
  289. static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
  290. .hw_params = mtk_dai_pcm_hw_params,
  291. };
  292. /* dai driver */
  293. #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
  294. SNDRV_PCM_RATE_16000 |\
  295. SNDRV_PCM_RATE_32000 |\
  296. SNDRV_PCM_RATE_48000)
  297. #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  298. SNDRV_PCM_FMTBIT_S24_LE |\
  299. SNDRV_PCM_FMTBIT_S32_LE)
  300. static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
  301. {
  302. .name = "PCM 1",
  303. .id = MT8192_DAI_PCM_1,
  304. .playback = {
  305. .stream_name = "PCM 1 Playback",
  306. .channels_min = 1,
  307. .channels_max = 2,
  308. .rates = MTK_PCM_RATES,
  309. .formats = MTK_PCM_FORMATS,
  310. },
  311. .capture = {
  312. .stream_name = "PCM 1 Capture",
  313. .channels_min = 1,
  314. .channels_max = 2,
  315. .rates = MTK_PCM_RATES,
  316. .formats = MTK_PCM_FORMATS,
  317. },
  318. .ops = &mtk_dai_pcm_ops,
  319. .symmetric_rate = 1,
  320. .symmetric_sample_bits = 1,
  321. },
  322. {
  323. .name = "PCM 2",
  324. .id = MT8192_DAI_PCM_2,
  325. .playback = {
  326. .stream_name = "PCM 2 Playback",
  327. .channels_min = 1,
  328. .channels_max = 2,
  329. .rates = MTK_PCM_RATES,
  330. .formats = MTK_PCM_FORMATS,
  331. },
  332. .capture = {
  333. .stream_name = "PCM 2 Capture",
  334. .channels_min = 1,
  335. .channels_max = 2,
  336. .rates = MTK_PCM_RATES,
  337. .formats = MTK_PCM_FORMATS,
  338. },
  339. .ops = &mtk_dai_pcm_ops,
  340. .symmetric_rate = 1,
  341. .symmetric_sample_bits = 1,
  342. },
  343. };
  344. int mt8192_dai_pcm_register(struct mtk_base_afe *afe)
  345. {
  346. struct mtk_base_afe_dai *dai;
  347. dev_info(afe->dev, "%s()\n", __func__);
  348. dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
  349. if (!dai)
  350. return -ENOMEM;
  351. list_add(&dai->list, &afe->sub_dais);
  352. dai->dai_drivers = mtk_dai_pcm_driver;
  353. dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
  354. dai->dapm_widgets = mtk_dai_pcm_widgets;
  355. dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
  356. dai->dapm_routes = mtk_dai_pcm_routes;
  357. dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
  358. return 0;
  359. }