mt6797-dai-adda.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // MediaTek ALSA SoC Audio DAI ADDA Control
  4. //
  5. // Copyright (c) 2018 MediaTek Inc.
  6. // Author: KaiChieh Chuang <[email protected]>
  7. #include <linux/regmap.h>
  8. #include <linux/delay.h>
  9. #include "mt6797-afe-common.h"
  10. #include "mt6797-interconnection.h"
  11. #include "mt6797-reg.h"
  12. enum {
  13. MTK_AFE_ADDA_DL_RATE_8K = 0,
  14. MTK_AFE_ADDA_DL_RATE_11K = 1,
  15. MTK_AFE_ADDA_DL_RATE_12K = 2,
  16. MTK_AFE_ADDA_DL_RATE_16K = 3,
  17. MTK_AFE_ADDA_DL_RATE_22K = 4,
  18. MTK_AFE_ADDA_DL_RATE_24K = 5,
  19. MTK_AFE_ADDA_DL_RATE_32K = 6,
  20. MTK_AFE_ADDA_DL_RATE_44K = 7,
  21. MTK_AFE_ADDA_DL_RATE_48K = 8,
  22. MTK_AFE_ADDA_DL_RATE_96K = 9,
  23. MTK_AFE_ADDA_DL_RATE_192K = 10,
  24. };
  25. enum {
  26. MTK_AFE_ADDA_UL_RATE_8K = 0,
  27. MTK_AFE_ADDA_UL_RATE_16K = 1,
  28. MTK_AFE_ADDA_UL_RATE_32K = 2,
  29. MTK_AFE_ADDA_UL_RATE_48K = 3,
  30. MTK_AFE_ADDA_UL_RATE_96K = 4,
  31. MTK_AFE_ADDA_UL_RATE_192K = 5,
  32. MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
  33. };
  34. static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
  35. unsigned int rate)
  36. {
  37. switch (rate) {
  38. case 8000:
  39. return MTK_AFE_ADDA_DL_RATE_8K;
  40. case 11025:
  41. return MTK_AFE_ADDA_DL_RATE_11K;
  42. case 12000:
  43. return MTK_AFE_ADDA_DL_RATE_12K;
  44. case 16000:
  45. return MTK_AFE_ADDA_DL_RATE_16K;
  46. case 22050:
  47. return MTK_AFE_ADDA_DL_RATE_22K;
  48. case 24000:
  49. return MTK_AFE_ADDA_DL_RATE_24K;
  50. case 32000:
  51. return MTK_AFE_ADDA_DL_RATE_32K;
  52. case 44100:
  53. return MTK_AFE_ADDA_DL_RATE_44K;
  54. case 48000:
  55. return MTK_AFE_ADDA_DL_RATE_48K;
  56. case 96000:
  57. return MTK_AFE_ADDA_DL_RATE_96K;
  58. case 192000:
  59. return MTK_AFE_ADDA_DL_RATE_192K;
  60. default:
  61. dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
  62. __func__, rate);
  63. return MTK_AFE_ADDA_DL_RATE_48K;
  64. }
  65. }
  66. static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
  67. unsigned int rate)
  68. {
  69. switch (rate) {
  70. case 8000:
  71. return MTK_AFE_ADDA_UL_RATE_8K;
  72. case 16000:
  73. return MTK_AFE_ADDA_UL_RATE_16K;
  74. case 32000:
  75. return MTK_AFE_ADDA_UL_RATE_32K;
  76. case 48000:
  77. return MTK_AFE_ADDA_UL_RATE_48K;
  78. case 96000:
  79. return MTK_AFE_ADDA_UL_RATE_96K;
  80. case 192000:
  81. return MTK_AFE_ADDA_UL_RATE_192K;
  82. default:
  83. dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
  84. __func__, rate);
  85. return MTK_AFE_ADDA_UL_RATE_48K;
  86. }
  87. }
  88. /* dai component */
  89. static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
  90. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
  91. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
  92. SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
  93. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
  94. I_ADDA_UL_CH2, 1, 0),
  95. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
  96. I_ADDA_UL_CH1, 1, 0),
  97. SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
  98. I_PCM_1_CAP_CH1, 1, 0),
  99. SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
  100. I_PCM_2_CAP_CH1, 1, 0),
  101. };
  102. static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
  103. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
  104. SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
  105. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
  106. SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
  107. SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
  108. SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
  109. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
  110. I_ADDA_UL_CH2, 1, 0),
  111. SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
  112. I_ADDA_UL_CH1, 1, 0),
  113. SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
  114. I_PCM_1_CAP_CH1, 1, 0),
  115. SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
  116. I_PCM_2_CAP_CH1, 1, 0),
  117. SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
  118. I_PCM_1_CAP_CH2, 1, 0),
  119. SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
  120. I_PCM_2_CAP_CH2, 1, 0),
  121. };
  122. static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
  123. struct snd_kcontrol *kcontrol,
  124. int event)
  125. {
  126. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  127. struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
  128. dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
  129. __func__, w->name, event);
  130. switch (event) {
  131. case SND_SOC_DAPM_POST_PMD:
  132. /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
  133. usleep_range(125, 135);
  134. break;
  135. default:
  136. break;
  137. }
  138. return 0;
  139. }
  140. enum {
  141. SUPPLY_SEQ_AUD_TOP_PDN,
  142. SUPPLY_SEQ_ADDA_AFE_ON,
  143. SUPPLY_SEQ_ADDA_DL_ON,
  144. SUPPLY_SEQ_ADDA_UL_ON,
  145. };
  146. static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
  147. /* adda */
  148. SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
  149. mtk_adda_dl_ch1_mix,
  150. ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
  151. SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
  152. mtk_adda_dl_ch2_mix,
  153. ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
  154. SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
  155. AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
  156. NULL, 0),
  157. SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
  158. AFE_ADDA_DL_SRC2_CON0,
  159. DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
  160. NULL, 0),
  161. SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
  162. AFE_ADDA_UL_SRC_CON0,
  163. UL_SRC_ON_TMP_CTL_SFT, 0,
  164. mtk_adda_ul_event,
  165. SND_SOC_DAPM_POST_PMD),
  166. SND_SOC_DAPM_SUPPLY_S("aud_dac_clk", SUPPLY_SEQ_AUD_TOP_PDN,
  167. AUDIO_TOP_CON0, PDN_DAC_SFT, 1,
  168. NULL, 0),
  169. SND_SOC_DAPM_SUPPLY_S("aud_dac_predis_clk", SUPPLY_SEQ_AUD_TOP_PDN,
  170. AUDIO_TOP_CON0, PDN_DAC_PREDIS_SFT, 1,
  171. NULL, 0),
  172. SND_SOC_DAPM_SUPPLY_S("aud_adc_clk", SUPPLY_SEQ_AUD_TOP_PDN,
  173. AUDIO_TOP_CON0, PDN_ADC_SFT, 1,
  174. NULL, 0),
  175. SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
  176. };
  177. static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
  178. /* playback */
  179. {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
  180. {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
  181. {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
  182. {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
  183. {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
  184. {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
  185. {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
  186. {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
  187. {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
  188. {"ADDA Playback", NULL, "ADDA_DL_CH1"},
  189. {"ADDA Playback", NULL, "ADDA_DL_CH2"},
  190. /* adda enable */
  191. {"ADDA Playback", NULL, "ADDA Enable"},
  192. {"ADDA Playback", NULL, "ADDA Playback Enable"},
  193. {"ADDA Capture", NULL, "ADDA Enable"},
  194. {"ADDA Capture", NULL, "ADDA Capture Enable"},
  195. /* clk */
  196. {"ADDA Playback", NULL, "mtkaif_26m_clk"},
  197. {"ADDA Playback", NULL, "aud_dac_clk"},
  198. {"ADDA Playback", NULL, "aud_dac_predis_clk"},
  199. {"ADDA Capture", NULL, "mtkaif_26m_clk"},
  200. {"ADDA Capture", NULL, "aud_adc_clk"},
  201. };
  202. /* dai ops */
  203. static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
  204. struct snd_pcm_hw_params *params,
  205. struct snd_soc_dai *dai)
  206. {
  207. struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
  208. unsigned int rate = params_rate(params);
  209. dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
  210. __func__, dai->id, substream->stream, rate);
  211. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  212. unsigned int dl_src2_con0 = 0;
  213. unsigned int dl_src2_con1 = 0;
  214. /* clean predistortion */
  215. regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
  216. regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
  217. /* set input sampling rate */
  218. dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
  219. /* set output mode */
  220. switch (rate) {
  221. case 192000:
  222. dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
  223. dl_src2_con0 |= 1 << 14;
  224. break;
  225. case 96000:
  226. dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
  227. dl_src2_con0 |= 1 << 14;
  228. break;
  229. default:
  230. dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
  231. break;
  232. }
  233. /* turn off mute function */
  234. dl_src2_con0 |= (0x03 << 11);
  235. /* set voice input data if input sample rate is 8k or 16k */
  236. if (rate == 8000 || rate == 16000)
  237. dl_src2_con0 |= 0x01 << 5;
  238. if (rate < 96000) {
  239. /* SA suggest apply -0.3db to audio/speech path */
  240. dl_src2_con1 = 0xf74f0000;
  241. } else {
  242. /* SA suggest apply -0.3db to audio/speech path
  243. * with DL gain set to half,
  244. * 0xFFFF = 0dB -> 0x8000 = 0dB when 96k, 192k
  245. */
  246. dl_src2_con1 = 0x7ba70000;
  247. }
  248. /* turn on down-link gain */
  249. dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
  250. regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
  251. regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
  252. } else {
  253. unsigned int voice_mode = 0;
  254. unsigned int ul_src_con0 = 0; /* default value */
  255. /* Using Internal ADC */
  256. regmap_update_bits(afe->regmap,
  257. AFE_ADDA_TOP_CON0,
  258. 0x1 << 0,
  259. 0x0 << 0);
  260. voice_mode = adda_ul_rate_transform(afe, rate);
  261. ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
  262. /* up8x txif sat on */
  263. regmap_write(afe->regmap, AFE_ADDA_NEWIF_CFG0, 0x03F87201);
  264. if (rate >= 96000) { /* hires */
  265. /* use hires format [1 0 23] */
  266. regmap_update_bits(afe->regmap,
  267. AFE_ADDA_NEWIF_CFG0,
  268. 0x1 << 5,
  269. 0x1 << 5);
  270. regmap_update_bits(afe->regmap,
  271. AFE_ADDA_NEWIF_CFG2,
  272. 0xf << 28,
  273. voice_mode << 28);
  274. } else { /* normal 8~48k */
  275. /* use fixed 260k anc path */
  276. regmap_update_bits(afe->regmap,
  277. AFE_ADDA_NEWIF_CFG2,
  278. 0xf << 28,
  279. 8 << 28);
  280. /* ul_use_cic_out */
  281. ul_src_con0 |= 0x1 << 20;
  282. }
  283. regmap_update_bits(afe->regmap,
  284. AFE_ADDA_NEWIF_CFG2,
  285. 0xf << 28,
  286. 8 << 28);
  287. regmap_update_bits(afe->regmap,
  288. AFE_ADDA_UL_SRC_CON0,
  289. 0xfffffffe,
  290. ul_src_con0);
  291. }
  292. return 0;
  293. }
  294. static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
  295. .hw_params = mtk_dai_adda_hw_params,
  296. };
  297. /* dai driver */
  298. #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
  299. SNDRV_PCM_RATE_96000 |\
  300. SNDRV_PCM_RATE_192000)
  301. #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
  302. SNDRV_PCM_RATE_16000 |\
  303. SNDRV_PCM_RATE_32000 |\
  304. SNDRV_PCM_RATE_48000 |\
  305. SNDRV_PCM_RATE_96000 |\
  306. SNDRV_PCM_RATE_192000)
  307. #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  308. SNDRV_PCM_FMTBIT_S24_LE |\
  309. SNDRV_PCM_FMTBIT_S32_LE)
  310. static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
  311. {
  312. .name = "ADDA",
  313. .id = MT6797_DAI_ADDA,
  314. .playback = {
  315. .stream_name = "ADDA Playback",
  316. .channels_min = 1,
  317. .channels_max = 2,
  318. .rates = MTK_ADDA_PLAYBACK_RATES,
  319. .formats = MTK_ADDA_FORMATS,
  320. },
  321. .capture = {
  322. .stream_name = "ADDA Capture",
  323. .channels_min = 1,
  324. .channels_max = 2,
  325. .rates = MTK_ADDA_CAPTURE_RATES,
  326. .formats = MTK_ADDA_FORMATS,
  327. },
  328. .ops = &mtk_dai_adda_ops,
  329. },
  330. };
  331. int mt6797_dai_adda_register(struct mtk_base_afe *afe)
  332. {
  333. struct mtk_base_afe_dai *dai;
  334. dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
  335. if (!dai)
  336. return -ENOMEM;
  337. list_add(&dai->list, &afe->sub_dais);
  338. dai->dai_drivers = mtk_dai_adda_driver;
  339. dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
  340. dai->dapm_widgets = mtk_dai_adda_widgets;
  341. dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
  342. dai->dapm_routes = mtk_dai_adda_routes;
  343. dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
  344. return 0;
  345. }