mt2701-cs42448.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * mt2701-cs42448.c -- MT2701 CS42448 ALSA SoC machine driver
  4. *
  5. * Copyright (c) 2016 MediaTek Inc.
  6. * Author: Ir Lian <[email protected]>
  7. * Garlic Tseng <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <sound/soc.h>
  11. #include <linux/delay.h>
  12. #include <linux/gpio.h>
  13. #include <linux/pinctrl/consumer.h>
  14. #include <linux/of_gpio.h>
  15. #include "mt2701-afe-common.h"
  16. struct mt2701_cs42448_private {
  17. int i2s1_in_mux;
  18. int i2s1_in_mux_gpio_sel_1;
  19. int i2s1_in_mux_gpio_sel_2;
  20. };
  21. static const char * const i2sin_mux_switch_text[] = {
  22. "ADC_SDOUT2",
  23. "ADC_SDOUT3",
  24. "I2S_IN_1",
  25. "I2S_IN_2",
  26. };
  27. static const struct soc_enum i2sin_mux_enum =
  28. SOC_ENUM_SINGLE_EXT(4, i2sin_mux_switch_text);
  29. static int mt2701_cs42448_i2sin1_mux_get(struct snd_kcontrol *kcontrol,
  30. struct snd_ctl_elem_value *ucontrol)
  31. {
  32. struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
  33. struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
  34. ucontrol->value.integer.value[0] = priv->i2s1_in_mux;
  35. return 0;
  36. }
  37. static int mt2701_cs42448_i2sin1_mux_set(struct snd_kcontrol *kcontrol,
  38. struct snd_ctl_elem_value *ucontrol)
  39. {
  40. struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
  41. struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
  42. if (ucontrol->value.integer.value[0] == priv->i2s1_in_mux)
  43. return 0;
  44. switch (ucontrol->value.integer.value[0]) {
  45. case 0:
  46. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
  47. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
  48. break;
  49. case 1:
  50. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
  51. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
  52. break;
  53. case 2:
  54. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
  55. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
  56. break;
  57. case 3:
  58. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
  59. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
  60. break;
  61. default:
  62. dev_warn(card->dev, "%s invalid setting\n", __func__);
  63. }
  64. priv->i2s1_in_mux = ucontrol->value.integer.value[0];
  65. return 0;
  66. }
  67. static const struct snd_soc_dapm_widget
  68. mt2701_cs42448_asoc_card_dapm_widgets[] = {
  69. SND_SOC_DAPM_LINE("Line Out Jack", NULL),
  70. SND_SOC_DAPM_MIC("AMIC", NULL),
  71. SND_SOC_DAPM_LINE("Tuner In", NULL),
  72. SND_SOC_DAPM_LINE("Satellite Tuner In", NULL),
  73. SND_SOC_DAPM_LINE("AUX In", NULL),
  74. };
  75. static const struct snd_kcontrol_new mt2701_cs42448_controls[] = {
  76. SOC_DAPM_PIN_SWITCH("Line Out Jack"),
  77. SOC_DAPM_PIN_SWITCH("AMIC"),
  78. SOC_DAPM_PIN_SWITCH("Tuner In"),
  79. SOC_DAPM_PIN_SWITCH("Satellite Tuner In"),
  80. SOC_DAPM_PIN_SWITCH("AUX In"),
  81. SOC_ENUM_EXT("I2SIN1_MUX_Switch", i2sin_mux_enum,
  82. mt2701_cs42448_i2sin1_mux_get,
  83. mt2701_cs42448_i2sin1_mux_set),
  84. };
  85. static const unsigned int mt2701_cs42448_sampling_rates[] = {48000};
  86. static const struct snd_pcm_hw_constraint_list mt2701_cs42448_constraints_rates = {
  87. .count = ARRAY_SIZE(mt2701_cs42448_sampling_rates),
  88. .list = mt2701_cs42448_sampling_rates,
  89. .mask = 0,
  90. };
  91. static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
  92. {
  93. int err;
  94. err = snd_pcm_hw_constraint_list(substream->runtime, 0,
  95. SNDRV_PCM_HW_PARAM_RATE,
  96. &mt2701_cs42448_constraints_rates);
  97. if (err < 0) {
  98. dev_err(substream->pcm->card->dev,
  99. "%s snd_pcm_hw_constraint_list failed: 0x%x\n",
  100. __func__, err);
  101. return err;
  102. }
  103. return 0;
  104. }
  105. static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
  106. .startup = mt2701_cs42448_fe_ops_startup,
  107. };
  108. static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
  109. struct snd_pcm_hw_params *params)
  110. {
  111. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  112. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  113. struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
  114. unsigned int mclk_rate;
  115. unsigned int rate = params_rate(params);
  116. unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
  117. unsigned int div_bck_over_lrck = 64;
  118. mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
  119. /* mt2701 mclk */
  120. snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
  121. /* codec mclk */
  122. snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
  123. return 0;
  124. }
  125. static const struct snd_soc_ops mt2701_cs42448_be_ops = {
  126. .hw_params = mt2701_cs42448_be_ops_hw_params
  127. };
  128. enum {
  129. DAI_LINK_FE_MULTI_CH_OUT,
  130. DAI_LINK_FE_PCM0_IN,
  131. DAI_LINK_FE_PCM1_IN,
  132. DAI_LINK_FE_BT_OUT,
  133. DAI_LINK_FE_BT_IN,
  134. DAI_LINK_BE_I2S0,
  135. DAI_LINK_BE_I2S1,
  136. DAI_LINK_BE_I2S2,
  137. DAI_LINK_BE_I2S3,
  138. DAI_LINK_BE_MRG_BT,
  139. };
  140. SND_SOC_DAILINK_DEFS(fe_multi_ch_out,
  141. DAILINK_COMP_ARRAY(COMP_CPU("PCM_multi")),
  142. DAILINK_COMP_ARRAY(COMP_DUMMY()),
  143. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  144. SND_SOC_DAILINK_DEFS(fe_pcm0_in,
  145. DAILINK_COMP_ARRAY(COMP_CPU("PCM0")),
  146. DAILINK_COMP_ARRAY(COMP_DUMMY()),
  147. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  148. SND_SOC_DAILINK_DEFS(fe_pcm1_in,
  149. DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
  150. DAILINK_COMP_ARRAY(COMP_DUMMY()),
  151. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  152. SND_SOC_DAILINK_DEFS(fe_bt_out,
  153. DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_DL")),
  154. DAILINK_COMP_ARRAY(COMP_DUMMY()),
  155. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  156. SND_SOC_DAILINK_DEFS(fe_bt_in,
  157. DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_UL")),
  158. DAILINK_COMP_ARRAY(COMP_DUMMY()),
  159. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  160. SND_SOC_DAILINK_DEFS(be_i2s0,
  161. DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
  162. DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
  163. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  164. SND_SOC_DAILINK_DEFS(be_i2s1,
  165. DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
  166. DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
  167. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  168. SND_SOC_DAILINK_DEFS(be_i2s2,
  169. DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
  170. DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
  171. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  172. SND_SOC_DAILINK_DEFS(be_i2s3,
  173. DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
  174. DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
  175. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  176. SND_SOC_DAILINK_DEFS(be_mrg_bt,
  177. DAILINK_COMP_ARRAY(COMP_CPU("MRG BT")),
  178. DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "bt-sco-pcm-wb")),
  179. DAILINK_COMP_ARRAY(COMP_EMPTY()));
  180. static struct snd_soc_dai_link mt2701_cs42448_dai_links[] = {
  181. /* FE */
  182. [DAI_LINK_FE_MULTI_CH_OUT] = {
  183. .name = "mt2701-cs42448-multi-ch-out",
  184. .stream_name = "mt2701-cs42448-multi-ch-out",
  185. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  186. SND_SOC_DPCM_TRIGGER_POST},
  187. .ops = &mt2701_cs42448_48k_fe_ops,
  188. .dynamic = 1,
  189. .dpcm_playback = 1,
  190. SND_SOC_DAILINK_REG(fe_multi_ch_out),
  191. },
  192. [DAI_LINK_FE_PCM0_IN] = {
  193. .name = "mt2701-cs42448-pcm0",
  194. .stream_name = "mt2701-cs42448-pcm0-data-UL",
  195. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  196. SND_SOC_DPCM_TRIGGER_POST},
  197. .ops = &mt2701_cs42448_48k_fe_ops,
  198. .dynamic = 1,
  199. .dpcm_capture = 1,
  200. SND_SOC_DAILINK_REG(fe_pcm0_in),
  201. },
  202. [DAI_LINK_FE_PCM1_IN] = {
  203. .name = "mt2701-cs42448-pcm1-data-UL",
  204. .stream_name = "mt2701-cs42448-pcm1-data-UL",
  205. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  206. SND_SOC_DPCM_TRIGGER_POST},
  207. .ops = &mt2701_cs42448_48k_fe_ops,
  208. .dynamic = 1,
  209. .dpcm_capture = 1,
  210. SND_SOC_DAILINK_REG(fe_pcm1_in),
  211. },
  212. [DAI_LINK_FE_BT_OUT] = {
  213. .name = "mt2701-cs42448-pcm-BT-out",
  214. .stream_name = "mt2701-cs42448-pcm-BT",
  215. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  216. SND_SOC_DPCM_TRIGGER_POST},
  217. .dynamic = 1,
  218. .dpcm_playback = 1,
  219. SND_SOC_DAILINK_REG(fe_bt_out),
  220. },
  221. [DAI_LINK_FE_BT_IN] = {
  222. .name = "mt2701-cs42448-pcm-BT-in",
  223. .stream_name = "mt2701-cs42448-pcm-BT",
  224. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  225. SND_SOC_DPCM_TRIGGER_POST},
  226. .dynamic = 1,
  227. .dpcm_capture = 1,
  228. SND_SOC_DAILINK_REG(fe_bt_in),
  229. },
  230. /* BE */
  231. [DAI_LINK_BE_I2S0] = {
  232. .name = "mt2701-cs42448-I2S0",
  233. .no_pcm = 1,
  234. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  235. | SND_SOC_DAIFMT_GATED,
  236. .ops = &mt2701_cs42448_be_ops,
  237. .dpcm_playback = 1,
  238. .dpcm_capture = 1,
  239. SND_SOC_DAILINK_REG(be_i2s0),
  240. },
  241. [DAI_LINK_BE_I2S1] = {
  242. .name = "mt2701-cs42448-I2S1",
  243. .no_pcm = 1,
  244. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  245. | SND_SOC_DAIFMT_GATED,
  246. .ops = &mt2701_cs42448_be_ops,
  247. .dpcm_playback = 1,
  248. .dpcm_capture = 1,
  249. SND_SOC_DAILINK_REG(be_i2s1),
  250. },
  251. [DAI_LINK_BE_I2S2] = {
  252. .name = "mt2701-cs42448-I2S2",
  253. .no_pcm = 1,
  254. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  255. | SND_SOC_DAIFMT_GATED,
  256. .ops = &mt2701_cs42448_be_ops,
  257. .dpcm_playback = 1,
  258. .dpcm_capture = 1,
  259. SND_SOC_DAILINK_REG(be_i2s2),
  260. },
  261. [DAI_LINK_BE_I2S3] = {
  262. .name = "mt2701-cs42448-I2S3",
  263. .no_pcm = 1,
  264. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  265. | SND_SOC_DAIFMT_GATED,
  266. .ops = &mt2701_cs42448_be_ops,
  267. .dpcm_playback = 1,
  268. .dpcm_capture = 1,
  269. SND_SOC_DAILINK_REG(be_i2s3),
  270. },
  271. [DAI_LINK_BE_MRG_BT] = {
  272. .name = "mt2701-cs42448-MRG-BT",
  273. .no_pcm = 1,
  274. .dpcm_playback = 1,
  275. .dpcm_capture = 1,
  276. SND_SOC_DAILINK_REG(be_mrg_bt),
  277. },
  278. };
  279. static struct snd_soc_card mt2701_cs42448_soc_card = {
  280. .name = "mt2701-cs42448",
  281. .owner = THIS_MODULE,
  282. .dai_link = mt2701_cs42448_dai_links,
  283. .num_links = ARRAY_SIZE(mt2701_cs42448_dai_links),
  284. .controls = mt2701_cs42448_controls,
  285. .num_controls = ARRAY_SIZE(mt2701_cs42448_controls),
  286. .dapm_widgets = mt2701_cs42448_asoc_card_dapm_widgets,
  287. .num_dapm_widgets = ARRAY_SIZE(mt2701_cs42448_asoc_card_dapm_widgets),
  288. };
  289. static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
  290. {
  291. struct snd_soc_card *card = &mt2701_cs42448_soc_card;
  292. int ret;
  293. int i;
  294. struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
  295. struct mt2701_cs42448_private *priv =
  296. devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
  297. GFP_KERNEL);
  298. struct device *dev = &pdev->dev;
  299. struct snd_soc_dai_link *dai_link;
  300. if (!priv)
  301. return -ENOMEM;
  302. platform_node = of_parse_phandle(pdev->dev.of_node,
  303. "mediatek,platform", 0);
  304. if (!platform_node) {
  305. dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
  306. return -EINVAL;
  307. }
  308. for_each_card_prelinks(card, i, dai_link) {
  309. if (dai_link->platforms->name)
  310. continue;
  311. dai_link->platforms->of_node = platform_node;
  312. }
  313. card->dev = dev;
  314. codec_node = of_parse_phandle(pdev->dev.of_node,
  315. "mediatek,audio-codec", 0);
  316. if (!codec_node) {
  317. dev_err(&pdev->dev,
  318. "Property 'audio-codec' missing or invalid\n");
  319. return -EINVAL;
  320. }
  321. for_each_card_prelinks(card, i, dai_link) {
  322. if (dai_link->codecs->name)
  323. continue;
  324. dai_link->codecs->of_node = codec_node;
  325. }
  326. codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
  327. "mediatek,audio-codec-bt-mrg", 0);
  328. if (!codec_node_bt_mrg) {
  329. dev_err(&pdev->dev,
  330. "Property 'audio-codec-bt-mrg' missing or invalid\n");
  331. return -EINVAL;
  332. }
  333. mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codecs->of_node
  334. = codec_node_bt_mrg;
  335. ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
  336. if (ret) {
  337. dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
  338. return ret;
  339. }
  340. priv->i2s1_in_mux_gpio_sel_1 =
  341. of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
  342. if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
  343. ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
  344. "i2s1_in_mux_gpio_sel_1");
  345. if (ret)
  346. dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
  347. __func__, ret);
  348. gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
  349. }
  350. priv->i2s1_in_mux_gpio_sel_2 =
  351. of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
  352. if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
  353. ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
  354. "i2s1_in_mux_gpio_sel_2");
  355. if (ret)
  356. dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
  357. __func__, ret);
  358. gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
  359. }
  360. snd_soc_card_set_drvdata(card, priv);
  361. ret = devm_snd_soc_register_card(&pdev->dev, card);
  362. if (ret)
  363. dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
  364. __func__, ret);
  365. return ret;
  366. }
  367. #ifdef CONFIG_OF
  368. static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
  369. {.compatible = "mediatek,mt2701-cs42448-machine",},
  370. {}
  371. };
  372. #endif
  373. static struct platform_driver mt2701_cs42448_machine = {
  374. .driver = {
  375. .name = "mt2701-cs42448",
  376. #ifdef CONFIG_OF
  377. .of_match_table = mt2701_cs42448_machine_dt_match,
  378. #endif
  379. },
  380. .probe = mt2701_cs42448_machine_probe,
  381. };
  382. module_platform_driver(mt2701_cs42448_machine);
  383. /* Module information */
  384. MODULE_DESCRIPTION("MT2701 CS42448 ALSA SoC machine driver");
  385. MODULE_AUTHOR("Ir Lian <[email protected]>");
  386. MODULE_LICENSE("GPL v2");
  387. MODULE_ALIAS("mt2701 cs42448 soc card");