mt2701-afe-common.h 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mt2701-afe-common.h -- Mediatek 2701 audio driver definitions
  4. *
  5. * Copyright (c) 2016 MediaTek Inc.
  6. * Author: Garlic Tseng <[email protected]>
  7. */
  8. #ifndef _MT_2701_AFE_COMMON_H_
  9. #define _MT_2701_AFE_COMMON_H_
  10. #include <sound/soc.h>
  11. #include <linux/clk.h>
  12. #include <linux/regmap.h>
  13. #include "mt2701-reg.h"
  14. #include "../common/mtk-base-afe.h"
  15. #define MT2701_PLL_DOMAIN_0_RATE 98304000
  16. #define MT2701_PLL_DOMAIN_1_RATE 90316800
  17. enum {
  18. MT2701_MEMIF_DL1,
  19. MT2701_MEMIF_DL2,
  20. MT2701_MEMIF_DL3,
  21. MT2701_MEMIF_DL4,
  22. MT2701_MEMIF_DL5,
  23. MT2701_MEMIF_DL_SINGLE_NUM,
  24. MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
  25. MT2701_MEMIF_UL1,
  26. MT2701_MEMIF_UL2,
  27. MT2701_MEMIF_UL3,
  28. MT2701_MEMIF_UL4,
  29. MT2701_MEMIF_UL5,
  30. MT2701_MEMIF_DLBT,
  31. MT2701_MEMIF_ULBT,
  32. MT2701_MEMIF_NUM,
  33. MT2701_IO_I2S = MT2701_MEMIF_NUM,
  34. MT2701_IO_2ND_I2S,
  35. MT2701_IO_3RD_I2S,
  36. MT2701_IO_4TH_I2S,
  37. MT2701_IO_5TH_I2S,
  38. MT2701_IO_6TH_I2S,
  39. MT2701_IO_MRG,
  40. };
  41. enum {
  42. MT2701_IRQ_ASYS_IRQ1,
  43. MT2701_IRQ_ASYS_IRQ2,
  44. MT2701_IRQ_ASYS_IRQ3,
  45. MT2701_IRQ_ASYS_END,
  46. };
  47. enum audio_base_clock {
  48. MT2701_INFRA_SYS_AUDIO,
  49. MT2701_TOP_AUD_MCLK_SRC0,
  50. MT2701_TOP_AUD_MCLK_SRC1,
  51. MT2701_TOP_AUD_A1SYS,
  52. MT2701_TOP_AUD_A2SYS,
  53. MT2701_AUDSYS_AFE,
  54. MT2701_AUDSYS_AFE_CONN,
  55. MT2701_AUDSYS_A1SYS,
  56. MT2701_AUDSYS_A2SYS,
  57. MT2701_BASE_CLK_NUM,
  58. };
  59. struct mt2701_i2s_data {
  60. int i2s_ctrl_reg;
  61. int i2s_asrc_fs_shift;
  62. int i2s_asrc_fs_mask;
  63. };
  64. struct mt2701_i2s_path {
  65. int mclk_rate;
  66. int on[MTK_STREAM_NUM];
  67. int occupied[MTK_STREAM_NUM];
  68. const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
  69. struct clk *hop_ck[MTK_STREAM_NUM];
  70. struct clk *sel_ck;
  71. struct clk *div_ck;
  72. struct clk *mclk_ck;
  73. struct clk *asrco_ck;
  74. };
  75. struct mt2701_soc_variants {
  76. bool has_one_heart_mode;
  77. int i2s_num;
  78. };
  79. struct mt2701_afe_private {
  80. struct mt2701_i2s_path *i2s_path;
  81. struct clk *base_ck[MT2701_BASE_CLK_NUM];
  82. struct clk *mrgif_ck;
  83. bool mrg_enable[MTK_STREAM_NUM];
  84. const struct mt2701_soc_variants *soc;
  85. };
  86. #endif