skl-sst.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * skl-sst.c - HDA DSP library functions for SKL platform
  4. *
  5. * Copyright (C) 2014-15, Intel Corporation.
  6. * Author:Rafal Redzimski <[email protected]>
  7. * Jeeja KP <[email protected]>
  8. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  9. */
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/err.h>
  14. #include <linux/uuid.h>
  15. #include "../common/sst-dsp.h"
  16. #include "../common/sst-dsp-priv.h"
  17. #include "../common/sst-ipc.h"
  18. #include "skl.h"
  19. #define SKL_BASEFW_TIMEOUT 300
  20. #define SKL_INIT_TIMEOUT 1000
  21. /* Intel HD Audio SRAM Window 0*/
  22. #define SKL_ADSP_SRAM0_BASE 0x8000
  23. /* Firmware status window */
  24. #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE
  25. #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4)
  26. #define SKL_NUM_MODULES 1
  27. static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
  28. {
  29. u32 cur_sts;
  30. cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
  31. return (cur_sts == status);
  32. }
  33. static int skl_transfer_firmware(struct sst_dsp *ctx,
  34. const void *basefw, u32 base_fw_size)
  35. {
  36. int ret = 0;
  37. ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size,
  38. true);
  39. if (ret < 0)
  40. return ret;
  41. ret = sst_dsp_register_poll(ctx,
  42. SKL_ADSP_FW_STATUS,
  43. SKL_FW_STS_MASK,
  44. SKL_FW_RFW_START,
  45. SKL_BASEFW_TIMEOUT,
  46. "Firmware boot");
  47. ctx->cl_dev.ops.cl_stop_dma(ctx);
  48. return ret;
  49. }
  50. #define SKL_ADSP_FW_BIN_HDR_OFFSET 0x284
  51. static int skl_load_base_firmware(struct sst_dsp *ctx)
  52. {
  53. int ret = 0, i;
  54. struct skl_dev *skl = ctx->thread_context;
  55. struct firmware stripped_fw;
  56. u32 reg;
  57. skl->boot_complete = false;
  58. init_waitqueue_head(&skl->boot_wait);
  59. if (ctx->fw == NULL) {
  60. ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
  61. if (ret < 0) {
  62. dev_err(ctx->dev, "Request firmware failed %d\n", ret);
  63. return -EIO;
  64. }
  65. }
  66. /* prase uuids on first boot */
  67. if (skl->is_first_boot) {
  68. ret = snd_skl_parse_uuids(ctx, ctx->fw, SKL_ADSP_FW_BIN_HDR_OFFSET, 0);
  69. if (ret < 0) {
  70. dev_err(ctx->dev, "UUID parsing err: %d\n", ret);
  71. release_firmware(ctx->fw);
  72. skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
  73. return ret;
  74. }
  75. }
  76. /* check for extended manifest */
  77. stripped_fw.data = ctx->fw->data;
  78. stripped_fw.size = ctx->fw->size;
  79. skl_dsp_strip_extended_manifest(&stripped_fw);
  80. ret = skl_dsp_boot(ctx);
  81. if (ret < 0) {
  82. dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
  83. goto skl_load_base_firmware_failed;
  84. }
  85. ret = skl_cldma_prepare(ctx);
  86. if (ret < 0) {
  87. dev_err(ctx->dev, "CL dma prepare failed : %d\n", ret);
  88. goto skl_load_base_firmware_failed;
  89. }
  90. /* enable Interrupt */
  91. skl_ipc_int_enable(ctx);
  92. skl_ipc_op_int_enable(ctx);
  93. /* check ROM Status */
  94. for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
  95. if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
  96. dev_dbg(ctx->dev,
  97. "ROM loaded, we can continue with FW loading\n");
  98. break;
  99. }
  100. mdelay(1);
  101. }
  102. if (!i) {
  103. reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
  104. dev_err(ctx->dev,
  105. "Timeout waiting for ROM init done, reg:0x%x\n", reg);
  106. ret = -EIO;
  107. goto transfer_firmware_failed;
  108. }
  109. ret = skl_transfer_firmware(ctx, stripped_fw.data, stripped_fw.size);
  110. if (ret < 0) {
  111. dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
  112. goto transfer_firmware_failed;
  113. } else {
  114. ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
  115. msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
  116. if (ret == 0) {
  117. dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
  118. ret = -EIO;
  119. goto transfer_firmware_failed;
  120. }
  121. dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
  122. skl->fw_loaded = true;
  123. }
  124. return 0;
  125. transfer_firmware_failed:
  126. ctx->cl_dev.ops.cl_cleanup_controller(ctx);
  127. skl_load_base_firmware_failed:
  128. skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
  129. release_firmware(ctx->fw);
  130. ctx->fw = NULL;
  131. return ret;
  132. }
  133. static int skl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
  134. {
  135. int ret;
  136. struct skl_ipc_dxstate_info dx;
  137. struct skl_dev *skl = ctx->thread_context;
  138. unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
  139. /* If core0 is being turned on, we need to load the FW */
  140. if (core_id == SKL_DSP_CORE0_ID) {
  141. ret = skl_load_base_firmware(ctx);
  142. if (ret < 0) {
  143. dev_err(ctx->dev, "unable to load firmware\n");
  144. return ret;
  145. }
  146. /* load libs as they are also lost on D3 */
  147. if (skl->lib_count > 1) {
  148. ret = ctx->fw_ops.load_library(ctx, skl->lib_info,
  149. skl->lib_count);
  150. if (ret < 0) {
  151. dev_err(ctx->dev, "reload libs failed: %d\n",
  152. ret);
  153. return ret;
  154. }
  155. }
  156. }
  157. /*
  158. * If any core other than core 0 is being moved to D0, enable the
  159. * core and send the set dx IPC for the core.
  160. */
  161. if (core_id != SKL_DSP_CORE0_ID) {
  162. ret = skl_dsp_enable_core(ctx, core_mask);
  163. if (ret < 0)
  164. return ret;
  165. dx.core_mask = core_mask;
  166. dx.dx_mask = core_mask;
  167. ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
  168. SKL_BASE_FW_MODULE_ID, &dx);
  169. if (ret < 0) {
  170. dev_err(ctx->dev, "Failed to set dsp to D0:core id= %d\n",
  171. core_id);
  172. skl_dsp_disable_core(ctx, core_mask);
  173. }
  174. }
  175. skl->cores.state[core_id] = SKL_DSP_RUNNING;
  176. return 0;
  177. }
  178. static int skl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
  179. {
  180. int ret;
  181. struct skl_ipc_dxstate_info dx;
  182. struct skl_dev *skl = ctx->thread_context;
  183. unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
  184. dx.core_mask = core_mask;
  185. dx.dx_mask = SKL_IPC_D3_MASK;
  186. ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
  187. if (ret < 0)
  188. dev_err(ctx->dev, "set Dx core %d fail: %d\n", core_id, ret);
  189. if (core_id == SKL_DSP_CORE0_ID) {
  190. /* disable Interrupt */
  191. ctx->cl_dev.ops.cl_cleanup_controller(ctx);
  192. skl_cldma_int_disable(ctx);
  193. skl_ipc_op_int_disable(ctx);
  194. skl_ipc_int_disable(ctx);
  195. }
  196. ret = skl_dsp_disable_core(ctx, core_mask);
  197. if (ret < 0)
  198. return ret;
  199. skl->cores.state[core_id] = SKL_DSP_RESET;
  200. return ret;
  201. }
  202. static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
  203. {
  204. return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
  205. }
  206. /*
  207. * since get/set_module are called from DAPM context,
  208. * we don't need lock for usage count
  209. */
  210. static int skl_get_module(struct sst_dsp *ctx, u16 mod_id)
  211. {
  212. struct skl_module_table *module;
  213. list_for_each_entry(module, &ctx->module_list, list) {
  214. if (module->mod_info->mod_id == mod_id)
  215. return ++module->usage_cnt;
  216. }
  217. return -EINVAL;
  218. }
  219. static int skl_put_module(struct sst_dsp *ctx, u16 mod_id)
  220. {
  221. struct skl_module_table *module;
  222. list_for_each_entry(module, &ctx->module_list, list) {
  223. if (module->mod_info->mod_id == mod_id)
  224. return --module->usage_cnt;
  225. }
  226. return -EINVAL;
  227. }
  228. static struct skl_module_table *skl_fill_module_table(struct sst_dsp *ctx,
  229. char *mod_name, int mod_id)
  230. {
  231. const struct firmware *fw;
  232. struct skl_module_table *skl_module;
  233. unsigned int size;
  234. int ret;
  235. ret = request_firmware(&fw, mod_name, ctx->dev);
  236. if (ret < 0) {
  237. dev_err(ctx->dev, "Request Module %s failed :%d\n",
  238. mod_name, ret);
  239. return NULL;
  240. }
  241. skl_module = devm_kzalloc(ctx->dev, sizeof(*skl_module), GFP_KERNEL);
  242. if (skl_module == NULL) {
  243. release_firmware(fw);
  244. return NULL;
  245. }
  246. size = sizeof(*skl_module->mod_info);
  247. skl_module->mod_info = devm_kzalloc(ctx->dev, size, GFP_KERNEL);
  248. if (skl_module->mod_info == NULL) {
  249. release_firmware(fw);
  250. return NULL;
  251. }
  252. skl_module->mod_info->mod_id = mod_id;
  253. skl_module->mod_info->fw = fw;
  254. list_add(&skl_module->list, &ctx->module_list);
  255. return skl_module;
  256. }
  257. /* get a module from it's unique ID */
  258. static struct skl_module_table *skl_module_get_from_id(
  259. struct sst_dsp *ctx, u16 mod_id)
  260. {
  261. struct skl_module_table *module;
  262. if (list_empty(&ctx->module_list)) {
  263. dev_err(ctx->dev, "Module list is empty\n");
  264. return NULL;
  265. }
  266. list_for_each_entry(module, &ctx->module_list, list) {
  267. if (module->mod_info->mod_id == mod_id)
  268. return module;
  269. }
  270. return NULL;
  271. }
  272. static int skl_transfer_module(struct sst_dsp *ctx, const void *data,
  273. u32 size, u16 mod_id, u8 table_id, bool is_module)
  274. {
  275. int ret, bytes_left, curr_pos;
  276. struct skl_dev *skl = ctx->thread_context;
  277. skl->mod_load_complete = false;
  278. bytes_left = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, data, size, false);
  279. if (bytes_left < 0)
  280. return bytes_left;
  281. /* check is_module flag to load module or library */
  282. if (is_module)
  283. ret = skl_ipc_load_modules(&skl->ipc, SKL_NUM_MODULES, &mod_id);
  284. else
  285. ret = skl_sst_ipc_load_library(&skl->ipc, 0, table_id, false);
  286. if (ret < 0) {
  287. dev_err(ctx->dev, "Failed to Load %s with err %d\n",
  288. is_module ? "module" : "lib", ret);
  289. goto out;
  290. }
  291. /*
  292. * if bytes_left > 0 then wait for BDL complete interrupt and
  293. * copy the next chunk till bytes_left is 0. if bytes_left is
  294. * zero, then wait for load module IPC reply
  295. */
  296. while (bytes_left > 0) {
  297. curr_pos = size - bytes_left;
  298. ret = skl_cldma_wait_interruptible(ctx);
  299. if (ret < 0)
  300. goto out;
  301. bytes_left = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx,
  302. data + curr_pos,
  303. bytes_left, false);
  304. }
  305. ret = wait_event_timeout(skl->mod_load_wait, skl->mod_load_complete,
  306. msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
  307. if (ret == 0 || !skl->mod_load_status) {
  308. dev_err(ctx->dev, "Module Load failed\n");
  309. ret = -EIO;
  310. }
  311. out:
  312. ctx->cl_dev.ops.cl_stop_dma(ctx);
  313. return ret;
  314. }
  315. static int
  316. skl_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
  317. {
  318. struct skl_dev *skl = ctx->thread_context;
  319. struct firmware stripped_fw;
  320. int ret, i;
  321. /* library indices start from 1 to N. 0 represents base FW */
  322. for (i = 1; i < lib_count; i++) {
  323. ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
  324. SKL_ADSP_FW_BIN_HDR_OFFSET, i);
  325. if (ret < 0)
  326. goto load_library_failed;
  327. ret = skl_transfer_module(ctx, stripped_fw.data,
  328. stripped_fw.size, 0, i, false);
  329. if (ret < 0)
  330. goto load_library_failed;
  331. }
  332. return 0;
  333. load_library_failed:
  334. skl_release_library(linfo, lib_count);
  335. return ret;
  336. }
  337. static int skl_load_module(struct sst_dsp *ctx, u16 mod_id, u8 *guid)
  338. {
  339. struct skl_module_table *module_entry = NULL;
  340. int ret = 0;
  341. char mod_name[64]; /* guid str = 32 chars + 4 hyphens */
  342. snprintf(mod_name, sizeof(mod_name), "intel/dsp_fw_%pUL.bin", guid);
  343. module_entry = skl_module_get_from_id(ctx, mod_id);
  344. if (module_entry == NULL) {
  345. module_entry = skl_fill_module_table(ctx, mod_name, mod_id);
  346. if (module_entry == NULL) {
  347. dev_err(ctx->dev, "Failed to Load module\n");
  348. return -EINVAL;
  349. }
  350. }
  351. if (!module_entry->usage_cnt) {
  352. ret = skl_transfer_module(ctx, module_entry->mod_info->fw->data,
  353. module_entry->mod_info->fw->size,
  354. mod_id, 0, true);
  355. if (ret < 0) {
  356. dev_err(ctx->dev, "Failed to Load module\n");
  357. return ret;
  358. }
  359. }
  360. ret = skl_get_module(ctx, mod_id);
  361. return ret;
  362. }
  363. static int skl_unload_module(struct sst_dsp *ctx, u16 mod_id)
  364. {
  365. int usage_cnt;
  366. struct skl_dev *skl = ctx->thread_context;
  367. int ret = 0;
  368. usage_cnt = skl_put_module(ctx, mod_id);
  369. if (usage_cnt < 0) {
  370. dev_err(ctx->dev, "Module bad usage cnt!:%d\n", usage_cnt);
  371. return -EIO;
  372. }
  373. /* if module is used by others return, no need to unload */
  374. if (usage_cnt > 0)
  375. return 0;
  376. ret = skl_ipc_unload_modules(&skl->ipc,
  377. SKL_NUM_MODULES, &mod_id);
  378. if (ret < 0) {
  379. dev_err(ctx->dev, "Failed to UnLoad module\n");
  380. skl_get_module(ctx, mod_id);
  381. return ret;
  382. }
  383. return ret;
  384. }
  385. void skl_clear_module_cnt(struct sst_dsp *ctx)
  386. {
  387. struct skl_module_table *module;
  388. if (list_empty(&ctx->module_list))
  389. return;
  390. list_for_each_entry(module, &ctx->module_list, list) {
  391. module->usage_cnt = 0;
  392. }
  393. }
  394. EXPORT_SYMBOL_GPL(skl_clear_module_cnt);
  395. static void skl_clear_module_table(struct sst_dsp *ctx)
  396. {
  397. struct skl_module_table *module, *tmp;
  398. if (list_empty(&ctx->module_list))
  399. return;
  400. list_for_each_entry_safe(module, tmp, &ctx->module_list, list) {
  401. list_del(&module->list);
  402. release_firmware(module->mod_info->fw);
  403. }
  404. }
  405. static const struct skl_dsp_fw_ops skl_fw_ops = {
  406. .set_state_D0 = skl_set_dsp_D0,
  407. .set_state_D3 = skl_set_dsp_D3,
  408. .load_fw = skl_load_base_firmware,
  409. .get_fw_errcode = skl_get_errorcode,
  410. .load_library = skl_load_library,
  411. .load_mod = skl_load_module,
  412. .unload_mod = skl_unload_module,
  413. };
  414. static struct sst_ops skl_ops = {
  415. .irq_handler = skl_dsp_sst_interrupt,
  416. .write = sst_shim32_write,
  417. .read = sst_shim32_read,
  418. .free = skl_dsp_free,
  419. };
  420. static struct sst_dsp_device skl_dev = {
  421. .thread = skl_dsp_irq_thread_handler,
  422. .ops = &skl_ops,
  423. };
  424. int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
  425. const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
  426. struct skl_dev **dsp)
  427. {
  428. struct skl_dev *skl;
  429. struct sst_dsp *sst;
  430. int ret;
  431. ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
  432. if (ret < 0) {
  433. dev_err(dev, "%s: no device\n", __func__);
  434. return ret;
  435. }
  436. skl = *dsp;
  437. sst = skl->dsp;
  438. sst->addr.lpe = mmio_base;
  439. sst->addr.shim = mmio_base;
  440. sst->addr.sram0_base = SKL_ADSP_SRAM0_BASE;
  441. sst->addr.sram1_base = SKL_ADSP_SRAM1_BASE;
  442. sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
  443. sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
  444. sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
  445. SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
  446. ret = skl_ipc_init(dev, skl);
  447. if (ret) {
  448. skl_dsp_free(sst);
  449. return ret;
  450. }
  451. sst->fw_ops = skl_fw_ops;
  452. return skl_dsp_acquire_irq(sst);
  453. }
  454. EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
  455. int skl_sst_init_fw(struct device *dev, struct skl_dev *skl)
  456. {
  457. int ret;
  458. struct sst_dsp *sst = skl->dsp;
  459. ret = sst->fw_ops.load_fw(sst);
  460. if (ret < 0) {
  461. dev_err(dev, "Load base fw failed : %d\n", ret);
  462. return ret;
  463. }
  464. skl_dsp_init_core_state(sst);
  465. if (skl->lib_count > 1) {
  466. ret = sst->fw_ops.load_library(sst, skl->lib_info,
  467. skl->lib_count);
  468. if (ret < 0) {
  469. dev_err(dev, "Load Library failed : %x\n", ret);
  470. return ret;
  471. }
  472. }
  473. skl->is_first_boot = false;
  474. return 0;
  475. }
  476. EXPORT_SYMBOL_GPL(skl_sst_init_fw);
  477. void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
  478. {
  479. if (skl->dsp->fw)
  480. release_firmware(skl->dsp->fw);
  481. skl_clear_module_table(skl->dsp);
  482. skl_freeup_uuid_list(skl);
  483. skl_ipc_free(&skl->ipc);
  484. skl->dsp->ops->free(skl->dsp);
  485. if (skl->boot_complete) {
  486. skl->dsp->cl_dev.ops.cl_cleanup_controller(skl->dsp);
  487. skl_cldma_int_disable(skl->dsp);
  488. }
  489. }
  490. EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
  491. MODULE_LICENSE("GPL v2");
  492. MODULE_DESCRIPTION("Intel Skylake IPC driver");