skl-i2s.h 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * skl-i2s.h - i2s blob mapping
  4. *
  5. * Copyright (C) 2017 Intel Corp
  6. * Author: Subhransu S. Prusty < [email protected]>
  7. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  8. *
  9. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10. */
  11. #ifndef __SOUND_SOC_SKL_I2S_H
  12. #define __SOUND_SOC_SKL_I2S_H
  13. #define SKL_I2S_MAX_TIME_SLOTS 8
  14. #define SKL_MCLK_DIV_CLK_SRC_MASK GENMASK(17, 16)
  15. #define SKL_MNDSS_DIV_CLK_SRC_MASK GENMASK(21, 20)
  16. #define SKL_SHIFT(x) (ffs(x) - 1)
  17. #define SKL_MCLK_DIV_RATIO_MASK GENMASK(11, 0)
  18. #define is_legacy_blob(x) (x.signature != 0xEE)
  19. #define ext_to_legacy_blob(i2s_config_blob_ext) \
  20. ((struct skl_i2s_config_blob_legacy *) i2s_config_blob_ext)
  21. #define get_clk_src(mclk, mask) \
  22. ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask))
  23. struct skl_i2s_config {
  24. u32 ssc0;
  25. u32 ssc1;
  26. u32 sscto;
  27. u32 sspsp;
  28. u32 sstsa;
  29. u32 ssrsa;
  30. u32 ssc2;
  31. u32 sspsp2;
  32. u32 ssc3;
  33. u32 ssioc;
  34. } __packed;
  35. struct skl_i2s_config_mclk {
  36. u32 mdivctrl;
  37. u32 mdivr;
  38. };
  39. struct skl_i2s_config_mclk_ext {
  40. u32 mdivctrl;
  41. u32 mdivr_count;
  42. u32 mdivr[];
  43. } __packed;
  44. struct skl_i2s_config_blob_signature {
  45. u32 minor_ver : 8;
  46. u32 major_ver : 8;
  47. u32 resvdz : 8;
  48. u32 signature : 8;
  49. } __packed;
  50. struct skl_i2s_config_blob_header {
  51. struct skl_i2s_config_blob_signature sig;
  52. u32 size;
  53. };
  54. /**
  55. * struct skl_i2s_config_blob_legacy - Structure defines I2S Gateway
  56. * configuration legacy blob
  57. *
  58. * @gtw_attr: Gateway attribute for the I2S Gateway
  59. * @tdm_ts_group: TDM slot mapping against channels in the Gateway.
  60. * @i2s_cfg: I2S HW registers
  61. * @mclk: MCLK clock source and divider values
  62. */
  63. struct skl_i2s_config_blob_legacy {
  64. u32 gtw_attr;
  65. u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
  66. struct skl_i2s_config i2s_cfg;
  67. struct skl_i2s_config_mclk mclk;
  68. };
  69. struct skl_i2s_config_blob_ext {
  70. u32 gtw_attr;
  71. struct skl_i2s_config_blob_header hdr;
  72. u32 tdm_ts_group[SKL_I2S_MAX_TIME_SLOTS];
  73. struct skl_i2s_config i2s_cfg;
  74. struct skl_i2s_config_mclk_ext mclk;
  75. } __packed;
  76. #endif /* __SOUND_SOC_SKL_I2S_H */