cldma.c 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
  4. //
  5. // Author: Cezary Rojewski <[email protected]>
  6. //
  7. #include <linux/pci.h>
  8. #include <sound/hda_register.h>
  9. #include <sound/hdaudio_ext.h>
  10. #include "cldma.h"
  11. #include "registers.h"
  12. /* Stream Registers */
  13. #define AZX_CL_SD_BASE 0x80
  14. #define AZX_SD_CTL_STRM_MASK GENMASK(23, 20)
  15. #define AZX_SD_CTL_STRM(s) (((s)->stream_tag << 20) & AZX_SD_CTL_STRM_MASK)
  16. #define AZX_SD_BDLPL_BDLPLBA_MASK GENMASK(31, 7)
  17. #define AZX_SD_BDLPL_BDLPLBA(lb) ((lb) & AZX_SD_BDLPL_BDLPLBA_MASK)
  18. /* Software Position Based FIFO Capability Registers */
  19. #define AZX_CL_SPBFCS 0x20
  20. #define AZX_REG_CL_SPBFCTL (AZX_CL_SPBFCS + 0x4)
  21. #define AZX_REG_CL_SD_SPIB (AZX_CL_SPBFCS + 0x8)
  22. #define AVS_CL_OP_INTERVAL_US 3
  23. #define AVS_CL_OP_TIMEOUT_US 300
  24. #define AVS_CL_IOC_TIMEOUT_MS 300
  25. #define AVS_CL_STREAM_INDEX 0
  26. struct hda_cldma {
  27. struct device *dev;
  28. struct hdac_bus *bus;
  29. void __iomem *dsp_ba;
  30. unsigned int buffer_size;
  31. unsigned int num_periods;
  32. unsigned int stream_tag;
  33. void __iomem *sd_addr;
  34. struct snd_dma_buffer dmab_data;
  35. struct snd_dma_buffer dmab_bdl;
  36. struct delayed_work memcpy_work;
  37. struct completion completion;
  38. /* runtime */
  39. void *position;
  40. unsigned int remaining;
  41. unsigned int sd_status;
  42. };
  43. static void cldma_memcpy_work(struct work_struct *work);
  44. struct hda_cldma code_loader = {
  45. .stream_tag = AVS_CL_STREAM_INDEX + 1,
  46. .memcpy_work = __DELAYED_WORK_INITIALIZER(code_loader.memcpy_work, cldma_memcpy_work, 0),
  47. .completion = COMPLETION_INITIALIZER(code_loader.completion),
  48. };
  49. void hda_cldma_fill(struct hda_cldma *cl)
  50. {
  51. unsigned int size, offset;
  52. if (cl->remaining > cl->buffer_size)
  53. size = cl->buffer_size;
  54. else
  55. size = cl->remaining;
  56. offset = snd_hdac_stream_readl(cl, CL_SD_SPIB);
  57. if (offset + size > cl->buffer_size) {
  58. unsigned int ss;
  59. ss = cl->buffer_size - offset;
  60. memcpy(cl->dmab_data.area + offset, cl->position, ss);
  61. offset = 0;
  62. size -= ss;
  63. cl->position += ss;
  64. cl->remaining -= ss;
  65. }
  66. memcpy(cl->dmab_data.area + offset, cl->position, size);
  67. cl->position += size;
  68. cl->remaining -= size;
  69. snd_hdac_stream_writel(cl, CL_SD_SPIB, offset + size);
  70. }
  71. static void cldma_memcpy_work(struct work_struct *work)
  72. {
  73. struct hda_cldma *cl = container_of(work, struct hda_cldma, memcpy_work.work);
  74. int ret;
  75. ret = hda_cldma_start(cl);
  76. if (ret < 0) {
  77. dev_err(cl->dev, "cldma set RUN failed: %d\n", ret);
  78. return;
  79. }
  80. while (true) {
  81. ret = wait_for_completion_timeout(&cl->completion,
  82. msecs_to_jiffies(AVS_CL_IOC_TIMEOUT_MS));
  83. if (!ret) {
  84. dev_err(cl->dev, "cldma IOC timeout\n");
  85. break;
  86. }
  87. if (!(cl->sd_status & SD_INT_COMPLETE)) {
  88. dev_err(cl->dev, "cldma transfer error, SD status: 0x%08x\n",
  89. cl->sd_status);
  90. break;
  91. }
  92. if (!cl->remaining)
  93. break;
  94. reinit_completion(&cl->completion);
  95. hda_cldma_fill(cl);
  96. /* enable CLDMA interrupt */
  97. snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA,
  98. AVS_ADSP_ADSPIC_CLDMA);
  99. }
  100. }
  101. void hda_cldma_transfer(struct hda_cldma *cl, unsigned long start_delay)
  102. {
  103. if (!cl->remaining)
  104. return;
  105. reinit_completion(&cl->completion);
  106. /* fill buffer with the first chunk before scheduling run */
  107. hda_cldma_fill(cl);
  108. schedule_delayed_work(&cl->memcpy_work, start_delay);
  109. }
  110. int hda_cldma_start(struct hda_cldma *cl)
  111. {
  112. unsigned int reg;
  113. /* enable interrupts */
  114. snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA,
  115. AVS_ADSP_ADSPIC_CLDMA);
  116. snd_hdac_stream_updateb(cl, SD_CTL, SD_INT_MASK | SD_CTL_DMA_START,
  117. SD_INT_MASK | SD_CTL_DMA_START);
  118. /* await DMA engine start */
  119. return snd_hdac_stream_readb_poll(cl, SD_CTL, reg, reg & SD_CTL_DMA_START,
  120. AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
  121. }
  122. int hda_cldma_stop(struct hda_cldma *cl)
  123. {
  124. unsigned int reg;
  125. int ret;
  126. /* disable interrupts */
  127. snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA, 0);
  128. snd_hdac_stream_updateb(cl, SD_CTL, SD_INT_MASK | SD_CTL_DMA_START, 0);
  129. /* await DMA engine stop */
  130. ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, !(reg & SD_CTL_DMA_START),
  131. AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
  132. cancel_delayed_work_sync(&cl->memcpy_work);
  133. return ret;
  134. }
  135. int hda_cldma_reset(struct hda_cldma *cl)
  136. {
  137. unsigned int reg;
  138. int ret;
  139. ret = hda_cldma_stop(cl);
  140. if (ret < 0) {
  141. dev_err(cl->dev, "cldma stop failed: %d\n", ret);
  142. return ret;
  143. }
  144. snd_hdac_stream_updateb(cl, SD_CTL, SD_CTL_STREAM_RESET, SD_CTL_STREAM_RESET);
  145. ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, (reg & SD_CTL_STREAM_RESET),
  146. AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
  147. if (ret < 0) {
  148. dev_err(cl->dev, "cldma set SRST failed: %d\n", ret);
  149. return ret;
  150. }
  151. snd_hdac_stream_updateb(cl, SD_CTL, SD_CTL_STREAM_RESET, 0);
  152. ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, !(reg & SD_CTL_STREAM_RESET),
  153. AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
  154. if (ret < 0) {
  155. dev_err(cl->dev, "cldma unset SRST failed: %d\n", ret);
  156. return ret;
  157. }
  158. return 0;
  159. }
  160. void hda_cldma_set_data(struct hda_cldma *cl, void *data, unsigned int size)
  161. {
  162. /* setup runtime */
  163. cl->position = data;
  164. cl->remaining = size;
  165. }
  166. static void cldma_setup_bdle(struct hda_cldma *cl, u32 bdle_size)
  167. {
  168. struct snd_dma_buffer *dmab = &cl->dmab_data;
  169. __le32 *bdl = (__le32 *)cl->dmab_bdl.area;
  170. int remaining = cl->buffer_size;
  171. int offset = 0;
  172. cl->num_periods = 0;
  173. while (remaining > 0) {
  174. phys_addr_t addr;
  175. int chunk;
  176. addr = snd_sgbuf_get_addr(dmab, offset);
  177. bdl[0] = cpu_to_le32(lower_32_bits(addr));
  178. bdl[1] = cpu_to_le32(upper_32_bits(addr));
  179. chunk = snd_sgbuf_get_chunk_size(dmab, offset, bdle_size);
  180. bdl[2] = cpu_to_le32(chunk);
  181. remaining -= chunk;
  182. /* set IOC only for the last entry */
  183. bdl[3] = (remaining > 0) ? 0 : cpu_to_le32(0x01);
  184. bdl += 4;
  185. offset += chunk;
  186. cl->num_periods++;
  187. }
  188. }
  189. void hda_cldma_setup(struct hda_cldma *cl)
  190. {
  191. dma_addr_t bdl_addr = cl->dmab_bdl.addr;
  192. cldma_setup_bdle(cl, cl->buffer_size / 2);
  193. snd_hdac_stream_writel(cl, SD_BDLPL, AZX_SD_BDLPL_BDLPLBA(lower_32_bits(bdl_addr)));
  194. snd_hdac_stream_writel(cl, SD_BDLPU, upper_32_bits(bdl_addr));
  195. snd_hdac_stream_writel(cl, SD_CBL, cl->buffer_size);
  196. snd_hdac_stream_writeb(cl, SD_LVI, cl->num_periods - 1);
  197. snd_hdac_stream_updatel(cl, SD_CTL, AZX_SD_CTL_STRM_MASK, AZX_SD_CTL_STRM(cl));
  198. /* enable spib */
  199. snd_hdac_stream_writel(cl, CL_SPBFCTL, 1);
  200. }
  201. static irqreturn_t cldma_irq_handler(int irq, void *dev_id)
  202. {
  203. struct hda_cldma *cl = dev_id;
  204. u32 adspis;
  205. adspis = snd_hdac_adsp_readl(cl, AVS_ADSP_REG_ADSPIS);
  206. if (adspis == UINT_MAX)
  207. return IRQ_NONE;
  208. if (!(adspis & AVS_ADSP_ADSPIS_CLDMA))
  209. return IRQ_NONE;
  210. cl->sd_status = snd_hdac_stream_readb(cl, SD_STS);
  211. dev_warn(cl->dev, "%s sd_status: 0x%08x\n", __func__, cl->sd_status);
  212. /* disable CLDMA interrupt */
  213. snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA, 0);
  214. complete(&cl->completion);
  215. return IRQ_HANDLED;
  216. }
  217. int hda_cldma_init(struct hda_cldma *cl, struct hdac_bus *bus, void __iomem *dsp_ba,
  218. unsigned int buffer_size)
  219. {
  220. struct pci_dev *pci = to_pci_dev(bus->dev);
  221. int ret;
  222. ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, buffer_size, &cl->dmab_data);
  223. if (ret < 0)
  224. return ret;
  225. ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, bus->dev, BDL_SIZE, &cl->dmab_bdl);
  226. if (ret < 0)
  227. goto alloc_err;
  228. cl->dev = bus->dev;
  229. cl->bus = bus;
  230. cl->dsp_ba = dsp_ba;
  231. cl->buffer_size = buffer_size;
  232. cl->sd_addr = dsp_ba + AZX_CL_SD_BASE;
  233. ret = pci_request_irq(pci, 0, cldma_irq_handler, NULL, cl, "CLDMA");
  234. if (ret < 0) {
  235. dev_err(cl->dev, "Failed to request CLDMA IRQ handler: %d\n", ret);
  236. goto req_err;
  237. }
  238. return 0;
  239. req_err:
  240. snd_dma_free_pages(&cl->dmab_bdl);
  241. alloc_err:
  242. snd_dma_free_pages(&cl->dmab_data);
  243. return ret;
  244. }
  245. void hda_cldma_free(struct hda_cldma *cl)
  246. {
  247. struct pci_dev *pci = to_pci_dev(cl->dev);
  248. pci_free_irq(pci, 0, cl);
  249. snd_dma_free_pages(&cl->dmab_data);
  250. snd_dma_free_pages(&cl->dmab_bdl);
  251. }