img-spdif-out.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IMG SPDIF output controller driver
  4. *
  5. * Copyright (C) 2015 Imagination Technologies Ltd.
  6. *
  7. * Author: Damien Horsley <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/reset.h>
  17. #include <sound/core.h>
  18. #include <sound/dmaengine_pcm.h>
  19. #include <sound/initval.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #define IMG_SPDIF_OUT_TX_FIFO 0x0
  24. #define IMG_SPDIF_OUT_CTL 0x4
  25. #define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4)
  26. #define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2)
  27. #define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0)
  28. #define IMG_SPDIF_OUT_CSL 0x14
  29. #define IMG_SPDIF_OUT_CSH_UV 0x18
  30. #define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT 0
  31. #define IMG_SPDIF_OUT_CSH_UV_CSH_MASK 0xff
  32. struct img_spdif_out {
  33. spinlock_t lock;
  34. void __iomem *base;
  35. struct clk *clk_sys;
  36. struct clk *clk_ref;
  37. struct snd_dmaengine_dai_dma_data dma_data;
  38. struct device *dev;
  39. struct reset_control *rst;
  40. u32 suspend_ctl;
  41. u32 suspend_csl;
  42. u32 suspend_csh;
  43. };
  44. static int img_spdif_out_runtime_suspend(struct device *dev)
  45. {
  46. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  47. clk_disable_unprepare(spdif->clk_ref);
  48. clk_disable_unprepare(spdif->clk_sys);
  49. return 0;
  50. }
  51. static int img_spdif_out_runtime_resume(struct device *dev)
  52. {
  53. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  54. int ret;
  55. ret = clk_prepare_enable(spdif->clk_sys);
  56. if (ret) {
  57. dev_err(dev, "clk_enable failed: %d\n", ret);
  58. return ret;
  59. }
  60. ret = clk_prepare_enable(spdif->clk_ref);
  61. if (ret) {
  62. dev_err(dev, "clk_enable failed: %d\n", ret);
  63. clk_disable_unprepare(spdif->clk_sys);
  64. return ret;
  65. }
  66. return 0;
  67. }
  68. static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
  69. u32 reg)
  70. {
  71. writel(val, spdif->base + reg);
  72. }
  73. static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
  74. {
  75. return readl(spdif->base + reg);
  76. }
  77. static void img_spdif_out_reset(struct img_spdif_out *spdif)
  78. {
  79. u32 ctl, status_low, status_high;
  80. ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
  81. ~IMG_SPDIF_OUT_CTL_SRT_MASK;
  82. status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  83. status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  84. reset_control_assert(spdif->rst);
  85. reset_control_deassert(spdif->rst);
  86. img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
  87. img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
  88. img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
  89. }
  90. static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
  91. struct snd_ctl_elem_info *uinfo)
  92. {
  93. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  94. uinfo->count = 1;
  95. return 0;
  96. }
  97. static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
  98. struct snd_ctl_elem_value *ucontrol)
  99. {
  100. ucontrol->value.iec958.status[0] = 0xff;
  101. ucontrol->value.iec958.status[1] = 0xff;
  102. ucontrol->value.iec958.status[2] = 0xff;
  103. ucontrol->value.iec958.status[3] = 0xff;
  104. ucontrol->value.iec958.status[4] = 0xff;
  105. return 0;
  106. }
  107. static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
  108. struct snd_ctl_elem_value *ucontrol)
  109. {
  110. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  111. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  112. u32 reg;
  113. unsigned long flags;
  114. spin_lock_irqsave(&spdif->lock, flags);
  115. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  116. ucontrol->value.iec958.status[0] = reg & 0xff;
  117. ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
  118. ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
  119. ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
  120. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  121. ucontrol->value.iec958.status[4] =
  122. (reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
  123. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  124. spin_unlock_irqrestore(&spdif->lock, flags);
  125. return 0;
  126. }
  127. static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
  128. struct snd_ctl_elem_value *ucontrol)
  129. {
  130. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  131. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  132. u32 reg;
  133. unsigned long flags;
  134. reg = ((u32)ucontrol->value.iec958.status[3] << 24);
  135. reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
  136. reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
  137. reg |= (u32)ucontrol->value.iec958.status[0];
  138. spin_lock_irqsave(&spdif->lock, flags);
  139. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
  140. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  141. reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
  142. reg |= (u32)ucontrol->value.iec958.status[4] <<
  143. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  144. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
  145. spin_unlock_irqrestore(&spdif->lock, flags);
  146. return 0;
  147. }
  148. static struct snd_kcontrol_new img_spdif_out_controls[] = {
  149. {
  150. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  151. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  152. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
  153. .info = img_spdif_out_info,
  154. .get = img_spdif_out_get_status_mask
  155. },
  156. {
  157. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  158. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  159. .info = img_spdif_out_info,
  160. .get = img_spdif_out_get_status,
  161. .put = img_spdif_out_set_status
  162. }
  163. };
  164. static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
  165. struct snd_soc_dai *dai)
  166. {
  167. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  168. u32 reg;
  169. unsigned long flags;
  170. switch (cmd) {
  171. case SNDRV_PCM_TRIGGER_START:
  172. case SNDRV_PCM_TRIGGER_RESUME:
  173. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  174. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  175. reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
  176. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  177. break;
  178. case SNDRV_PCM_TRIGGER_STOP:
  179. case SNDRV_PCM_TRIGGER_SUSPEND:
  180. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  181. spin_lock_irqsave(&spdif->lock, flags);
  182. img_spdif_out_reset(spdif);
  183. spin_unlock_irqrestore(&spdif->lock, flags);
  184. break;
  185. default:
  186. return -EINVAL;
  187. }
  188. return 0;
  189. }
  190. static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
  191. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  192. {
  193. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  194. unsigned int channels;
  195. long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
  196. u32 reg;
  197. snd_pcm_format_t format;
  198. rate = params_rate(params);
  199. format = params_format(params);
  200. channels = params_channels(params);
  201. dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
  202. rate, channels, format);
  203. if (format != SNDRV_PCM_FORMAT_S32_LE)
  204. return -EINVAL;
  205. if (channels != 2)
  206. return -EINVAL;
  207. pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
  208. if (pre_div_a < 0)
  209. return pre_div_a;
  210. pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
  211. if (pre_div_b < 0)
  212. return pre_div_b;
  213. diff_a = abs((pre_div_a / 256) - rate);
  214. diff_b = abs((pre_div_b / 384) - rate);
  215. /* If diffs are equal, use lower clock rate */
  216. if (diff_a > diff_b)
  217. clk_set_rate(spdif->clk_ref, pre_div_b);
  218. else
  219. clk_set_rate(spdif->clk_ref, pre_div_a);
  220. /*
  221. * Another driver (eg machine driver) may have rejected the above
  222. * change. Get the current rate and set the register bit according to
  223. * the new min diff
  224. */
  225. clk_rate = clk_get_rate(spdif->clk_ref);
  226. diff_a = abs((clk_rate / 256) - rate);
  227. diff_b = abs((clk_rate / 384) - rate);
  228. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  229. if (diff_a <= diff_b)
  230. reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
  231. else
  232. reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
  233. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  234. return 0;
  235. }
  236. static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
  237. .trigger = img_spdif_out_trigger,
  238. .hw_params = img_spdif_out_hw_params
  239. };
  240. static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
  241. {
  242. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  243. snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
  244. snd_soc_add_dai_controls(dai, img_spdif_out_controls,
  245. ARRAY_SIZE(img_spdif_out_controls));
  246. return 0;
  247. }
  248. static struct snd_soc_dai_driver img_spdif_out_dai = {
  249. .probe = img_spdif_out_dai_probe,
  250. .playback = {
  251. .channels_min = 2,
  252. .channels_max = 2,
  253. .rates = SNDRV_PCM_RATE_8000_192000,
  254. .formats = SNDRV_PCM_FMTBIT_S32_LE
  255. },
  256. .ops = &img_spdif_out_dai_ops
  257. };
  258. static const struct snd_soc_component_driver img_spdif_out_component = {
  259. .name = "img-spdif-out",
  260. .legacy_dai_naming = 1,
  261. };
  262. static int img_spdif_out_probe(struct platform_device *pdev)
  263. {
  264. struct img_spdif_out *spdif;
  265. struct resource *res;
  266. void __iomem *base;
  267. int ret;
  268. struct device *dev = &pdev->dev;
  269. spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
  270. if (!spdif)
  271. return -ENOMEM;
  272. platform_set_drvdata(pdev, spdif);
  273. spdif->dev = &pdev->dev;
  274. base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  275. if (IS_ERR(base))
  276. return PTR_ERR(base);
  277. spdif->base = base;
  278. spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
  279. if (IS_ERR(spdif->rst))
  280. return dev_err_probe(&pdev->dev, PTR_ERR(spdif->rst),
  281. "No top level reset found\n");
  282. spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
  283. if (IS_ERR(spdif->clk_sys))
  284. return dev_err_probe(dev, PTR_ERR(spdif->clk_sys),
  285. "Failed to acquire clock 'sys'\n");
  286. spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
  287. if (IS_ERR(spdif->clk_ref))
  288. return dev_err_probe(dev, PTR_ERR(spdif->clk_ref),
  289. "Failed to acquire clock 'ref'\n");
  290. pm_runtime_enable(&pdev->dev);
  291. if (!pm_runtime_enabled(&pdev->dev)) {
  292. ret = img_spdif_out_runtime_resume(&pdev->dev);
  293. if (ret)
  294. goto err_pm_disable;
  295. }
  296. ret = pm_runtime_resume_and_get(&pdev->dev);
  297. if (ret < 0)
  298. goto err_suspend;
  299. img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
  300. IMG_SPDIF_OUT_CTL);
  301. img_spdif_out_reset(spdif);
  302. pm_runtime_put(&pdev->dev);
  303. spin_lock_init(&spdif->lock);
  304. spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
  305. spdif->dma_data.addr_width = 4;
  306. spdif->dma_data.maxburst = 4;
  307. ret = devm_snd_soc_register_component(&pdev->dev,
  308. &img_spdif_out_component,
  309. &img_spdif_out_dai, 1);
  310. if (ret)
  311. goto err_suspend;
  312. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  313. if (ret)
  314. goto err_suspend;
  315. dev_dbg(&pdev->dev, "Probe successful\n");
  316. return 0;
  317. err_suspend:
  318. if (!pm_runtime_status_suspended(&pdev->dev))
  319. img_spdif_out_runtime_suspend(&pdev->dev);
  320. err_pm_disable:
  321. pm_runtime_disable(&pdev->dev);
  322. return ret;
  323. }
  324. static int img_spdif_out_dev_remove(struct platform_device *pdev)
  325. {
  326. pm_runtime_disable(&pdev->dev);
  327. if (!pm_runtime_status_suspended(&pdev->dev))
  328. img_spdif_out_runtime_suspend(&pdev->dev);
  329. return 0;
  330. }
  331. #ifdef CONFIG_PM_SLEEP
  332. static int img_spdif_out_suspend(struct device *dev)
  333. {
  334. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  335. int ret;
  336. if (pm_runtime_status_suspended(dev)) {
  337. ret = img_spdif_out_runtime_resume(dev);
  338. if (ret)
  339. return ret;
  340. }
  341. spdif->suspend_ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  342. spdif->suspend_csl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  343. spdif->suspend_csh = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  344. img_spdif_out_runtime_suspend(dev);
  345. return 0;
  346. }
  347. static int img_spdif_out_resume(struct device *dev)
  348. {
  349. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  350. int ret;
  351. ret = img_spdif_out_runtime_resume(dev);
  352. if (ret)
  353. return ret;
  354. img_spdif_out_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_OUT_CTL);
  355. img_spdif_out_writel(spdif, spdif->suspend_csl, IMG_SPDIF_OUT_CSL);
  356. img_spdif_out_writel(spdif, spdif->suspend_csh, IMG_SPDIF_OUT_CSH_UV);
  357. if (pm_runtime_status_suspended(dev))
  358. img_spdif_out_runtime_suspend(dev);
  359. return 0;
  360. }
  361. #endif
  362. static const struct of_device_id img_spdif_out_of_match[] = {
  363. { .compatible = "img,spdif-out" },
  364. {}
  365. };
  366. MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
  367. static const struct dev_pm_ops img_spdif_out_pm_ops = {
  368. SET_RUNTIME_PM_OPS(img_spdif_out_runtime_suspend,
  369. img_spdif_out_runtime_resume, NULL)
  370. SET_SYSTEM_SLEEP_PM_OPS(img_spdif_out_suspend, img_spdif_out_resume)
  371. };
  372. static struct platform_driver img_spdif_out_driver = {
  373. .driver = {
  374. .name = "img-spdif-out",
  375. .of_match_table = img_spdif_out_of_match,
  376. .pm = &img_spdif_out_pm_ops
  377. },
  378. .probe = img_spdif_out_probe,
  379. .remove = img_spdif_out_dev_remove
  380. };
  381. module_platform_driver(img_spdif_out_driver);
  382. MODULE_AUTHOR("Damien Horsley <[email protected]>");
  383. MODULE_DESCRIPTION("IMG SPDIF Output driver");
  384. MODULE_LICENSE("GPL v2");