fsl_xcvr.c 39 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright 2019 NXP
  3. #include <linux/bitrev.h>
  4. #include <linux/clk.h>
  5. #include <linux/firmware.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/module.h>
  8. #include <linux/of_platform.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/regmap.h>
  11. #include <linux/reset.h>
  12. #include <sound/dmaengine_pcm.h>
  13. #include <sound/pcm_iec958.h>
  14. #include <sound/pcm_params.h>
  15. #include "fsl_xcvr.h"
  16. #include "imx-pcm.h"
  17. #define FSL_XCVR_CAPDS_SIZE 256
  18. struct fsl_xcvr_soc_data {
  19. const char *fw_name;
  20. };
  21. struct fsl_xcvr {
  22. const struct fsl_xcvr_soc_data *soc_data;
  23. struct platform_device *pdev;
  24. struct regmap *regmap;
  25. struct clk *ipg_clk;
  26. struct clk *pll_ipg_clk;
  27. struct clk *phy_clk;
  28. struct clk *spba_clk;
  29. struct reset_control *reset;
  30. u8 streams;
  31. u32 mode;
  32. u32 arc_mode;
  33. void __iomem *ram_addr;
  34. struct snd_dmaengine_dai_dma_data dma_prms_rx;
  35. struct snd_dmaengine_dai_dma_data dma_prms_tx;
  36. struct snd_aes_iec958 rx_iec958;
  37. struct snd_aes_iec958 tx_iec958;
  38. u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
  39. };
  40. static const struct fsl_xcvr_pll_conf {
  41. u8 mfi; /* min=0x18, max=0x38 */
  42. u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
  43. u32 mfd; /* unsigned int */
  44. u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
  45. } fsl_xcvr_pll_cfg[] = {
  46. { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */
  47. { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */
  48. { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */
  49. { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */
  50. };
  51. /*
  52. * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
  53. * stream. Todo: to check how this case can be considered below
  54. */
  55. static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
  56. static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
  57. .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
  58. .list = fsl_xcvr_earc_channels,
  59. };
  60. static const u32 fsl_xcvr_earc_rates[] = {
  61. 32000, 44100, 48000, 64000, 88200, 96000,
  62. 128000, 176400, 192000, 256000, 352800, 384000,
  63. 512000, 705600, 768000, 1024000, 1411200, 1536000,
  64. };
  65. static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
  66. .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
  67. .list = fsl_xcvr_earc_rates,
  68. };
  69. static const u32 fsl_xcvr_spdif_channels[] = { 2, };
  70. static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
  71. .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
  72. .list = fsl_xcvr_spdif_channels,
  73. };
  74. static const u32 fsl_xcvr_spdif_rates[] = {
  75. 32000, 44100, 48000, 88200, 96000, 176400, 192000,
  76. };
  77. static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
  78. .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
  79. .list = fsl_xcvr_spdif_rates,
  80. };
  81. static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
  82. struct snd_ctl_elem_value *ucontrol)
  83. {
  84. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  85. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  86. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  87. unsigned int *item = ucontrol->value.enumerated.item;
  88. xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
  89. return 0;
  90. }
  91. static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
  92. struct snd_ctl_elem_value *ucontrol)
  93. {
  94. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  95. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  96. ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
  97. return 0;
  98. }
  99. static const u32 fsl_xcvr_phy_arc_cfg[] = {
  100. FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
  101. };
  102. static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
  103. static const struct soc_enum fsl_xcvr_arc_mode_enum =
  104. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
  105. static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
  106. SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
  107. fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
  108. /* Capabilities data structure, bytes */
  109. static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
  110. struct snd_ctl_elem_info *uinfo)
  111. {
  112. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  113. uinfo->count = FSL_XCVR_CAPDS_SIZE;
  114. return 0;
  115. }
  116. static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
  117. struct snd_ctl_elem_value *ucontrol)
  118. {
  119. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  120. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  121. memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
  122. return 0;
  123. }
  124. static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
  125. struct snd_ctl_elem_value *ucontrol)
  126. {
  127. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  128. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  129. memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
  130. return 0;
  131. }
  132. static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
  133. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  134. .name = "Capabilities Data Structure",
  135. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  136. .info = fsl_xcvr_type_capds_bytes_info,
  137. .get = fsl_xcvr_capds_get,
  138. .put = fsl_xcvr_capds_put,
  139. };
  140. static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
  141. bool active)
  142. {
  143. struct snd_soc_card *card = dai->component->card;
  144. struct snd_kcontrol *kctl;
  145. bool enabled;
  146. kctl = snd_soc_card_get_kcontrol(card, name);
  147. if (kctl == NULL)
  148. return -ENOENT;
  149. enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
  150. if (active == enabled)
  151. return 0; /* nothing to do */
  152. if (active)
  153. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
  154. else
  155. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
  156. snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  157. return 1;
  158. }
  159. static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
  160. struct snd_ctl_elem_value *ucontrol)
  161. {
  162. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  163. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  164. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  165. unsigned int *item = ucontrol->value.enumerated.item;
  166. struct snd_soc_card *card = dai->component->card;
  167. struct snd_soc_pcm_runtime *rtd;
  168. xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
  169. fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
  170. (xcvr->mode == FSL_XCVR_MODE_ARC));
  171. fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
  172. (xcvr->mode == FSL_XCVR_MODE_EARC));
  173. /* Allow playback for SPDIF only */
  174. rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
  175. rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
  176. (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
  177. return 0;
  178. }
  179. static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
  180. struct snd_ctl_elem_value *ucontrol)
  181. {
  182. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  183. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  184. ucontrol->value.enumerated.item[0] = xcvr->mode;
  185. return 0;
  186. }
  187. static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
  188. static const struct soc_enum fsl_xcvr_mode_enum =
  189. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
  190. static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
  191. SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
  192. fsl_xcvr_mode_get, fsl_xcvr_mode_put);
  193. /** phy: true => phy, false => pll */
  194. static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
  195. {
  196. struct device *dev = &xcvr->pdev->dev;
  197. u32 val, idx, tidx;
  198. int ret;
  199. idx = BIT(phy ? 26 : 24);
  200. tidx = BIT(phy ? 27 : 25);
  201. regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
  202. regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
  203. regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
  204. regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
  205. ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
  206. (val & idx) == ((val & tidx) >> 1),
  207. 10, 10000);
  208. if (ret)
  209. dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
  210. phy ? "PHY" : "PLL", reg, data);
  211. return ret;
  212. }
  213. static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
  214. {
  215. struct device *dev = &xcvr->pdev->dev;
  216. u32 i, div = 0, log2;
  217. int ret;
  218. for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
  219. if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
  220. div = fsl_xcvr_pll_cfg[i].fout / freq;
  221. break;
  222. }
  223. }
  224. if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
  225. return -EINVAL;
  226. log2 = ilog2(div);
  227. /* Release AI interface from reset */
  228. ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
  229. FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
  230. if (ret < 0) {
  231. dev_err(dev, "Error while setting IER0: %d\n", ret);
  232. return ret;
  233. }
  234. /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
  235. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
  236. FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
  237. /* PLL: CTRL0: DIV_INTEGER */
  238. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
  239. /* PLL: NUMERATOR: MFN */
  240. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
  241. /* PLL: DENOMINATOR: MFD */
  242. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
  243. /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
  244. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
  245. FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
  246. udelay(25);
  247. /* PLL: CTRL0: Clear Hold Ring Off */
  248. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
  249. FSL_XCVR_PLL_CTRL0_HROFF, 0);
  250. udelay(100);
  251. if (tx) { /* TX is enabled for SPDIF only */
  252. /* PLL: POSTDIV: PDIV0 */
  253. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
  254. FSL_XCVR_PLL_PDIVx(log2, 0), 0);
  255. /* PLL: CTRL_SET: CLKMUX0_EN */
  256. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
  257. FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
  258. } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
  259. /* PLL: POSTDIV: PDIV1 */
  260. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
  261. FSL_XCVR_PLL_PDIVx(log2, 1), 0);
  262. /* PLL: CTRL_SET: CLKMUX1_EN */
  263. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
  264. FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
  265. } else { /* SPDIF / ARC RX */
  266. /* PLL: POSTDIV: PDIV2 */
  267. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
  268. FSL_XCVR_PLL_PDIVx(log2, 2), 0);
  269. /* PLL: CTRL_SET: CLKMUX2_EN */
  270. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
  271. FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
  272. }
  273. if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
  274. /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
  275. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
  276. FSL_XCVR_PHY_CTRL_TSDIFF_OE |
  277. FSL_XCVR_PHY_CTRL_PHY_EN, 1);
  278. /* PHY: CTRL2_SET: EARC_TX_MODE */
  279. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
  280. FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
  281. } else if (!tx) { /* SPDIF / ARC RX mode */
  282. if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
  283. /* PHY: CTRL_SET: SPDIF_EN */
  284. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
  285. FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
  286. else /* PHY: CTRL_SET: ARC RX setup */
  287. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
  288. FSL_XCVR_PHY_CTRL_PHY_EN |
  289. FSL_XCVR_PHY_CTRL_RX_CM_EN |
  290. fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
  291. }
  292. dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
  293. freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
  294. fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
  295. return 0;
  296. }
  297. static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
  298. {
  299. struct device *dev = &xcvr->pdev->dev;
  300. int ret;
  301. clk_disable_unprepare(xcvr->phy_clk);
  302. ret = clk_set_rate(xcvr->phy_clk, freq);
  303. if (ret < 0) {
  304. dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
  305. return ret;
  306. }
  307. ret = clk_prepare_enable(xcvr->phy_clk);
  308. if (ret) {
  309. dev_err(dev, "failed to start PHY clock: %d\n", ret);
  310. return ret;
  311. }
  312. /* Release AI interface from reset */
  313. ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
  314. FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
  315. if (ret < 0) {
  316. dev_err(dev, "Error while setting IER0: %d\n", ret);
  317. return ret;
  318. }
  319. if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
  320. /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
  321. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
  322. FSL_XCVR_PHY_CTRL_TSDIFF_OE |
  323. FSL_XCVR_PHY_CTRL_PHY_EN, 1);
  324. /* PHY: CTRL2_SET: EARC_TX_MODE */
  325. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
  326. FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
  327. } else { /* SPDIF mode */
  328. /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
  329. fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
  330. FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
  331. FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
  332. }
  333. dev_dbg(dev, "PLL Fexp: %u\n", freq);
  334. return 0;
  335. }
  336. #define FSL_XCVR_SPDIF_RX_FREQ 175000000
  337. static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
  338. struct snd_soc_dai *dai)
  339. {
  340. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  341. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  342. u32 m_ctl = 0, v_ctl = 0;
  343. u32 r = substream->runtime->rate, ch = substream->runtime->channels;
  344. u32 fout = 32 * r * ch * 10 * 2;
  345. int ret = 0;
  346. switch (xcvr->mode) {
  347. case FSL_XCVR_MODE_SPDIF:
  348. case FSL_XCVR_MODE_ARC:
  349. if (tx) {
  350. ret = fsl_xcvr_en_aud_pll(xcvr, fout);
  351. if (ret < 0) {
  352. dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
  353. fout, ret);
  354. return ret;
  355. }
  356. ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
  357. FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
  358. if (ret < 0) {
  359. dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
  360. return ret;
  361. }
  362. /**
  363. * set SPDIF MODE - this flag is used to gate
  364. * SPDIF output, useless for SPDIF RX
  365. */
  366. m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
  367. v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
  368. } else {
  369. /**
  370. * Clear RX FIFO, flip RX FIFO bits,
  371. * disable eARC related HW mode detects
  372. */
  373. ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
  374. FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
  375. FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
  376. FSL_XCVR_RX_DPTH_CTRL_COMP |
  377. FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
  378. if (ret < 0) {
  379. dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
  380. return ret;
  381. }
  382. ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
  383. if (ret < 0) {
  384. dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
  385. FSL_XCVR_SPDIF_RX_FREQ, ret);
  386. return ret;
  387. }
  388. }
  389. break;
  390. case FSL_XCVR_MODE_EARC:
  391. if (!tx) {
  392. /** Clear RX FIFO, flip RX FIFO bits */
  393. ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
  394. FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
  395. FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
  396. if (ret < 0) {
  397. dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
  398. return ret;
  399. }
  400. /** Enable eARC related HW mode detects */
  401. ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
  402. FSL_XCVR_RX_DPTH_CTRL_COMP |
  403. FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
  404. if (ret < 0) {
  405. dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
  406. return ret;
  407. }
  408. }
  409. /* clear CMDC RESET */
  410. m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
  411. /* set TX_RX_MODE */
  412. m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
  413. v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
  414. break;
  415. }
  416. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
  417. FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
  418. if (ret < 0) {
  419. dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
  420. return ret;
  421. }
  422. /* set DPATH RESET */
  423. m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
  424. v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
  425. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
  426. if (ret < 0) {
  427. dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
  428. return ret;
  429. }
  430. return 0;
  431. }
  432. static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
  433. const struct snd_pcm_hw_constraint_list *channels,
  434. const struct snd_pcm_hw_constraint_list *rates)
  435. {
  436. struct snd_pcm_runtime *rt = substream->runtime;
  437. int ret;
  438. ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  439. channels);
  440. if (ret < 0)
  441. return ret;
  442. ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
  443. rates);
  444. if (ret < 0)
  445. return ret;
  446. return 0;
  447. }
  448. static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
  449. struct snd_soc_dai *dai)
  450. {
  451. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  452. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  453. int ret = 0;
  454. if (xcvr->streams & BIT(substream->stream)) {
  455. dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
  456. return -EBUSY;
  457. }
  458. switch (xcvr->mode) {
  459. case FSL_XCVR_MODE_SPDIF:
  460. case FSL_XCVR_MODE_ARC:
  461. ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
  462. &fsl_xcvr_spdif_rates_constr);
  463. break;
  464. case FSL_XCVR_MODE_EARC:
  465. ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
  466. &fsl_xcvr_earc_rates_constr);
  467. break;
  468. }
  469. if (ret < 0)
  470. return ret;
  471. xcvr->streams |= BIT(substream->stream);
  472. /* Disable XCVR controls if there is stream started */
  473. fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
  474. fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
  475. fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
  476. return 0;
  477. }
  478. static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
  479. struct snd_soc_dai *dai)
  480. {
  481. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  482. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  483. u32 mask = 0, val = 0;
  484. int ret;
  485. xcvr->streams &= ~BIT(substream->stream);
  486. /* Enable XCVR controls if there is no stream started */
  487. if (!xcvr->streams) {
  488. fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
  489. fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
  490. (xcvr->mode == FSL_XCVR_MODE_ARC));
  491. fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
  492. (xcvr->mode == FSL_XCVR_MODE_EARC));
  493. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
  494. FSL_XCVR_IRQ_EARC_ALL, 0);
  495. if (ret < 0) {
  496. dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
  497. return;
  498. }
  499. /* clear SPDIF MODE */
  500. if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
  501. mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
  502. }
  503. if (xcvr->mode == FSL_XCVR_MODE_EARC) {
  504. /* set CMDC RESET */
  505. mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
  506. val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
  507. }
  508. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
  509. if (ret < 0) {
  510. dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
  511. return;
  512. }
  513. }
  514. static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
  515. struct snd_soc_dai *dai)
  516. {
  517. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  518. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  519. int ret;
  520. switch (cmd) {
  521. case SNDRV_PCM_TRIGGER_START:
  522. case SNDRV_PCM_TRIGGER_RESUME:
  523. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  524. if (tx) {
  525. switch (xcvr->mode) {
  526. case FSL_XCVR_MODE_EARC:
  527. /* set isr_cmdc_tx_en, w1c */
  528. ret = regmap_write(xcvr->regmap,
  529. FSL_XCVR_ISR_SET,
  530. FSL_XCVR_ISR_CMDC_TX_EN);
  531. if (ret < 0) {
  532. dev_err(dai->dev, "err updating isr %d\n", ret);
  533. return ret;
  534. }
  535. fallthrough;
  536. case FSL_XCVR_MODE_SPDIF:
  537. ret = regmap_write(xcvr->regmap,
  538. FSL_XCVR_TX_DPTH_CTRL_SET,
  539. FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
  540. if (ret < 0) {
  541. dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
  542. return ret;
  543. }
  544. break;
  545. }
  546. }
  547. /* enable DMA RD/WR */
  548. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  549. FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
  550. if (ret < 0) {
  551. dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
  552. return ret;
  553. }
  554. /* clear DPATH RESET */
  555. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  556. FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
  557. 0);
  558. if (ret < 0) {
  559. dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
  560. return ret;
  561. }
  562. break;
  563. case SNDRV_PCM_TRIGGER_STOP:
  564. case SNDRV_PCM_TRIGGER_SUSPEND:
  565. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  566. /* disable DMA RD/WR */
  567. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  568. FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
  569. FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
  570. if (ret < 0) {
  571. dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
  572. return ret;
  573. }
  574. if (tx) {
  575. switch (xcvr->mode) {
  576. case FSL_XCVR_MODE_SPDIF:
  577. ret = regmap_write(xcvr->regmap,
  578. FSL_XCVR_TX_DPTH_CTRL_CLR,
  579. FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
  580. if (ret < 0) {
  581. dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
  582. return ret;
  583. }
  584. fallthrough;
  585. case FSL_XCVR_MODE_EARC:
  586. /* clear ISR_CMDC_TX_EN, W1C */
  587. ret = regmap_write(xcvr->regmap,
  588. FSL_XCVR_ISR_CLR,
  589. FSL_XCVR_ISR_CMDC_TX_EN);
  590. if (ret < 0) {
  591. dev_err(dai->dev,
  592. "Err updating ISR %d\n", ret);
  593. return ret;
  594. }
  595. break;
  596. }
  597. }
  598. break;
  599. default:
  600. return -EINVAL;
  601. }
  602. return 0;
  603. }
  604. static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
  605. {
  606. struct device *dev = &xcvr->pdev->dev;
  607. const struct firmware *fw;
  608. int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
  609. u32 mask, val;
  610. ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
  611. if (ret) {
  612. dev_err(dev, "failed to request firmware.\n");
  613. return ret;
  614. }
  615. rem = fw->size;
  616. /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
  617. if (rem > 16384) {
  618. dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
  619. release_firmware(fw);
  620. return -ENOMEM;
  621. }
  622. for (page = 0; page < 10; page++) {
  623. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  624. FSL_XCVR_EXT_CTRL_PAGE_MASK,
  625. FSL_XCVR_EXT_CTRL_PAGE(page));
  626. if (ret < 0) {
  627. dev_err(dev, "FW: failed to set page %d, err=%d\n",
  628. page, ret);
  629. goto err_firmware;
  630. }
  631. off = page * size;
  632. out = min(rem, size);
  633. /* IPG clock is assumed to be running, otherwise it will hang */
  634. if (out > 0) {
  635. /* write firmware into code memory */
  636. memcpy_toio(xcvr->ram_addr, fw->data + off, out);
  637. rem -= out;
  638. if (rem == 0) {
  639. /* last part of firmware written */
  640. /* clean remaining part of code memory page */
  641. memset_io(xcvr->ram_addr + out, 0, size - out);
  642. }
  643. } else {
  644. /* clean current page, including data memory */
  645. memset_io(xcvr->ram_addr, 0, size);
  646. }
  647. }
  648. err_firmware:
  649. release_firmware(fw);
  650. if (ret < 0)
  651. return ret;
  652. /* configure watermarks */
  653. mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
  654. val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
  655. val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
  656. /* disable DMA RD/WR */
  657. mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
  658. val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
  659. /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
  660. mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
  661. val |= FSL_XCVR_EXT_CTRL_PAGE(8);
  662. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
  663. if (ret < 0) {
  664. dev_err(dev, "Failed to set watermarks: %d\n", ret);
  665. return ret;
  666. }
  667. /* Store Capabilities Data Structure into Data RAM */
  668. memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
  669. FSL_XCVR_CAPDS_SIZE);
  670. return 0;
  671. }
  672. static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
  673. struct snd_ctl_elem_info *uinfo)
  674. {
  675. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  676. uinfo->count = 1;
  677. return 0;
  678. }
  679. static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
  680. struct snd_ctl_elem_info *uinfo)
  681. {
  682. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  683. uinfo->count = sizeof_field(struct snd_aes_iec958, status);
  684. return 0;
  685. }
  686. static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
  687. struct snd_ctl_elem_value *ucontrol)
  688. {
  689. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  690. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  691. memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
  692. return 0;
  693. }
  694. static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
  695. struct snd_ctl_elem_value *ucontrol)
  696. {
  697. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  698. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  699. memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
  700. return 0;
  701. }
  702. static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
  703. struct snd_ctl_elem_value *ucontrol)
  704. {
  705. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  706. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  707. memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
  708. return 0;
  709. }
  710. static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
  711. /* Channel status controller */
  712. {
  713. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  714. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
  715. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  716. .info = fsl_xcvr_type_iec958_info,
  717. .get = fsl_xcvr_rx_cs_get,
  718. },
  719. /* Capture channel status, bytes */
  720. {
  721. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  722. .name = "Capture Channel Status",
  723. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  724. .info = fsl_xcvr_type_iec958_bytes_info,
  725. .get = fsl_xcvr_rx_cs_get,
  726. },
  727. };
  728. static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
  729. /* Channel status controller */
  730. {
  731. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  732. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  733. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  734. .info = fsl_xcvr_type_iec958_info,
  735. .get = fsl_xcvr_tx_cs_get,
  736. .put = fsl_xcvr_tx_cs_put,
  737. },
  738. /* Playback channel status, bytes */
  739. {
  740. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  741. .name = "Playback Channel Status",
  742. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  743. .info = fsl_xcvr_type_iec958_bytes_info,
  744. .get = fsl_xcvr_tx_cs_get,
  745. .put = fsl_xcvr_tx_cs_put,
  746. },
  747. };
  748. static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
  749. .prepare = fsl_xcvr_prepare,
  750. .startup = fsl_xcvr_startup,
  751. .shutdown = fsl_xcvr_shutdown,
  752. .trigger = fsl_xcvr_trigger,
  753. };
  754. static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
  755. {
  756. struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
  757. snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
  758. snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
  759. snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
  760. snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
  761. snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
  762. ARRAY_SIZE(fsl_xcvr_tx_ctls));
  763. snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
  764. ARRAY_SIZE(fsl_xcvr_rx_ctls));
  765. return 0;
  766. }
  767. static struct snd_soc_dai_driver fsl_xcvr_dai = {
  768. .probe = fsl_xcvr_dai_probe,
  769. .ops = &fsl_xcvr_dai_ops,
  770. .playback = {
  771. .stream_name = "CPU-Playback",
  772. .channels_min = 1,
  773. .channels_max = 32,
  774. .rate_min = 32000,
  775. .rate_max = 1536000,
  776. .rates = SNDRV_PCM_RATE_KNOT,
  777. .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
  778. },
  779. .capture = {
  780. .stream_name = "CPU-Capture",
  781. .channels_min = 1,
  782. .channels_max = 32,
  783. .rate_min = 32000,
  784. .rate_max = 1536000,
  785. .rates = SNDRV_PCM_RATE_KNOT,
  786. .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
  787. },
  788. };
  789. static const struct snd_soc_component_driver fsl_xcvr_comp = {
  790. .name = "fsl-xcvr-dai",
  791. .legacy_dai_naming = 1,
  792. };
  793. static const struct reg_default fsl_xcvr_reg_defaults[] = {
  794. { FSL_XCVR_VERSION, 0x00000000 },
  795. { FSL_XCVR_EXT_CTRL, 0xF8204040 },
  796. { FSL_XCVR_EXT_STATUS, 0x00000000 },
  797. { FSL_XCVR_EXT_IER0, 0x00000000 },
  798. { FSL_XCVR_EXT_IER1, 0x00000000 },
  799. { FSL_XCVR_EXT_ISR, 0x00000000 },
  800. { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
  801. { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
  802. { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
  803. { FSL_XCVR_IER, 0x00000000 },
  804. { FSL_XCVR_ISR, 0x00000000 },
  805. { FSL_XCVR_ISR_SET, 0x00000000 },
  806. { FSL_XCVR_ISR_CLR, 0x00000000 },
  807. { FSL_XCVR_ISR_TOG, 0x00000000 },
  808. { FSL_XCVR_RX_DPTH_CTRL, 0x00002C89 },
  809. { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 },
  810. { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 },
  811. { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 },
  812. { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
  813. { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
  814. { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
  815. { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
  816. { FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
  817. { FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
  818. { FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
  819. { FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
  820. { FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
  821. { FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
  822. { FSL_XCVR_DEBUG_REG_0, 0x00000000 },
  823. { FSL_XCVR_DEBUG_REG_1, 0x00000000 },
  824. };
  825. static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
  826. {
  827. switch (reg) {
  828. case FSL_XCVR_VERSION:
  829. case FSL_XCVR_EXT_CTRL:
  830. case FSL_XCVR_EXT_STATUS:
  831. case FSL_XCVR_EXT_IER0:
  832. case FSL_XCVR_EXT_IER1:
  833. case FSL_XCVR_EXT_ISR:
  834. case FSL_XCVR_EXT_ISR_SET:
  835. case FSL_XCVR_EXT_ISR_CLR:
  836. case FSL_XCVR_EXT_ISR_TOG:
  837. case FSL_XCVR_IER:
  838. case FSL_XCVR_ISR:
  839. case FSL_XCVR_ISR_SET:
  840. case FSL_XCVR_ISR_CLR:
  841. case FSL_XCVR_ISR_TOG:
  842. case FSL_XCVR_PHY_AI_CTRL:
  843. case FSL_XCVR_PHY_AI_CTRL_SET:
  844. case FSL_XCVR_PHY_AI_CTRL_CLR:
  845. case FSL_XCVR_PHY_AI_CTRL_TOG:
  846. case FSL_XCVR_PHY_AI_RDATA:
  847. case FSL_XCVR_CLK_CTRL:
  848. case FSL_XCVR_RX_DPTH_CTRL:
  849. case FSL_XCVR_RX_DPTH_CTRL_SET:
  850. case FSL_XCVR_RX_DPTH_CTRL_CLR:
  851. case FSL_XCVR_RX_DPTH_CTRL_TOG:
  852. case FSL_XCVR_TX_DPTH_CTRL:
  853. case FSL_XCVR_TX_DPTH_CTRL_SET:
  854. case FSL_XCVR_TX_DPTH_CTRL_CLR:
  855. case FSL_XCVR_TX_DPTH_CTRL_TOG:
  856. case FSL_XCVR_TX_CS_DATA_0:
  857. case FSL_XCVR_TX_CS_DATA_1:
  858. case FSL_XCVR_TX_CS_DATA_2:
  859. case FSL_XCVR_TX_CS_DATA_3:
  860. case FSL_XCVR_TX_CS_DATA_4:
  861. case FSL_XCVR_TX_CS_DATA_5:
  862. case FSL_XCVR_DEBUG_REG_0:
  863. case FSL_XCVR_DEBUG_REG_1:
  864. return true;
  865. default:
  866. return false;
  867. }
  868. }
  869. static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
  870. {
  871. switch (reg) {
  872. case FSL_XCVR_EXT_CTRL:
  873. case FSL_XCVR_EXT_IER0:
  874. case FSL_XCVR_EXT_IER1:
  875. case FSL_XCVR_EXT_ISR:
  876. case FSL_XCVR_EXT_ISR_SET:
  877. case FSL_XCVR_EXT_ISR_CLR:
  878. case FSL_XCVR_EXT_ISR_TOG:
  879. case FSL_XCVR_IER:
  880. case FSL_XCVR_ISR_SET:
  881. case FSL_XCVR_ISR_CLR:
  882. case FSL_XCVR_ISR_TOG:
  883. case FSL_XCVR_PHY_AI_CTRL:
  884. case FSL_XCVR_PHY_AI_CTRL_SET:
  885. case FSL_XCVR_PHY_AI_CTRL_CLR:
  886. case FSL_XCVR_PHY_AI_CTRL_TOG:
  887. case FSL_XCVR_PHY_AI_WDATA:
  888. case FSL_XCVR_CLK_CTRL:
  889. case FSL_XCVR_RX_DPTH_CTRL:
  890. case FSL_XCVR_RX_DPTH_CTRL_SET:
  891. case FSL_XCVR_RX_DPTH_CTRL_CLR:
  892. case FSL_XCVR_RX_DPTH_CTRL_TOG:
  893. case FSL_XCVR_TX_DPTH_CTRL_SET:
  894. case FSL_XCVR_TX_DPTH_CTRL_CLR:
  895. case FSL_XCVR_TX_DPTH_CTRL_TOG:
  896. case FSL_XCVR_TX_CS_DATA_0:
  897. case FSL_XCVR_TX_CS_DATA_1:
  898. case FSL_XCVR_TX_CS_DATA_2:
  899. case FSL_XCVR_TX_CS_DATA_3:
  900. case FSL_XCVR_TX_CS_DATA_4:
  901. case FSL_XCVR_TX_CS_DATA_5:
  902. return true;
  903. default:
  904. return false;
  905. }
  906. }
  907. static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
  908. {
  909. return fsl_xcvr_readable_reg(dev, reg);
  910. }
  911. static const struct regmap_config fsl_xcvr_regmap_cfg = {
  912. .reg_bits = 32,
  913. .reg_stride = 4,
  914. .val_bits = 32,
  915. .max_register = FSL_XCVR_MAX_REG,
  916. .reg_defaults = fsl_xcvr_reg_defaults,
  917. .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
  918. .readable_reg = fsl_xcvr_readable_reg,
  919. .volatile_reg = fsl_xcvr_volatile_reg,
  920. .writeable_reg = fsl_xcvr_writeable_reg,
  921. .cache_type = REGCACHE_FLAT,
  922. };
  923. static irqreturn_t irq0_isr(int irq, void *devid)
  924. {
  925. struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
  926. struct device *dev = &xcvr->pdev->dev;
  927. struct regmap *regmap = xcvr->regmap;
  928. void __iomem *reg_ctrl, *reg_buff;
  929. u32 isr, isr_clr = 0, val, i;
  930. regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
  931. if (isr & FSL_XCVR_IRQ_NEW_CS) {
  932. dev_dbg(dev, "Received new CS block\n");
  933. isr_clr |= FSL_XCVR_IRQ_NEW_CS;
  934. /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
  935. regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  936. FSL_XCVR_EXT_CTRL_PAGE_MASK,
  937. FSL_XCVR_EXT_CTRL_PAGE(8));
  938. /* Find updated CS buffer */
  939. reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
  940. reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
  941. memcpy_fromio(&val, reg_ctrl, sizeof(val));
  942. if (!val) {
  943. reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
  944. reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
  945. memcpy_fromio(&val, reg_ctrl, sizeof(val));
  946. }
  947. if (val) {
  948. /* copy CS buffer */
  949. memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
  950. sizeof(xcvr->rx_iec958.status));
  951. for (i = 0; i < 6; i++) {
  952. val = *(u32 *)(xcvr->rx_iec958.status + i*4);
  953. *(u32 *)(xcvr->rx_iec958.status + i*4) =
  954. bitrev32(val);
  955. }
  956. /* clear CS control register */
  957. memset_io(reg_ctrl, 0, sizeof(val));
  958. }
  959. }
  960. if (isr & FSL_XCVR_IRQ_NEW_UD) {
  961. dev_dbg(dev, "Received new UD block\n");
  962. isr_clr |= FSL_XCVR_IRQ_NEW_UD;
  963. }
  964. if (isr & FSL_XCVR_IRQ_MUTE) {
  965. dev_dbg(dev, "HW mute bit detected\n");
  966. isr_clr |= FSL_XCVR_IRQ_MUTE;
  967. }
  968. if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
  969. dev_dbg(dev, "RX/TX FIFO full/empty\n");
  970. isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
  971. }
  972. if (isr & FSL_XCVR_IRQ_ARC_MODE) {
  973. dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
  974. isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
  975. }
  976. if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
  977. dev_dbg(dev, "DMA read request\n");
  978. isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
  979. }
  980. if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
  981. dev_dbg(dev, "DMA write request\n");
  982. isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
  983. }
  984. if (isr_clr) {
  985. regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
  986. return IRQ_HANDLED;
  987. }
  988. return IRQ_NONE;
  989. }
  990. static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
  991. .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
  992. };
  993. static const struct of_device_id fsl_xcvr_dt_ids[] = {
  994. { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
  995. { /* sentinel */ }
  996. };
  997. MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
  998. static int fsl_xcvr_probe(struct platform_device *pdev)
  999. {
  1000. struct device *dev = &pdev->dev;
  1001. struct fsl_xcvr *xcvr;
  1002. struct resource *rx_res, *tx_res;
  1003. void __iomem *regs;
  1004. int ret, irq;
  1005. xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
  1006. if (!xcvr)
  1007. return -ENOMEM;
  1008. xcvr->pdev = pdev;
  1009. xcvr->soc_data = of_device_get_match_data(&pdev->dev);
  1010. xcvr->ipg_clk = devm_clk_get(dev, "ipg");
  1011. if (IS_ERR(xcvr->ipg_clk)) {
  1012. dev_err(dev, "failed to get ipg clock\n");
  1013. return PTR_ERR(xcvr->ipg_clk);
  1014. }
  1015. xcvr->phy_clk = devm_clk_get(dev, "phy");
  1016. if (IS_ERR(xcvr->phy_clk)) {
  1017. dev_err(dev, "failed to get phy clock\n");
  1018. return PTR_ERR(xcvr->phy_clk);
  1019. }
  1020. xcvr->spba_clk = devm_clk_get(dev, "spba");
  1021. if (IS_ERR(xcvr->spba_clk)) {
  1022. dev_err(dev, "failed to get spba clock\n");
  1023. return PTR_ERR(xcvr->spba_clk);
  1024. }
  1025. xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
  1026. if (IS_ERR(xcvr->pll_ipg_clk)) {
  1027. dev_err(dev, "failed to get pll_ipg clock\n");
  1028. return PTR_ERR(xcvr->pll_ipg_clk);
  1029. }
  1030. xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
  1031. if (IS_ERR(xcvr->ram_addr))
  1032. return PTR_ERR(xcvr->ram_addr);
  1033. regs = devm_platform_ioremap_resource_byname(pdev, "regs");
  1034. if (IS_ERR(regs))
  1035. return PTR_ERR(regs);
  1036. xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
  1037. &fsl_xcvr_regmap_cfg);
  1038. if (IS_ERR(xcvr->regmap)) {
  1039. dev_err(dev, "failed to init XCVR regmap: %ld\n",
  1040. PTR_ERR(xcvr->regmap));
  1041. return PTR_ERR(xcvr->regmap);
  1042. }
  1043. xcvr->reset = devm_reset_control_get_exclusive(dev, NULL);
  1044. if (IS_ERR(xcvr->reset)) {
  1045. dev_err(dev, "failed to get XCVR reset control\n");
  1046. return PTR_ERR(xcvr->reset);
  1047. }
  1048. /* get IRQs */
  1049. irq = platform_get_irq(pdev, 0);
  1050. if (irq < 0)
  1051. return irq;
  1052. ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
  1053. if (ret) {
  1054. dev_err(dev, "failed to claim IRQ0: %i\n", ret);
  1055. return ret;
  1056. }
  1057. rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
  1058. tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
  1059. if (!rx_res || !tx_res) {
  1060. dev_err(dev, "could not find rxfifo or txfifo resource\n");
  1061. return -EINVAL;
  1062. }
  1063. xcvr->dma_prms_rx.chan_name = "rx";
  1064. xcvr->dma_prms_tx.chan_name = "tx";
  1065. xcvr->dma_prms_rx.addr = rx_res->start;
  1066. xcvr->dma_prms_tx.addr = tx_res->start;
  1067. xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
  1068. xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
  1069. platform_set_drvdata(pdev, xcvr);
  1070. pm_runtime_enable(dev);
  1071. regcache_cache_only(xcvr->regmap, true);
  1072. /*
  1073. * Register platform component before registering cpu dai for there
  1074. * is not defer probe for platform component in snd_soc_add_pcm_runtime().
  1075. */
  1076. ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
  1077. if (ret) {
  1078. pm_runtime_disable(dev);
  1079. dev_err(dev, "failed to pcm register\n");
  1080. return ret;
  1081. }
  1082. ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
  1083. &fsl_xcvr_dai, 1);
  1084. if (ret) {
  1085. pm_runtime_disable(dev);
  1086. dev_err(dev, "failed to register component %s\n",
  1087. fsl_xcvr_comp.name);
  1088. }
  1089. return ret;
  1090. }
  1091. static int fsl_xcvr_remove(struct platform_device *pdev)
  1092. {
  1093. pm_runtime_disable(&pdev->dev);
  1094. return 0;
  1095. }
  1096. static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
  1097. {
  1098. struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
  1099. int ret;
  1100. /*
  1101. * Clear interrupts, when streams starts or resumes after
  1102. * suspend, interrupts are enabled in prepare(), so no need
  1103. * to enable interrupts in resume().
  1104. */
  1105. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
  1106. FSL_XCVR_IRQ_EARC_ALL, 0);
  1107. if (ret < 0)
  1108. dev_err(dev, "Failed to clear IER0: %d\n", ret);
  1109. /* Assert M0+ reset */
  1110. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  1111. FSL_XCVR_EXT_CTRL_CORE_RESET,
  1112. FSL_XCVR_EXT_CTRL_CORE_RESET);
  1113. if (ret < 0)
  1114. dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
  1115. regcache_cache_only(xcvr->regmap, true);
  1116. clk_disable_unprepare(xcvr->spba_clk);
  1117. clk_disable_unprepare(xcvr->phy_clk);
  1118. clk_disable_unprepare(xcvr->pll_ipg_clk);
  1119. clk_disable_unprepare(xcvr->ipg_clk);
  1120. return 0;
  1121. }
  1122. static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
  1123. {
  1124. struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
  1125. int ret;
  1126. ret = reset_control_assert(xcvr->reset);
  1127. if (ret < 0) {
  1128. dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
  1129. return ret;
  1130. }
  1131. ret = clk_prepare_enable(xcvr->ipg_clk);
  1132. if (ret) {
  1133. dev_err(dev, "failed to start IPG clock.\n");
  1134. return ret;
  1135. }
  1136. ret = clk_prepare_enable(xcvr->pll_ipg_clk);
  1137. if (ret) {
  1138. dev_err(dev, "failed to start PLL IPG clock.\n");
  1139. goto stop_ipg_clk;
  1140. }
  1141. ret = clk_prepare_enable(xcvr->phy_clk);
  1142. if (ret) {
  1143. dev_err(dev, "failed to start PHY clock: %d\n", ret);
  1144. goto stop_pll_ipg_clk;
  1145. }
  1146. ret = clk_prepare_enable(xcvr->spba_clk);
  1147. if (ret) {
  1148. dev_err(dev, "failed to start SPBA clock.\n");
  1149. goto stop_phy_clk;
  1150. }
  1151. regcache_cache_only(xcvr->regmap, false);
  1152. regcache_mark_dirty(xcvr->regmap);
  1153. ret = regcache_sync(xcvr->regmap);
  1154. if (ret) {
  1155. dev_err(dev, "failed to sync regcache.\n");
  1156. goto stop_spba_clk;
  1157. }
  1158. ret = reset_control_deassert(xcvr->reset);
  1159. if (ret) {
  1160. dev_err(dev, "failed to deassert M0+ reset.\n");
  1161. goto stop_spba_clk;
  1162. }
  1163. ret = fsl_xcvr_load_firmware(xcvr);
  1164. if (ret) {
  1165. dev_err(dev, "failed to load firmware.\n");
  1166. goto stop_spba_clk;
  1167. }
  1168. /* Release M0+ reset */
  1169. ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
  1170. FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
  1171. if (ret < 0) {
  1172. dev_err(dev, "M0+ core release failed: %d\n", ret);
  1173. goto stop_spba_clk;
  1174. }
  1175. /* Let M0+ core complete firmware initialization */
  1176. msleep(50);
  1177. return 0;
  1178. stop_spba_clk:
  1179. clk_disable_unprepare(xcvr->spba_clk);
  1180. stop_phy_clk:
  1181. clk_disable_unprepare(xcvr->phy_clk);
  1182. stop_pll_ipg_clk:
  1183. clk_disable_unprepare(xcvr->pll_ipg_clk);
  1184. stop_ipg_clk:
  1185. clk_disable_unprepare(xcvr->ipg_clk);
  1186. return ret;
  1187. }
  1188. static const struct dev_pm_ops fsl_xcvr_pm_ops = {
  1189. SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
  1190. fsl_xcvr_runtime_resume,
  1191. NULL)
  1192. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1193. pm_runtime_force_resume)
  1194. };
  1195. static struct platform_driver fsl_xcvr_driver = {
  1196. .probe = fsl_xcvr_probe,
  1197. .driver = {
  1198. .name = "fsl,imx8mp-audio-xcvr",
  1199. .pm = &fsl_xcvr_pm_ops,
  1200. .of_match_table = fsl_xcvr_dt_ids,
  1201. },
  1202. .remove = fsl_xcvr_remove,
  1203. };
  1204. module_platform_driver(fsl_xcvr_driver);
  1205. MODULE_AUTHOR("Viorel Suman <[email protected]>");
  1206. MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
  1207. MODULE_LICENSE("GPL v2");