fsl_utils.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale ALSA SoC Machine driver utility
  4. //
  5. // Author: Timur Tabi <[email protected]>
  6. //
  7. // Copyright 2010 Freescale Semiconductor, Inc.
  8. #include <linux/clk.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/module.h>
  11. #include <linux/of_address.h>
  12. #include <sound/soc.h>
  13. #include "fsl_utils.h"
  14. /**
  15. * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
  16. *
  17. * @ssi_np: pointer to the SSI device tree node
  18. * @name: name of the phandle pointing to the dma channel
  19. * @dai: ASoC DAI link pointer to be filled with platform_name
  20. * @dma_channel_id: dma channel id to be returned
  21. * @dma_id: dma id to be returned
  22. *
  23. * This function determines the dma and channel id for given SSI node. It
  24. * also discovers the platform_name for the ASoC DAI link.
  25. */
  26. int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
  27. const char *name,
  28. struct snd_soc_dai_link *dai,
  29. unsigned int *dma_channel_id,
  30. unsigned int *dma_id)
  31. {
  32. struct resource res;
  33. struct device_node *dma_channel_np, *dma_np;
  34. const __be32 *iprop;
  35. int ret;
  36. dma_channel_np = of_parse_phandle(ssi_np, name, 0);
  37. if (!dma_channel_np)
  38. return -EINVAL;
  39. if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
  40. of_node_put(dma_channel_np);
  41. return -EINVAL;
  42. }
  43. /* Determine the dev_name for the device_node. This code mimics the
  44. * behavior of of_device_make_bus_id(). We need this because ASoC uses
  45. * the dev_name() of the device to match the platform (DMA) device with
  46. * the CPU (SSI) device. It's all ugly and hackish, but it works (for
  47. * now).
  48. *
  49. * dai->platform name should already point to an allocated buffer.
  50. */
  51. ret = of_address_to_resource(dma_channel_np, 0, &res);
  52. if (ret) {
  53. of_node_put(dma_channel_np);
  54. return ret;
  55. }
  56. snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn",
  57. (unsigned long long) res.start, dma_channel_np);
  58. iprop = of_get_property(dma_channel_np, "cell-index", NULL);
  59. if (!iprop) {
  60. of_node_put(dma_channel_np);
  61. return -EINVAL;
  62. }
  63. *dma_channel_id = be32_to_cpup(iprop);
  64. dma_np = of_get_parent(dma_channel_np);
  65. iprop = of_get_property(dma_np, "cell-index", NULL);
  66. if (!iprop) {
  67. of_node_put(dma_np);
  68. of_node_put(dma_channel_np);
  69. return -EINVAL;
  70. }
  71. *dma_id = be32_to_cpup(iprop);
  72. of_node_put(dma_np);
  73. of_node_put(dma_channel_np);
  74. return 0;
  75. }
  76. EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
  77. /**
  78. * fsl_asoc_get_pll_clocks - get two PLL clock source
  79. *
  80. * @dev: device pointer
  81. * @pll8k_clk: PLL clock pointer for 8kHz
  82. * @pll11k_clk: PLL clock pointer for 11kHz
  83. *
  84. * This function get two PLL clock source
  85. */
  86. void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
  87. struct clk **pll11k_clk)
  88. {
  89. *pll8k_clk = devm_clk_get(dev, "pll8k");
  90. if (IS_ERR(*pll8k_clk))
  91. *pll8k_clk = NULL;
  92. *pll11k_clk = devm_clk_get(dev, "pll11k");
  93. if (IS_ERR(*pll11k_clk))
  94. *pll11k_clk = NULL;
  95. }
  96. EXPORT_SYMBOL(fsl_asoc_get_pll_clocks);
  97. /**
  98. * fsl_asoc_reparent_pll_clocks - set clock parent if necessary
  99. *
  100. * @dev: device pointer
  101. * @clk: root clock pointer
  102. * @pll8k_clk: PLL clock pointer for 8kHz
  103. * @pll11k_clk: PLL clock pointer for 11kHz
  104. * @ratio: target requency for root clock
  105. *
  106. * This function set root clock parent according to the target ratio
  107. */
  108. void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
  109. struct clk *pll8k_clk,
  110. struct clk *pll11k_clk, u64 ratio)
  111. {
  112. struct clk *p, *pll = NULL, *npll = NULL;
  113. bool reparent = false;
  114. int ret;
  115. if (!clk || !pll8k_clk || !pll11k_clk)
  116. return;
  117. p = clk;
  118. while (p && pll8k_clk && pll11k_clk) {
  119. struct clk *pp = clk_get_parent(p);
  120. if (clk_is_match(pp, pll8k_clk) ||
  121. clk_is_match(pp, pll11k_clk)) {
  122. pll = pp;
  123. break;
  124. }
  125. p = pp;
  126. }
  127. npll = (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk);
  128. reparent = (pll && !clk_is_match(pll, npll));
  129. if (reparent) {
  130. ret = clk_set_parent(p, npll);
  131. if (ret < 0)
  132. dev_warn(dev, "failed to set parent:%d\n", ret);
  133. }
  134. }
  135. EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
  136. MODULE_AUTHOR("Timur Tabi <[email protected]>");
  137. MODULE_DESCRIPTION("Freescale ASoC utility code");
  138. MODULE_LICENSE("GPL v2");