fsl_spdif.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. *
  7. * Author: Nicolin Chen <[email protected]>
  8. *
  9. * Based on fsl_ssi.h
  10. * Author: Timur Tabi <[email protected]>
  11. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  12. */
  13. #ifndef _FSL_SPDIF_DAI_H
  14. #define _FSL_SPDIF_DAI_H
  15. /* S/PDIF Register Map */
  16. #define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
  17. #define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
  18. #define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
  19. #define REG_SPDIF_SIE 0xc /* InterruptEn Register */
  20. #define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
  21. #define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
  22. #define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
  23. #define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
  24. #define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
  25. #define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
  26. #define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
  27. #define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
  28. #define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
  29. #define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
  30. #define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
  31. #define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
  32. #define REG_SPDIF_STCSPH 0x3C /* SPDIFTxCChannel_Prof_h Register */
  33. #define REG_SPDIF_STCSPL 0x40 /* SPDIFTxCChannel_Prof_l Register */
  34. #define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
  35. #define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
  36. #define REG_SPDIF_SRCCA_31_0 0x60 /* SPDIF receive C channel register, bits 31-0 */
  37. #define REG_SPDIF_SRCCA_63_32 0x64 /* SPDIF receive C channel register, bits 63-32 */
  38. #define REG_SPDIF_SRCCA_95_64 0x68 /* SPDIF receive C channel register, bits 95-64 */
  39. #define REG_SPDIF_SRCCA_127_96 0x6C /* SPDIF receive C channel register, bits 127-96 */
  40. #define REG_SPDIF_SRCCA_159_128 0x70 /* SPDIF receive C channel register, bits 159-128 */
  41. #define REG_SPDIF_SRCCA_191_160 0x74 /* SPDIF receive C channel register, bits 191-160 */
  42. #define REG_SPDIF_STCCA_31_0 0x78 /* SPDIF transmit C channel register, bits 31-0 */
  43. #define REG_SPDIF_STCCA_63_32 0x7C /* SPDIF transmit C channel register, bits 63-32 */
  44. #define REG_SPDIF_STCCA_95_64 0x80 /* SPDIF transmit C channel register, bits 95-64 */
  45. #define REG_SPDIF_STCCA_127_96 0x84 /* SPDIF transmit C channel register, bits 127-96 */
  46. #define REG_SPDIF_STCCA_159_128 0x88 /* SPDIF transmit C channel register, bits 159-128 */
  47. #define REG_SPDIF_STCCA_191_160 0x8C /* SPDIF transmit C channel register, bits 191-160 */
  48. /* SPDIF Configuration register */
  49. #define SCR_RXFIFO_CTL_OFFSET 23
  50. #define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
  51. #define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
  52. #define SCR_RXFIFO_OFF_OFFSET 22
  53. #define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
  54. #define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
  55. #define SCR_RXFIFO_RST_OFFSET 21
  56. #define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
  57. #define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
  58. #define SCR_RXFIFO_FSEL_OFFSET 19
  59. #define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
  60. #define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
  61. #define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
  62. #define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
  63. #define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
  64. #define SCR_RXFIFO_AUTOSYNC_OFFSET 18
  65. #define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
  66. #define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
  67. #define SCR_TXFIFO_AUTOSYNC_OFFSET 17
  68. #define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
  69. #define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
  70. #define SCR_TXFIFO_FSEL_OFFSET 15
  71. #define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
  72. #define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
  73. #define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
  74. #define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
  75. #define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
  76. #define SCR_RAW_CAPTURE_MODE BIT(14)
  77. #define SCR_LOW_POWER (1 << 13)
  78. #define SCR_SOFT_RESET (1 << 12)
  79. #define SCR_TXFIFO_CTRL_OFFSET 10
  80. #define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
  81. #define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
  82. #define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
  83. #define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
  84. #define SCR_DMA_RX_EN_OFFSET 9
  85. #define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
  86. #define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
  87. #define SCR_DMA_TX_EN_OFFSET 8
  88. #define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
  89. #define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
  90. #define SCR_VAL_OFFSET 5
  91. #define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
  92. #define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
  93. #define SCR_TXSEL_OFFSET 2
  94. #define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
  95. #define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
  96. #define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
  97. #define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
  98. #define SCR_USRC_SEL_OFFSET 0x0
  99. #define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
  100. #define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
  101. #define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
  102. #define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
  103. #define SCR_DMA_xX_EN(tx) (tx ? SCR_DMA_TX_EN : SCR_DMA_RX_EN)
  104. /* SPDIF CDText control */
  105. #define SRCD_CD_USER_OFFSET 1
  106. #define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
  107. /* SPDIF Phase Configuration register */
  108. #define SRPC_DPLL_LOCKED (1 << 6)
  109. #define SRPC_CLKSRC_SEL_OFFSET 7
  110. #define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
  111. #define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
  112. #define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
  113. #define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
  114. #define SRPC_GAINSEL_OFFSET 3
  115. #define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
  116. #define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
  117. #define SRPC_CLKSRC_MAX 16
  118. enum spdif_gainsel {
  119. GAINSEL_MULTI_24 = 0,
  120. GAINSEL_MULTI_16,
  121. GAINSEL_MULTI_12,
  122. GAINSEL_MULTI_8,
  123. GAINSEL_MULTI_6,
  124. GAINSEL_MULTI_4,
  125. GAINSEL_MULTI_3,
  126. };
  127. #define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
  128. #define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
  129. /* SPDIF interrupt mask define */
  130. #define INT_DPLL_LOCKED (1 << 20)
  131. #define INT_TXFIFO_UNOV (1 << 19)
  132. #define INT_TXFIFO_RESYNC (1 << 18)
  133. #define INT_CNEW (1 << 17)
  134. #define INT_VAL_NOGOOD (1 << 16)
  135. #define INT_SYM_ERR (1 << 15)
  136. #define INT_BIT_ERR (1 << 14)
  137. #define INT_URX_FUL (1 << 10)
  138. #define INT_URX_OV (1 << 9)
  139. #define INT_QRX_FUL (1 << 8)
  140. #define INT_QRX_OV (1 << 7)
  141. #define INT_UQ_SYNC (1 << 6)
  142. #define INT_UQ_ERR (1 << 5)
  143. #define INT_RXFIFO_UNOV (1 << 4)
  144. #define INT_RXFIFO_RESYNC (1 << 3)
  145. #define INT_LOSS_LOCK (1 << 2)
  146. #define INT_TX_EM (1 << 1)
  147. #define INT_RXFIFO_FUL (1 << 0)
  148. /* SPDIF Clock register */
  149. #define STC_SYSCLK_DF_OFFSET 11
  150. #define STC_SYSCLK_DF_MASK (0x1ff << STC_SYSCLK_DF_OFFSET)
  151. #define STC_SYSCLK_DF(x) ((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)
  152. #define STC_TXCLK_SRC_OFFSET 8
  153. #define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
  154. #define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
  155. #define STC_TXCLK_ALL_EN_OFFSET 7
  156. #define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
  157. #define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
  158. #define STC_TXCLK_DF_OFFSET 0
  159. #define STC_TXCLK_DF_MASK (0x7f << STC_TXCLK_DF_OFFSET)
  160. #define STC_TXCLK_DF(x) ((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)
  161. #define STC_TXCLK_SRC_MAX 8
  162. #define STC_TXCLK_SPDIF_ROOT 1
  163. /* SPDIF tx rate */
  164. enum spdif_txrate {
  165. SPDIF_TXRATE_32000 = 0,
  166. SPDIF_TXRATE_44100,
  167. SPDIF_TXRATE_48000,
  168. SPDIF_TXRATE_88200,
  169. SPDIF_TXRATE_96000,
  170. SPDIF_TXRATE_176400,
  171. SPDIF_TXRATE_192000,
  172. };
  173. #define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1)
  174. #define SPDIF_CSTATUS_BYTE 6
  175. #define SPDIF_UBITS_SIZE 96
  176. #define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
  177. #define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
  178. SNDRV_PCM_RATE_44100 | \
  179. SNDRV_PCM_RATE_48000 | \
  180. SNDRV_PCM_RATE_88200 | \
  181. SNDRV_PCM_RATE_96000 | \
  182. SNDRV_PCM_RATE_176400 | \
  183. SNDRV_PCM_RATE_192000)
  184. #define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
  185. SNDRV_PCM_RATE_32000 | \
  186. SNDRV_PCM_RATE_44100 | \
  187. SNDRV_PCM_RATE_48000 | \
  188. SNDRV_PCM_RATE_88200 | \
  189. SNDRV_PCM_RATE_64000 | \
  190. SNDRV_PCM_RATE_96000 | \
  191. SNDRV_PCM_RATE_176400 | \
  192. SNDRV_PCM_RATE_192000)
  193. #define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
  194. SNDRV_PCM_FMTBIT_S20_3LE | \
  195. SNDRV_PCM_FMTBIT_S24_LE)
  196. #define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
  197. #endif /* _FSL_SPDIF_DAI_H */