fsl_spdif.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
  4. //
  5. // Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. //
  7. // Based on stmp3xxx_spdif_dai.c
  8. // Vladimir Barinov <[email protected]>
  9. // Copyright 2008 SigmaTel, Inc
  10. // Copyright 2008 Embedded Alley Solutions, Inc
  11. #include <linux/bitrev.h>
  12. #include <linux/clk.h>
  13. #include <linux/module.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/regmap.h>
  18. #include <linux/pm_runtime.h>
  19. #include <sound/asoundef.h>
  20. #include <sound/dmaengine_pcm.h>
  21. #include <sound/soc.h>
  22. #include "fsl_spdif.h"
  23. #include "fsl_utils.h"
  24. #include "imx-pcm.h"
  25. #define FSL_SPDIF_TXFIFO_WML 0x8
  26. #define FSL_SPDIF_RXFIFO_WML 0x8
  27. #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
  28. #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
  29. INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
  30. INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
  31. INT_LOSS_LOCK | INT_DPLL_LOCKED)
  32. #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
  33. /* Index list for the values that has if (DPLL Locked) condition */
  34. static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
  35. #define SRPC_NODPLL_START1 0x5
  36. #define SRPC_NODPLL_START2 0xc
  37. #define DEFAULT_RXCLK_SRC 1
  38. #define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate"
  39. /**
  40. * struct fsl_spdif_soc_data: soc specific data
  41. *
  42. * @imx: for imx platform
  43. * @shared_root_clock: flag of sharing a clock source with others;
  44. * so the driver shouldn't set root clock rate
  45. * @raw_capture_mode: if raw capture mode support
  46. * @cchannel_192b: if there are registers for 192bits C channel data
  47. * @interrupts: interrupt number
  48. * @tx_burst: tx maxburst size
  49. * @rx_burst: rx maxburst size
  50. * @tx_formats: tx supported data format
  51. */
  52. struct fsl_spdif_soc_data {
  53. bool imx;
  54. bool shared_root_clock;
  55. bool raw_capture_mode;
  56. bool cchannel_192b;
  57. u32 interrupts;
  58. u32 tx_burst;
  59. u32 rx_burst;
  60. u64 tx_formats;
  61. };
  62. /*
  63. * SPDIF control structure
  64. * Defines channel status, subcode and Q sub
  65. */
  66. struct spdif_mixer_control {
  67. /* spinlock to access control data */
  68. spinlock_t ctl_lock;
  69. /* IEC958 channel tx status bit */
  70. unsigned char ch_status[4];
  71. /* User bits */
  72. unsigned char subcode[2 * SPDIF_UBITS_SIZE];
  73. /* Q subcode part of user bits */
  74. unsigned char qsub[2 * SPDIF_QSUB_SIZE];
  75. /* Buffer offset for U/Q */
  76. u32 upos;
  77. u32 qpos;
  78. /* Ready buffer index of the two buffers */
  79. u32 ready_buf;
  80. };
  81. /**
  82. * struct fsl_spdif_priv - Freescale SPDIF private data
  83. * @soc: SPDIF soc data
  84. * @fsl_spdif_control: SPDIF control data
  85. * @cpu_dai_drv: cpu dai driver
  86. * @snd_card: sound card pointer
  87. * @rxrate_kcontrol: kcontrol for RX Sample Rate
  88. * @pdev: platform device pointer
  89. * @regmap: regmap handler
  90. * @dpll_locked: dpll lock flag
  91. * @txrate: the best rates for playback
  92. * @txclk_df: STC_TXCLK_DF dividers value for playback
  93. * @sysclk_df: STC_SYSCLK_DF dividers value for playback
  94. * @txclk_src: STC_TXCLK_SRC values for playback
  95. * @rxclk_src: SRPC_CLKSRC_SEL values for capture
  96. * @txclk: tx clock sources for playback
  97. * @rxclk: rx clock sources for capture
  98. * @coreclk: core clock for register access via DMA
  99. * @sysclk: system clock for rx clock rate measurement
  100. * @spbaclk: SPBA clock (optional, depending on SoC design)
  101. * @dma_params_tx: DMA parameters for transmit channel
  102. * @dma_params_rx: DMA parameters for receive channel
  103. * @regcache_srpc: regcache for SRPC
  104. * @bypass: status of bypass input to output
  105. * @pll8k_clk: PLL clock for the rate of multiply of 8kHz
  106. * @pll11k_clk: PLL clock for the rate of multiply of 11kHz
  107. */
  108. struct fsl_spdif_priv {
  109. const struct fsl_spdif_soc_data *soc;
  110. struct spdif_mixer_control fsl_spdif_control;
  111. struct snd_soc_dai_driver cpu_dai_drv;
  112. struct snd_card *snd_card;
  113. struct snd_kcontrol *rxrate_kcontrol;
  114. struct platform_device *pdev;
  115. struct regmap *regmap;
  116. bool dpll_locked;
  117. u32 txrate[SPDIF_TXRATE_MAX];
  118. u8 txclk_df[SPDIF_TXRATE_MAX];
  119. u16 sysclk_df[SPDIF_TXRATE_MAX];
  120. u8 txclk_src[SPDIF_TXRATE_MAX];
  121. u8 rxclk_src;
  122. struct clk *txclk[STC_TXCLK_SRC_MAX];
  123. struct clk *rxclk;
  124. struct clk *coreclk;
  125. struct clk *sysclk;
  126. struct clk *spbaclk;
  127. struct snd_dmaengine_dai_dma_data dma_params_tx;
  128. struct snd_dmaengine_dai_dma_data dma_params_rx;
  129. /* regcache for SRPC */
  130. u32 regcache_srpc;
  131. bool bypass;
  132. struct clk *pll8k_clk;
  133. struct clk *pll11k_clk;
  134. };
  135. static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
  136. .imx = false,
  137. .shared_root_clock = false,
  138. .raw_capture_mode = false,
  139. .interrupts = 1,
  140. .tx_burst = FSL_SPDIF_TXFIFO_WML,
  141. .rx_burst = FSL_SPDIF_RXFIFO_WML,
  142. .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
  143. };
  144. static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
  145. .imx = true,
  146. .shared_root_clock = false,
  147. .raw_capture_mode = false,
  148. .interrupts = 1,
  149. .tx_burst = FSL_SPDIF_TXFIFO_WML,
  150. .rx_burst = FSL_SPDIF_RXFIFO_WML,
  151. .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
  152. };
  153. static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
  154. .imx = true,
  155. .shared_root_clock = true,
  156. .raw_capture_mode = false,
  157. .interrupts = 1,
  158. .tx_burst = FSL_SPDIF_TXFIFO_WML,
  159. .rx_burst = FSL_SPDIF_RXFIFO_WML,
  160. .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
  161. };
  162. static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
  163. .imx = true,
  164. .shared_root_clock = true,
  165. .raw_capture_mode = false,
  166. .interrupts = 2,
  167. .tx_burst = 2, /* Applied for EDMA */
  168. .rx_burst = 2, /* Applied for EDMA */
  169. .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
  170. };
  171. static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
  172. .imx = true,
  173. .shared_root_clock = false,
  174. .raw_capture_mode = true,
  175. .interrupts = 1,
  176. .tx_burst = FSL_SPDIF_TXFIFO_WML,
  177. .rx_burst = FSL_SPDIF_RXFIFO_WML,
  178. .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
  179. };
  180. static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
  181. .imx = true,
  182. .shared_root_clock = true,
  183. .raw_capture_mode = false,
  184. .interrupts = 1,
  185. .tx_burst = 2, /* Applied for EDMA */
  186. .rx_burst = 2, /* Applied for EDMA */
  187. .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
  188. .cchannel_192b = true,
  189. };
  190. /* Check if clk is a root clock that does not share clock source with others */
  191. static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
  192. {
  193. return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
  194. }
  195. /* DPLL locked and lock loss interrupt handler */
  196. static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
  197. {
  198. struct regmap *regmap = spdif_priv->regmap;
  199. struct platform_device *pdev = spdif_priv->pdev;
  200. u32 locked;
  201. regmap_read(regmap, REG_SPDIF_SRPC, &locked);
  202. locked &= SRPC_DPLL_LOCKED;
  203. dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
  204. locked ? "locked" : "loss lock");
  205. spdif_priv->dpll_locked = locked ? true : false;
  206. if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) {
  207. snd_ctl_notify(spdif_priv->snd_card,
  208. SNDRV_CTL_EVENT_MASK_VALUE,
  209. &spdif_priv->rxrate_kcontrol->id);
  210. }
  211. }
  212. /* Receiver found illegal symbol interrupt handler */
  213. static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
  214. {
  215. struct regmap *regmap = spdif_priv->regmap;
  216. struct platform_device *pdev = spdif_priv->pdev;
  217. dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
  218. /* Clear illegal symbol if DPLL unlocked since no audio stream */
  219. if (!spdif_priv->dpll_locked)
  220. regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
  221. }
  222. /* U/Q Channel receive register full */
  223. static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
  224. {
  225. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  226. struct regmap *regmap = spdif_priv->regmap;
  227. struct platform_device *pdev = spdif_priv->pdev;
  228. u32 *pos, size, val, reg;
  229. switch (name) {
  230. case 'U':
  231. pos = &ctrl->upos;
  232. size = SPDIF_UBITS_SIZE;
  233. reg = REG_SPDIF_SRU;
  234. break;
  235. case 'Q':
  236. pos = &ctrl->qpos;
  237. size = SPDIF_QSUB_SIZE;
  238. reg = REG_SPDIF_SRQ;
  239. break;
  240. default:
  241. dev_err(&pdev->dev, "unsupported channel name\n");
  242. return;
  243. }
  244. dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
  245. if (*pos >= size * 2) {
  246. *pos = 0;
  247. } else if (unlikely((*pos % size) + 3 > size)) {
  248. dev_err(&pdev->dev, "User bit receive buffer overflow\n");
  249. return;
  250. }
  251. regmap_read(regmap, reg, &val);
  252. ctrl->subcode[*pos++] = val >> 16;
  253. ctrl->subcode[*pos++] = val >> 8;
  254. ctrl->subcode[*pos++] = val;
  255. }
  256. /* U/Q Channel sync found */
  257. static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
  258. {
  259. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  260. struct platform_device *pdev = spdif_priv->pdev;
  261. dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
  262. /* U/Q buffer reset */
  263. if (ctrl->qpos == 0)
  264. return;
  265. /* Set ready to this buffer */
  266. ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
  267. }
  268. /* U/Q Channel framing error */
  269. static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
  270. {
  271. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  272. struct regmap *regmap = spdif_priv->regmap;
  273. struct platform_device *pdev = spdif_priv->pdev;
  274. u32 val;
  275. dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
  276. /* Read U/Q data to clear the irq and do buffer reset */
  277. regmap_read(regmap, REG_SPDIF_SRU, &val);
  278. regmap_read(regmap, REG_SPDIF_SRQ, &val);
  279. /* Drop this U/Q buffer */
  280. ctrl->ready_buf = 0;
  281. ctrl->upos = 0;
  282. ctrl->qpos = 0;
  283. }
  284. /* Get spdif interrupt status and clear the interrupt */
  285. static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
  286. {
  287. struct regmap *regmap = spdif_priv->regmap;
  288. u32 val, val2;
  289. regmap_read(regmap, REG_SPDIF_SIS, &val);
  290. regmap_read(regmap, REG_SPDIF_SIE, &val2);
  291. regmap_write(regmap, REG_SPDIF_SIC, val & val2);
  292. return val;
  293. }
  294. static irqreturn_t spdif_isr(int irq, void *devid)
  295. {
  296. struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
  297. struct platform_device *pdev = spdif_priv->pdev;
  298. u32 sis;
  299. sis = spdif_intr_status_clear(spdif_priv);
  300. if (sis & INT_DPLL_LOCKED)
  301. spdif_irq_dpll_lock(spdif_priv);
  302. if (sis & INT_TXFIFO_UNOV)
  303. dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
  304. if (sis & INT_TXFIFO_RESYNC)
  305. dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
  306. if (sis & INT_CNEW)
  307. dev_dbg(&pdev->dev, "isr: cstatus new\n");
  308. if (sis & INT_VAL_NOGOOD)
  309. dev_dbg(&pdev->dev, "isr: validity flag no good\n");
  310. if (sis & INT_SYM_ERR)
  311. spdif_irq_sym_error(spdif_priv);
  312. if (sis & INT_BIT_ERR)
  313. dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
  314. if (sis & INT_URX_FUL)
  315. spdif_irq_uqrx_full(spdif_priv, 'U');
  316. if (sis & INT_URX_OV)
  317. dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
  318. if (sis & INT_QRX_FUL)
  319. spdif_irq_uqrx_full(spdif_priv, 'Q');
  320. if (sis & INT_QRX_OV)
  321. dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
  322. if (sis & INT_UQ_SYNC)
  323. spdif_irq_uq_sync(spdif_priv);
  324. if (sis & INT_UQ_ERR)
  325. spdif_irq_uq_err(spdif_priv);
  326. if (sis & INT_RXFIFO_UNOV)
  327. dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
  328. if (sis & INT_RXFIFO_RESYNC)
  329. dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
  330. if (sis & INT_LOSS_LOCK)
  331. spdif_irq_dpll_lock(spdif_priv);
  332. /* FIXME: Write Tx FIFO to clear TxEm */
  333. if (sis & INT_TX_EM)
  334. dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
  335. /* FIXME: Read Rx FIFO to clear RxFIFOFul */
  336. if (sis & INT_RXFIFO_FUL)
  337. dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
  338. return IRQ_HANDLED;
  339. }
  340. static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
  341. {
  342. struct regmap *regmap = spdif_priv->regmap;
  343. u32 val, cycle = 1000;
  344. regcache_cache_bypass(regmap, true);
  345. regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
  346. /*
  347. * RESET bit would be cleared after finishing its reset procedure,
  348. * which typically lasts 8 cycles. 1000 cycles will keep it safe.
  349. */
  350. do {
  351. regmap_read(regmap, REG_SPDIF_SCR, &val);
  352. } while ((val & SCR_SOFT_RESET) && cycle--);
  353. regcache_cache_bypass(regmap, false);
  354. regcache_mark_dirty(regmap);
  355. regcache_sync(regmap);
  356. if (cycle)
  357. return 0;
  358. else
  359. return -EBUSY;
  360. }
  361. static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
  362. u8 mask, u8 cstatus)
  363. {
  364. ctrl->ch_status[3] &= ~mask;
  365. ctrl->ch_status[3] |= cstatus & mask;
  366. }
  367. static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
  368. {
  369. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  370. struct regmap *regmap = spdif_priv->regmap;
  371. struct platform_device *pdev = spdif_priv->pdev;
  372. u32 ch_status;
  373. ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
  374. (bitrev8(ctrl->ch_status[1]) << 8) |
  375. bitrev8(ctrl->ch_status[2]);
  376. regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
  377. dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
  378. ch_status = bitrev8(ctrl->ch_status[3]) << 16;
  379. regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
  380. dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
  381. if (spdif_priv->soc->cchannel_192b) {
  382. ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
  383. (bitrev8(ctrl->ch_status[1]) << 16) |
  384. (bitrev8(ctrl->ch_status[2]) << 8) |
  385. bitrev8(ctrl->ch_status[3]);
  386. regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
  387. /*
  388. * The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
  389. * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
  390. * then can get correct result with HDMI analyzer capture.
  391. * There is a hardware bug here.
  392. */
  393. regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
  394. }
  395. }
  396. /* Set SPDIF PhaseConfig register for rx clock */
  397. static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
  398. enum spdif_gainsel gainsel, int dpll_locked)
  399. {
  400. struct regmap *regmap = spdif_priv->regmap;
  401. u8 clksrc = spdif_priv->rxclk_src;
  402. if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
  403. return -EINVAL;
  404. regmap_update_bits(regmap, REG_SPDIF_SRPC,
  405. SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
  406. SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
  407. return 0;
  408. }
  409. static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index);
  410. static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
  411. int sample_rate)
  412. {
  413. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  414. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  415. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  416. struct regmap *regmap = spdif_priv->regmap;
  417. struct platform_device *pdev = spdif_priv->pdev;
  418. unsigned long csfs = 0;
  419. u32 stc, mask, rate;
  420. u16 sysclk_df;
  421. u8 clk, txclk_df;
  422. int ret;
  423. switch (sample_rate) {
  424. case 32000:
  425. rate = SPDIF_TXRATE_32000;
  426. csfs = IEC958_AES3_CON_FS_32000;
  427. break;
  428. case 44100:
  429. rate = SPDIF_TXRATE_44100;
  430. csfs = IEC958_AES3_CON_FS_44100;
  431. break;
  432. case 48000:
  433. rate = SPDIF_TXRATE_48000;
  434. csfs = IEC958_AES3_CON_FS_48000;
  435. break;
  436. case 88200:
  437. rate = SPDIF_TXRATE_88200;
  438. csfs = IEC958_AES3_CON_FS_88200;
  439. break;
  440. case 96000:
  441. rate = SPDIF_TXRATE_96000;
  442. csfs = IEC958_AES3_CON_FS_96000;
  443. break;
  444. case 176400:
  445. rate = SPDIF_TXRATE_176400;
  446. csfs = IEC958_AES3_CON_FS_176400;
  447. break;
  448. case 192000:
  449. rate = SPDIF_TXRATE_192000;
  450. csfs = IEC958_AES3_CON_FS_192000;
  451. break;
  452. default:
  453. dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
  454. return -EINVAL;
  455. }
  456. ret = fsl_spdif_probe_txclk(spdif_priv, rate);
  457. if (ret)
  458. return ret;
  459. clk = spdif_priv->txclk_src[rate];
  460. if (clk >= STC_TXCLK_SRC_MAX) {
  461. dev_err(&pdev->dev, "tx clock source is out of range\n");
  462. return -EINVAL;
  463. }
  464. txclk_df = spdif_priv->txclk_df[rate];
  465. if (txclk_df == 0) {
  466. dev_err(&pdev->dev, "the txclk_df can't be zero\n");
  467. return -EINVAL;
  468. }
  469. sysclk_df = spdif_priv->sysclk_df[rate];
  470. if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
  471. goto clk_set_bypass;
  472. /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
  473. ret = clk_set_rate(spdif_priv->txclk[clk],
  474. 64 * sample_rate * txclk_df);
  475. if (ret) {
  476. dev_err(&pdev->dev, "failed to set tx clock rate\n");
  477. return ret;
  478. }
  479. clk_set_bypass:
  480. dev_dbg(&pdev->dev, "expected clock rate = %d\n",
  481. (64 * sample_rate * txclk_df * sysclk_df));
  482. dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
  483. clk_get_rate(spdif_priv->txclk[clk]));
  484. /* set fs field in consumer channel status */
  485. spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
  486. /* select clock source and divisor */
  487. stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
  488. STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
  489. mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
  490. STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
  491. regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
  492. dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
  493. spdif_priv->txrate[rate], sample_rate);
  494. return 0;
  495. }
  496. static int fsl_spdif_startup(struct snd_pcm_substream *substream,
  497. struct snd_soc_dai *cpu_dai)
  498. {
  499. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  500. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  501. struct platform_device *pdev = spdif_priv->pdev;
  502. struct regmap *regmap = spdif_priv->regmap;
  503. u32 scr, mask;
  504. int ret;
  505. /* Reset module and interrupts only for first initialization */
  506. if (!snd_soc_dai_active(cpu_dai)) {
  507. ret = spdif_softreset(spdif_priv);
  508. if (ret) {
  509. dev_err(&pdev->dev, "failed to soft reset\n");
  510. return ret;
  511. }
  512. /* Disable all the interrupts */
  513. regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
  514. }
  515. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  516. scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
  517. SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
  518. SCR_TXFIFO_FSEL_IF8;
  519. mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
  520. SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
  521. SCR_TXFIFO_FSEL_MASK;
  522. } else {
  523. scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
  524. mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
  525. SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
  526. }
  527. regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
  528. /* Power up SPDIF module */
  529. regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
  530. return 0;
  531. }
  532. static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
  533. struct snd_soc_dai *cpu_dai)
  534. {
  535. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  536. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  537. struct regmap *regmap = spdif_priv->regmap;
  538. u32 scr, mask;
  539. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  540. scr = 0;
  541. mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
  542. SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
  543. SCR_TXFIFO_FSEL_MASK;
  544. /* Disable TX clock */
  545. regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
  546. } else {
  547. scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
  548. mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
  549. SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
  550. }
  551. regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
  552. /* Power down SPDIF module only if tx&rx are both inactive */
  553. if (!snd_soc_dai_active(cpu_dai)) {
  554. spdif_intr_status_clear(spdif_priv);
  555. regmap_update_bits(regmap, REG_SPDIF_SCR,
  556. SCR_LOW_POWER, SCR_LOW_POWER);
  557. }
  558. }
  559. static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate)
  560. {
  561. struct platform_device *pdev = spdif_priv->pdev;
  562. struct clk *clk;
  563. int ret;
  564. /* Reparent clock if required condition is true */
  565. if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT))
  566. return 0;
  567. /* Get root clock */
  568. clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT];
  569. /* Disable clock first, for it was enabled by pm_runtime */
  570. clk_disable_unprepare(clk);
  571. fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk,
  572. spdif_priv->pll11k_clk, sample_rate);
  573. ret = clk_prepare_enable(clk);
  574. if (ret)
  575. return ret;
  576. return 0;
  577. }
  578. static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
  579. struct snd_pcm_hw_params *params,
  580. struct snd_soc_dai *dai)
  581. {
  582. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  583. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  584. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  585. struct platform_device *pdev = spdif_priv->pdev;
  586. u32 sample_rate = params_rate(params);
  587. int ret = 0;
  588. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  589. ret = spdif_reparent_rootclk(spdif_priv, sample_rate);
  590. if (ret) {
  591. dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n",
  592. __func__, sample_rate);
  593. return ret;
  594. }
  595. ret = spdif_set_sample_rate(substream, sample_rate);
  596. if (ret) {
  597. dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
  598. __func__, sample_rate);
  599. return ret;
  600. }
  601. spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
  602. IEC958_AES3_CON_CLOCK_1000PPM);
  603. spdif_write_channel_status(spdif_priv);
  604. } else {
  605. /* Setup rx clock source */
  606. ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
  607. }
  608. return ret;
  609. }
  610. static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
  611. int cmd, struct snd_soc_dai *dai)
  612. {
  613. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  614. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  615. struct regmap *regmap = spdif_priv->regmap;
  616. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  617. u32 intr = SIE_INTR_FOR(tx);
  618. u32 dmaen = SCR_DMA_xX_EN(tx);
  619. switch (cmd) {
  620. case SNDRV_PCM_TRIGGER_START:
  621. case SNDRV_PCM_TRIGGER_RESUME:
  622. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  623. regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
  624. regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
  625. break;
  626. case SNDRV_PCM_TRIGGER_STOP:
  627. case SNDRV_PCM_TRIGGER_SUSPEND:
  628. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  629. regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
  630. regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
  631. regmap_write(regmap, REG_SPDIF_STL, 0x0);
  632. regmap_write(regmap, REG_SPDIF_STR, 0x0);
  633. break;
  634. default:
  635. return -EINVAL;
  636. }
  637. return 0;
  638. }
  639. static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
  640. .startup = fsl_spdif_startup,
  641. .hw_params = fsl_spdif_hw_params,
  642. .trigger = fsl_spdif_trigger,
  643. .shutdown = fsl_spdif_shutdown,
  644. };
  645. /*
  646. * FSL SPDIF IEC958 controller(mixer) functions
  647. *
  648. * Channel status get/put control
  649. * User bit value get/put control
  650. * Valid bit value get control
  651. * DPLL lock status get control
  652. * User bit sync mode selection control
  653. */
  654. static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
  655. struct snd_ctl_elem_info *uinfo)
  656. {
  657. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  658. uinfo->count = 1;
  659. return 0;
  660. }
  661. static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
  662. struct snd_ctl_elem_value *uvalue)
  663. {
  664. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  665. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  666. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  667. uvalue->value.iec958.status[0] = ctrl->ch_status[0];
  668. uvalue->value.iec958.status[1] = ctrl->ch_status[1];
  669. uvalue->value.iec958.status[2] = ctrl->ch_status[2];
  670. uvalue->value.iec958.status[3] = ctrl->ch_status[3];
  671. return 0;
  672. }
  673. static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
  674. struct snd_ctl_elem_value *uvalue)
  675. {
  676. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  677. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  678. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  679. ctrl->ch_status[0] = uvalue->value.iec958.status[0];
  680. ctrl->ch_status[1] = uvalue->value.iec958.status[1];
  681. ctrl->ch_status[2] = uvalue->value.iec958.status[2];
  682. ctrl->ch_status[3] = uvalue->value.iec958.status[3];
  683. spdif_write_channel_status(spdif_priv);
  684. return 0;
  685. }
  686. /* Get channel status from SPDIF_RX_CCHAN register */
  687. static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
  688. struct snd_ctl_elem_value *ucontrol)
  689. {
  690. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  691. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  692. struct regmap *regmap = spdif_priv->regmap;
  693. u32 cstatus, val;
  694. regmap_read(regmap, REG_SPDIF_SIS, &val);
  695. if (!(val & INT_CNEW))
  696. return -EAGAIN;
  697. regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
  698. ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
  699. ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
  700. ucontrol->value.iec958.status[2] = cstatus & 0xFF;
  701. regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
  702. ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
  703. ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
  704. ucontrol->value.iec958.status[5] = cstatus & 0xFF;
  705. /* Clear intr */
  706. regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
  707. return 0;
  708. }
  709. /*
  710. * Get User bits (subcode) from chip value which readed out
  711. * in UChannel register.
  712. */
  713. static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
  714. struct snd_ctl_elem_value *ucontrol)
  715. {
  716. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  717. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  718. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  719. unsigned long flags;
  720. int ret = -EAGAIN;
  721. spin_lock_irqsave(&ctrl->ctl_lock, flags);
  722. if (ctrl->ready_buf) {
  723. int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
  724. memcpy(&ucontrol->value.iec958.subcode[0],
  725. &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
  726. ret = 0;
  727. }
  728. spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
  729. return ret;
  730. }
  731. /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
  732. static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
  733. struct snd_ctl_elem_info *uinfo)
  734. {
  735. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  736. uinfo->count = SPDIF_QSUB_SIZE;
  737. return 0;
  738. }
  739. /* Get Q subcode from chip value which readed out in QChannel register */
  740. static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
  741. struct snd_ctl_elem_value *ucontrol)
  742. {
  743. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  744. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  745. struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
  746. unsigned long flags;
  747. int ret = -EAGAIN;
  748. spin_lock_irqsave(&ctrl->ctl_lock, flags);
  749. if (ctrl->ready_buf) {
  750. int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
  751. memcpy(&ucontrol->value.bytes.data[0],
  752. &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
  753. ret = 0;
  754. }
  755. spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
  756. return ret;
  757. }
  758. /* Get valid good bit from interrupt status register */
  759. static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
  760. struct snd_ctl_elem_value *ucontrol)
  761. {
  762. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  763. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  764. struct regmap *regmap = spdif_priv->regmap;
  765. u32 val;
  766. regmap_read(regmap, REG_SPDIF_SIS, &val);
  767. ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
  768. regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
  769. return 0;
  770. }
  771. static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
  772. struct snd_ctl_elem_value *ucontrol)
  773. {
  774. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  775. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  776. struct regmap *regmap = spdif_priv->regmap;
  777. u32 val;
  778. regmap_read(regmap, REG_SPDIF_SCR, &val);
  779. val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
  780. val = 1 - val;
  781. ucontrol->value.integer.value[0] = val;
  782. return 0;
  783. }
  784. static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
  785. struct snd_ctl_elem_value *ucontrol)
  786. {
  787. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  788. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  789. struct regmap *regmap = spdif_priv->regmap;
  790. u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
  791. regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
  792. return 0;
  793. }
  794. static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,
  795. struct snd_ctl_elem_value *ucontrol)
  796. {
  797. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  798. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  799. struct regmap *regmap = spdif_priv->regmap;
  800. u32 val;
  801. regmap_read(regmap, REG_SPDIF_SCR, &val);
  802. val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;
  803. ucontrol->value.integer.value[0] = val;
  804. return 0;
  805. }
  806. static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,
  807. struct snd_ctl_elem_value *ucontrol)
  808. {
  809. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  810. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  811. struct regmap *regmap = spdif_priv->regmap;
  812. u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);
  813. if (val)
  814. cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;
  815. else
  816. cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;
  817. regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);
  818. return 0;
  819. }
  820. static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol,
  821. struct snd_ctl_elem_value *ucontrol)
  822. {
  823. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  824. struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
  825. ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0;
  826. return 0;
  827. }
  828. static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol,
  829. struct snd_ctl_elem_value *ucontrol)
  830. {
  831. struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
  832. struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
  833. struct snd_soc_card *card = dai->component->card;
  834. bool set = (ucontrol->value.integer.value[0] != 0);
  835. struct regmap *regmap = priv->regmap;
  836. struct snd_soc_pcm_runtime *rtd;
  837. u32 scr, mask;
  838. int stream;
  839. rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
  840. if (priv->bypass == set)
  841. return 0; /* nothing to do */
  842. if (snd_soc_dai_active(dai)) {
  843. dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n");
  844. return -EBUSY;
  845. }
  846. pm_runtime_get_sync(dai->dev);
  847. if (set) {
  848. /* Disable interrupts */
  849. regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
  850. /* Configure BYPASS mode */
  851. scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF;
  852. mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK |
  853. SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK;
  854. /* Power up SPDIF module */
  855. mask |= SCR_LOW_POWER;
  856. } else {
  857. /* Power down SPDIF module, disable TX */
  858. scr = SCR_LOW_POWER | SCR_TXSEL_OFF;
  859. mask = SCR_LOW_POWER | SCR_TXSEL_MASK;
  860. }
  861. regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
  862. /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */
  863. for_each_pcm_streams(stream)
  864. rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);
  865. priv->bypass = set;
  866. pm_runtime_put_sync(dai->dev);
  867. return 0;
  868. }
  869. /* DPLL lock information */
  870. static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
  871. struct snd_ctl_elem_info *uinfo)
  872. {
  873. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  874. uinfo->count = 1;
  875. uinfo->value.integer.min = 16000;
  876. uinfo->value.integer.max = 192000;
  877. return 0;
  878. }
  879. static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
  880. 24, 16, 12, 8, 6, 4, 3,
  881. };
  882. /* Get RX data clock rate given the SPDIF bus_clk */
  883. static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
  884. enum spdif_gainsel gainsel)
  885. {
  886. struct regmap *regmap = spdif_priv->regmap;
  887. struct platform_device *pdev = spdif_priv->pdev;
  888. u64 tmpval64, busclk_freq = 0;
  889. u32 freqmeas, phaseconf;
  890. u8 clksrc;
  891. regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
  892. regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
  893. clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
  894. /* Get bus clock from system */
  895. if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
  896. busclk_freq = clk_get_rate(spdif_priv->sysclk);
  897. /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
  898. tmpval64 = (u64) busclk_freq * freqmeas;
  899. do_div(tmpval64, gainsel_multi[gainsel] * 1024);
  900. do_div(tmpval64, 128 * 1024);
  901. dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
  902. dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
  903. dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
  904. return (int)tmpval64;
  905. }
  906. /*
  907. * Get DPLL lock or not info from stable interrupt status register.
  908. * User application must use this control to get locked,
  909. * then can do next PCM operation
  910. */
  911. static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  915. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  916. int rate = 0;
  917. if (spdif_priv->dpll_locked)
  918. rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
  919. ucontrol->value.integer.value[0] = rate;
  920. return 0;
  921. }
  922. /*
  923. * User bit sync mode:
  924. * 1 CD User channel subcode
  925. * 0 Non-CD data
  926. */
  927. static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
  928. struct snd_ctl_elem_value *ucontrol)
  929. {
  930. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  931. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  932. struct regmap *regmap = spdif_priv->regmap;
  933. u32 val;
  934. regmap_read(regmap, REG_SPDIF_SRCD, &val);
  935. ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
  936. return 0;
  937. }
  938. /*
  939. * User bit sync mode:
  940. * 1 CD User channel subcode
  941. * 0 Non-CD data
  942. */
  943. static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
  944. struct snd_ctl_elem_value *ucontrol)
  945. {
  946. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  947. struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
  948. struct regmap *regmap = spdif_priv->regmap;
  949. u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
  950. regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
  951. return 0;
  952. }
  953. /* FSL SPDIF IEC958 controller defines */
  954. static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
  955. /* Status cchanel controller */
  956. {
  957. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  958. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  959. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  960. SNDRV_CTL_ELEM_ACCESS_WRITE |
  961. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  962. .info = fsl_spdif_info,
  963. .get = fsl_spdif_pb_get,
  964. .put = fsl_spdif_pb_put,
  965. },
  966. {
  967. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  968. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
  969. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  970. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  971. .info = fsl_spdif_info,
  972. .get = fsl_spdif_capture_get,
  973. },
  974. /* User bits controller */
  975. {
  976. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  977. .name = "IEC958 Subcode Capture Default",
  978. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  979. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  980. .info = fsl_spdif_info,
  981. .get = fsl_spdif_subcode_get,
  982. },
  983. {
  984. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  985. .name = "IEC958 Q-subcode Capture Default",
  986. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  987. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  988. .info = fsl_spdif_qinfo,
  989. .get = fsl_spdif_qget,
  990. },
  991. /* Valid bit error controller */
  992. {
  993. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  994. .name = "IEC958 RX V-Bit Errors",
  995. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  996. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  997. .info = snd_ctl_boolean_mono_info,
  998. .get = fsl_spdif_rx_vbit_get,
  999. },
  1000. {
  1001. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1002. .name = "IEC958 TX V-Bit",
  1003. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  1004. SNDRV_CTL_ELEM_ACCESS_WRITE |
  1005. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1006. .info = snd_ctl_boolean_mono_info,
  1007. .get = fsl_spdif_tx_vbit_get,
  1008. .put = fsl_spdif_tx_vbit_put,
  1009. },
  1010. /* DPLL lock info get controller */
  1011. {
  1012. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1013. .name = RX_SAMPLE_RATE_KCONTROL,
  1014. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  1015. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1016. .info = fsl_spdif_rxrate_info,
  1017. .get = fsl_spdif_rxrate_get,
  1018. },
  1019. /* RX bypass controller */
  1020. {
  1021. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1022. .name = "Bypass Mode",
  1023. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1024. .info = snd_ctl_boolean_mono_info,
  1025. .get = fsl_spdif_bypass_get,
  1026. .put = fsl_spdif_bypass_put,
  1027. },
  1028. /* User bit sync mode set/get controller */
  1029. {
  1030. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1031. .name = "IEC958 USyncMode CDText",
  1032. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  1033. SNDRV_CTL_ELEM_ACCESS_WRITE |
  1034. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1035. .info = snd_ctl_boolean_mono_info,
  1036. .get = fsl_spdif_usync_get,
  1037. .put = fsl_spdif_usync_put,
  1038. },
  1039. };
  1040. static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {
  1041. {
  1042. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1043. .name = "IEC958 Raw Capture Mode",
  1044. .access = SNDRV_CTL_ELEM_ACCESS_READ |
  1045. SNDRV_CTL_ELEM_ACCESS_WRITE |
  1046. SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1047. .info = snd_ctl_boolean_mono_info,
  1048. .get = fsl_spdif_rx_rcm_get,
  1049. .put = fsl_spdif_rx_rcm_put,
  1050. },
  1051. };
  1052. static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
  1053. {
  1054. struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
  1055. snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
  1056. &spdif_private->dma_params_rx);
  1057. snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
  1058. if (spdif_private->soc->raw_capture_mode)
  1059. snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,
  1060. ARRAY_SIZE(fsl_spdif_ctrls_rcm));
  1061. spdif_private->snd_card = dai->component->card->snd_card;
  1062. spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card,
  1063. RX_SAMPLE_RATE_KCONTROL);
  1064. if (!spdif_private->rxrate_kcontrol)
  1065. dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n",
  1066. RX_SAMPLE_RATE_KCONTROL);
  1067. /*Clear the val bit for Tx*/
  1068. regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
  1069. SCR_VAL_MASK, SCR_VAL_CLEAR);
  1070. return 0;
  1071. }
  1072. static struct snd_soc_dai_driver fsl_spdif_dai = {
  1073. .probe = &fsl_spdif_dai_probe,
  1074. .playback = {
  1075. .stream_name = "CPU-Playback",
  1076. .channels_min = 2,
  1077. .channels_max = 2,
  1078. .rates = FSL_SPDIF_RATES_PLAYBACK,
  1079. .formats = FSL_SPDIF_FORMATS_PLAYBACK,
  1080. },
  1081. .capture = {
  1082. .stream_name = "CPU-Capture",
  1083. .channels_min = 2,
  1084. .channels_max = 2,
  1085. .rates = FSL_SPDIF_RATES_CAPTURE,
  1086. .formats = FSL_SPDIF_FORMATS_CAPTURE,
  1087. },
  1088. .ops = &fsl_spdif_dai_ops,
  1089. };
  1090. static const struct snd_soc_component_driver fsl_spdif_component = {
  1091. .name = "fsl-spdif",
  1092. .legacy_dai_naming = 1,
  1093. };
  1094. /* FSL SPDIF REGMAP */
  1095. static const struct reg_default fsl_spdif_reg_defaults[] = {
  1096. {REG_SPDIF_SCR, 0x00000400},
  1097. {REG_SPDIF_SRCD, 0x00000000},
  1098. {REG_SPDIF_SIE, 0x00000000},
  1099. {REG_SPDIF_STL, 0x00000000},
  1100. {REG_SPDIF_STR, 0x00000000},
  1101. {REG_SPDIF_STCSCH, 0x00000000},
  1102. {REG_SPDIF_STCSCL, 0x00000000},
  1103. {REG_SPDIF_STCSPH, 0x00000000},
  1104. {REG_SPDIF_STCSPL, 0x00000000},
  1105. {REG_SPDIF_STC, 0x00020f00},
  1106. };
  1107. static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
  1108. {
  1109. switch (reg) {
  1110. case REG_SPDIF_SCR:
  1111. case REG_SPDIF_SRCD:
  1112. case REG_SPDIF_SRPC:
  1113. case REG_SPDIF_SIE:
  1114. case REG_SPDIF_SIS:
  1115. case REG_SPDIF_SRL:
  1116. case REG_SPDIF_SRR:
  1117. case REG_SPDIF_SRCSH:
  1118. case REG_SPDIF_SRCSL:
  1119. case REG_SPDIF_SRU:
  1120. case REG_SPDIF_SRQ:
  1121. case REG_SPDIF_STCSCH:
  1122. case REG_SPDIF_STCSCL:
  1123. case REG_SPDIF_STCSPH:
  1124. case REG_SPDIF_STCSPL:
  1125. case REG_SPDIF_SRFM:
  1126. case REG_SPDIF_STC:
  1127. case REG_SPDIF_SRCCA_31_0:
  1128. case REG_SPDIF_SRCCA_63_32:
  1129. case REG_SPDIF_SRCCA_95_64:
  1130. case REG_SPDIF_SRCCA_127_96:
  1131. case REG_SPDIF_SRCCA_159_128:
  1132. case REG_SPDIF_SRCCA_191_160:
  1133. case REG_SPDIF_STCCA_31_0:
  1134. case REG_SPDIF_STCCA_63_32:
  1135. case REG_SPDIF_STCCA_95_64:
  1136. case REG_SPDIF_STCCA_127_96:
  1137. case REG_SPDIF_STCCA_159_128:
  1138. case REG_SPDIF_STCCA_191_160:
  1139. return true;
  1140. default:
  1141. return false;
  1142. }
  1143. }
  1144. static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
  1145. {
  1146. switch (reg) {
  1147. case REG_SPDIF_SRPC:
  1148. case REG_SPDIF_SIS:
  1149. case REG_SPDIF_SRL:
  1150. case REG_SPDIF_SRR:
  1151. case REG_SPDIF_SRCSH:
  1152. case REG_SPDIF_SRCSL:
  1153. case REG_SPDIF_SRU:
  1154. case REG_SPDIF_SRQ:
  1155. case REG_SPDIF_SRFM:
  1156. case REG_SPDIF_SRCCA_31_0:
  1157. case REG_SPDIF_SRCCA_63_32:
  1158. case REG_SPDIF_SRCCA_95_64:
  1159. case REG_SPDIF_SRCCA_127_96:
  1160. case REG_SPDIF_SRCCA_159_128:
  1161. case REG_SPDIF_SRCCA_191_160:
  1162. return true;
  1163. default:
  1164. return false;
  1165. }
  1166. }
  1167. static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
  1168. {
  1169. switch (reg) {
  1170. case REG_SPDIF_SCR:
  1171. case REG_SPDIF_SRCD:
  1172. case REG_SPDIF_SRPC:
  1173. case REG_SPDIF_SIE:
  1174. case REG_SPDIF_SIC:
  1175. case REG_SPDIF_STL:
  1176. case REG_SPDIF_STR:
  1177. case REG_SPDIF_STCSCH:
  1178. case REG_SPDIF_STCSCL:
  1179. case REG_SPDIF_STCSPH:
  1180. case REG_SPDIF_STCSPL:
  1181. case REG_SPDIF_STC:
  1182. case REG_SPDIF_STCCA_31_0:
  1183. case REG_SPDIF_STCCA_63_32:
  1184. case REG_SPDIF_STCCA_95_64:
  1185. case REG_SPDIF_STCCA_127_96:
  1186. case REG_SPDIF_STCCA_159_128:
  1187. case REG_SPDIF_STCCA_191_160:
  1188. return true;
  1189. default:
  1190. return false;
  1191. }
  1192. }
  1193. static const struct regmap_config fsl_spdif_regmap_config = {
  1194. .reg_bits = 32,
  1195. .reg_stride = 4,
  1196. .val_bits = 32,
  1197. .max_register = REG_SPDIF_STCCA_191_160,
  1198. .reg_defaults = fsl_spdif_reg_defaults,
  1199. .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
  1200. .readable_reg = fsl_spdif_readable_reg,
  1201. .volatile_reg = fsl_spdif_volatile_reg,
  1202. .writeable_reg = fsl_spdif_writeable_reg,
  1203. .cache_type = REGCACHE_FLAT,
  1204. };
  1205. static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
  1206. struct clk *clk, u64 savesub,
  1207. enum spdif_txrate index, bool round)
  1208. {
  1209. static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
  1210. 192000, };
  1211. bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
  1212. u64 rate_ideal, rate_actual, sub;
  1213. u32 arate;
  1214. u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
  1215. u8 txclk_df;
  1216. /* The sysclk has an extra divisor [2, 512] */
  1217. sysclk_dfmin = is_sysclk ? 2 : 1;
  1218. sysclk_dfmax = is_sysclk ? 512 : 1;
  1219. for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
  1220. for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
  1221. rate_ideal = rate[index] * txclk_df * 64ULL;
  1222. if (round)
  1223. rate_actual = clk_round_rate(clk, rate_ideal);
  1224. else
  1225. rate_actual = clk_get_rate(clk);
  1226. arate = rate_actual / 64;
  1227. arate /= txclk_df * sysclk_df;
  1228. if (arate == rate[index]) {
  1229. /* We are lucky */
  1230. savesub = 0;
  1231. spdif_priv->txclk_df[index] = txclk_df;
  1232. spdif_priv->sysclk_df[index] = sysclk_df;
  1233. spdif_priv->txrate[index] = arate;
  1234. goto out;
  1235. } else if (arate / rate[index] == 1) {
  1236. /* A little bigger than expect */
  1237. sub = (u64)(arate - rate[index]) * 100000;
  1238. do_div(sub, rate[index]);
  1239. if (sub >= savesub)
  1240. continue;
  1241. savesub = sub;
  1242. spdif_priv->txclk_df[index] = txclk_df;
  1243. spdif_priv->sysclk_df[index] = sysclk_df;
  1244. spdif_priv->txrate[index] = arate;
  1245. } else if (rate[index] / arate == 1) {
  1246. /* A little smaller than expect */
  1247. sub = (u64)(rate[index] - arate) * 100000;
  1248. do_div(sub, rate[index]);
  1249. if (sub >= savesub)
  1250. continue;
  1251. savesub = sub;
  1252. spdif_priv->txclk_df[index] = txclk_df;
  1253. spdif_priv->sysclk_df[index] = sysclk_df;
  1254. spdif_priv->txrate[index] = arate;
  1255. }
  1256. }
  1257. }
  1258. out:
  1259. return savesub;
  1260. }
  1261. static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
  1262. enum spdif_txrate index)
  1263. {
  1264. static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
  1265. 192000, };
  1266. struct platform_device *pdev = spdif_priv->pdev;
  1267. struct device *dev = &pdev->dev;
  1268. u64 savesub = 100000, ret;
  1269. struct clk *clk;
  1270. int i;
  1271. for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
  1272. clk = spdif_priv->txclk[i];
  1273. if (IS_ERR(clk)) {
  1274. dev_err(dev, "no rxtx%d clock in devicetree\n", i);
  1275. return PTR_ERR(clk);
  1276. }
  1277. if (!clk_get_rate(clk))
  1278. continue;
  1279. ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
  1280. fsl_spdif_can_set_clk_rate(spdif_priv, i));
  1281. if (savesub == ret)
  1282. continue;
  1283. savesub = ret;
  1284. spdif_priv->txclk_src[index] = i;
  1285. /* To quick catch a divisor, we allow a 0.1% deviation */
  1286. if (savesub < 100)
  1287. break;
  1288. }
  1289. dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
  1290. spdif_priv->txclk_src[index], rate[index]);
  1291. dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
  1292. spdif_priv->txclk_df[index], rate[index]);
  1293. if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))
  1294. dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
  1295. spdif_priv->sysclk_df[index], rate[index]);
  1296. dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
  1297. rate[index], spdif_priv->txrate[index]);
  1298. return 0;
  1299. }
  1300. static int fsl_spdif_probe(struct platform_device *pdev)
  1301. {
  1302. struct fsl_spdif_priv *spdif_priv;
  1303. struct spdif_mixer_control *ctrl;
  1304. struct resource *res;
  1305. void __iomem *regs;
  1306. int irq, ret, i;
  1307. char tmp[16];
  1308. spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
  1309. if (!spdif_priv)
  1310. return -ENOMEM;
  1311. spdif_priv->pdev = pdev;
  1312. spdif_priv->soc = of_device_get_match_data(&pdev->dev);
  1313. /* Initialize this copy of the CPU DAI driver structure */
  1314. memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
  1315. spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
  1316. spdif_priv->cpu_dai_drv.playback.formats =
  1317. spdif_priv->soc->tx_formats;
  1318. /* Get the addresses and IRQ */
  1319. regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  1320. if (IS_ERR(regs))
  1321. return PTR_ERR(regs);
  1322. spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
  1323. if (IS_ERR(spdif_priv->regmap)) {
  1324. dev_err(&pdev->dev, "regmap init failed\n");
  1325. return PTR_ERR(spdif_priv->regmap);
  1326. }
  1327. for (i = 0; i < spdif_priv->soc->interrupts; i++) {
  1328. irq = platform_get_irq(pdev, i);
  1329. if (irq < 0)
  1330. return irq;
  1331. ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
  1332. dev_name(&pdev->dev), spdif_priv);
  1333. if (ret) {
  1334. dev_err(&pdev->dev, "could not claim irq %u\n", irq);
  1335. return ret;
  1336. }
  1337. }
  1338. for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
  1339. sprintf(tmp, "rxtx%d", i);
  1340. spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);
  1341. if (IS_ERR(spdif_priv->txclk[i])) {
  1342. dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);
  1343. return PTR_ERR(spdif_priv->txclk[i]);
  1344. }
  1345. }
  1346. /* Get system clock for rx clock rate calculation */
  1347. spdif_priv->sysclk = spdif_priv->txclk[5];
  1348. if (IS_ERR(spdif_priv->sysclk)) {
  1349. dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
  1350. return PTR_ERR(spdif_priv->sysclk);
  1351. }
  1352. /* Get core clock for data register access via DMA */
  1353. spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
  1354. if (IS_ERR(spdif_priv->coreclk)) {
  1355. dev_err(&pdev->dev, "no core clock in devicetree\n");
  1356. return PTR_ERR(spdif_priv->coreclk);
  1357. }
  1358. spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
  1359. if (IS_ERR(spdif_priv->spbaclk))
  1360. dev_warn(&pdev->dev, "no spba clock in devicetree\n");
  1361. /* Select clock source for rx/tx clock */
  1362. spdif_priv->rxclk = spdif_priv->txclk[1];
  1363. if (IS_ERR(spdif_priv->rxclk)) {
  1364. dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
  1365. return PTR_ERR(spdif_priv->rxclk);
  1366. }
  1367. spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
  1368. fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk,
  1369. &spdif_priv->pll11k_clk);
  1370. /* Initial spinlock for control data */
  1371. ctrl = &spdif_priv->fsl_spdif_control;
  1372. spin_lock_init(&ctrl->ctl_lock);
  1373. /* Init tx channel status default value */
  1374. ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
  1375. IEC958_AES0_CON_EMPHASIS_5015;
  1376. ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
  1377. ctrl->ch_status[2] = 0x00;
  1378. ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
  1379. IEC958_AES3_CON_CLOCK_1000PPM;
  1380. spdif_priv->dpll_locked = false;
  1381. spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
  1382. spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
  1383. spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
  1384. spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
  1385. /* Register with ASoC */
  1386. dev_set_drvdata(&pdev->dev, spdif_priv);
  1387. pm_runtime_enable(&pdev->dev);
  1388. regcache_cache_only(spdif_priv->regmap, true);
  1389. /*
  1390. * Register platform component before registering cpu dai for there
  1391. * is not defer probe for platform component in snd_soc_add_pcm_runtime().
  1392. */
  1393. ret = imx_pcm_dma_init(pdev);
  1394. if (ret) {
  1395. dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
  1396. goto err_pm_disable;
  1397. }
  1398. ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
  1399. &spdif_priv->cpu_dai_drv, 1);
  1400. if (ret) {
  1401. dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
  1402. goto err_pm_disable;
  1403. }
  1404. return ret;
  1405. err_pm_disable:
  1406. pm_runtime_disable(&pdev->dev);
  1407. return ret;
  1408. }
  1409. static int fsl_spdif_remove(struct platform_device *pdev)
  1410. {
  1411. pm_runtime_disable(&pdev->dev);
  1412. return 0;
  1413. }
  1414. #ifdef CONFIG_PM
  1415. static int fsl_spdif_runtime_suspend(struct device *dev)
  1416. {
  1417. struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
  1418. int i;
  1419. /* Disable all the interrupts */
  1420. regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
  1421. regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
  1422. &spdif_priv->regcache_srpc);
  1423. regcache_cache_only(spdif_priv->regmap, true);
  1424. for (i = 0; i < STC_TXCLK_SRC_MAX; i++)
  1425. clk_disable_unprepare(spdif_priv->txclk[i]);
  1426. if (!IS_ERR(spdif_priv->spbaclk))
  1427. clk_disable_unprepare(spdif_priv->spbaclk);
  1428. clk_disable_unprepare(spdif_priv->coreclk);
  1429. return 0;
  1430. }
  1431. static int fsl_spdif_runtime_resume(struct device *dev)
  1432. {
  1433. struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
  1434. int ret;
  1435. int i;
  1436. ret = clk_prepare_enable(spdif_priv->coreclk);
  1437. if (ret) {
  1438. dev_err(dev, "failed to enable core clock\n");
  1439. return ret;
  1440. }
  1441. if (!IS_ERR(spdif_priv->spbaclk)) {
  1442. ret = clk_prepare_enable(spdif_priv->spbaclk);
  1443. if (ret) {
  1444. dev_err(dev, "failed to enable spba clock\n");
  1445. goto disable_core_clk;
  1446. }
  1447. }
  1448. for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
  1449. ret = clk_prepare_enable(spdif_priv->txclk[i]);
  1450. if (ret)
  1451. goto disable_tx_clk;
  1452. }
  1453. regcache_cache_only(spdif_priv->regmap, false);
  1454. regcache_mark_dirty(spdif_priv->regmap);
  1455. regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
  1456. SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
  1457. spdif_priv->regcache_srpc);
  1458. ret = regcache_sync(spdif_priv->regmap);
  1459. if (ret)
  1460. goto disable_tx_clk;
  1461. return 0;
  1462. disable_tx_clk:
  1463. for (i--; i >= 0; i--)
  1464. clk_disable_unprepare(spdif_priv->txclk[i]);
  1465. if (!IS_ERR(spdif_priv->spbaclk))
  1466. clk_disable_unprepare(spdif_priv->spbaclk);
  1467. disable_core_clk:
  1468. clk_disable_unprepare(spdif_priv->coreclk);
  1469. return ret;
  1470. }
  1471. #endif /* CONFIG_PM */
  1472. static const struct dev_pm_ops fsl_spdif_pm = {
  1473. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1474. pm_runtime_force_resume)
  1475. SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
  1476. NULL)
  1477. };
  1478. static const struct of_device_id fsl_spdif_dt_ids[] = {
  1479. { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
  1480. { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
  1481. { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
  1482. { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
  1483. { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
  1484. { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
  1485. {}
  1486. };
  1487. MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
  1488. static struct platform_driver fsl_spdif_driver = {
  1489. .driver = {
  1490. .name = "fsl-spdif-dai",
  1491. .of_match_table = fsl_spdif_dt_ids,
  1492. .pm = &fsl_spdif_pm,
  1493. },
  1494. .probe = fsl_spdif_probe,
  1495. .remove = fsl_spdif_remove,
  1496. };
  1497. module_platform_driver(fsl_spdif_driver);
  1498. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  1499. MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
  1500. MODULE_LICENSE("GPL v2");
  1501. MODULE_ALIAS("platform:fsl-spdif-dai");