fsl_micfil.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * PDM Microphone Interface for the NXP i.MX SoC
  4. * Copyright 2018 NXP
  5. */
  6. #ifndef _FSL_MICFIL_H
  7. #define _FSL_MICFIL_H
  8. /* MICFIL Register Map */
  9. #define REG_MICFIL_CTRL1 0x00
  10. #define REG_MICFIL_CTRL2 0x04
  11. #define REG_MICFIL_STAT 0x08
  12. #define REG_MICFIL_FIFO_CTRL 0x10
  13. #define REG_MICFIL_FIFO_STAT 0x14
  14. #define REG_MICFIL_DATACH0 0x24
  15. #define REG_MICFIL_DATACH1 0x28
  16. #define REG_MICFIL_DATACH2 0x2C
  17. #define REG_MICFIL_DATACH3 0x30
  18. #define REG_MICFIL_DATACH4 0x34
  19. #define REG_MICFIL_DATACH5 0x38
  20. #define REG_MICFIL_DATACH6 0x3C
  21. #define REG_MICFIL_DATACH7 0x40
  22. #define REG_MICFIL_DC_CTRL 0x64
  23. #define REG_MICFIL_OUT_CTRL 0x74
  24. #define REG_MICFIL_OUT_STAT 0x7C
  25. #define REG_MICFIL_VAD0_CTRL1 0x90
  26. #define REG_MICFIL_VAD0_CTRL2 0x94
  27. #define REG_MICFIL_VAD0_STAT 0x98
  28. #define REG_MICFIL_VAD0_SCONFIG 0x9C
  29. #define REG_MICFIL_VAD0_NCONFIG 0xA0
  30. #define REG_MICFIL_VAD0_NDATA 0xA4
  31. #define REG_MICFIL_VAD0_ZCD 0xA8
  32. /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
  33. #define MICFIL_CTRL1_MDIS BIT(31)
  34. #define MICFIL_CTRL1_DOZEN BIT(30)
  35. #define MICFIL_CTRL1_PDMIEN BIT(29)
  36. #define MICFIL_CTRL1_DBG BIT(28)
  37. #define MICFIL_CTRL1_SRES BIT(27)
  38. #define MICFIL_CTRL1_DBGE BIT(26)
  39. #define MICFIL_CTRL1_DISEL_DISABLE 0
  40. #define MICFIL_CTRL1_DISEL_DMA 1
  41. #define MICFIL_CTRL1_DISEL_IRQ 2
  42. #define MICFIL_CTRL1_DISEL GENMASK(25, 24)
  43. #define MICFIL_CTRL1_ERREN BIT(23)
  44. #define MICFIL_CTRL1_CHEN(ch) BIT(ch)
  45. /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
  46. #define MICFIL_CTRL2_QSEL_SHIFT 25
  47. #define MICFIL_CTRL2_QSEL GENMASK(27, 25)
  48. #define MICFIL_QSEL_MEDIUM_QUALITY 0
  49. #define MICFIL_QSEL_HIGH_QUALITY 1
  50. #define MICFIL_QSEL_LOW_QUALITY 7
  51. #define MICFIL_QSEL_VLOW0_QUALITY 6
  52. #define MICFIL_QSEL_VLOW1_QUALITY 5
  53. #define MICFIL_QSEL_VLOW2_QUALITY 4
  54. #define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
  55. #define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
  56. /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
  57. #define MICFIL_STAT_BSY_FIL BIT(31)
  58. #define MICFIL_STAT_FIR_RDY BIT(30)
  59. #define MICFIL_STAT_LOWFREQF BIT(29)
  60. #define MICFIL_STAT_CHXF(ch) BIT(ch)
  61. /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
  62. #define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
  63. /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
  64. #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
  65. #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
  66. /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
  67. #define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0)
  68. #define MICFIL_DC_CHX_SHIFT(ch) ((ch) << 1)
  69. #define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) << 1))
  70. #define MICFIL_DC_CUTOFF_21HZ 0
  71. #define MICFIL_DC_CUTOFF_83HZ 1
  72. #define MICFIL_DC_CUTOFF_152Hz 2
  73. #define MICFIL_DC_BYPASS 3
  74. /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
  75. #define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
  76. #define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)
  77. #define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)
  78. #define MICFIL_VAD0_CTRL1_ST10 BIT(4)
  79. #define MICFIL_VAD0_CTRL1_ERIE BIT(3)
  80. #define MICFIL_VAD0_CTRL1_IE BIT(2)
  81. #define MICFIL_VAD0_CTRL1_RST BIT(1)
  82. #define MICFIL_VAD0_CTRL1_EN BIT(0)
  83. /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
  84. #define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
  85. #define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
  86. #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
  87. #define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
  88. #define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
  89. #define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
  90. /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
  91. #define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
  92. #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
  93. #define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
  94. /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
  95. #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
  96. #define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
  97. #define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
  98. #define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
  99. #define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
  100. #define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
  101. /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
  102. #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
  103. #define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)
  104. #define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
  105. #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
  106. #define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
  107. /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
  108. #define MICFIL_VAD0_STAT_INITF BIT(31)
  109. #define MICFIL_VAD0_STAT_INSATF BIT(16)
  110. #define MICFIL_VAD0_STAT_EF BIT(15)
  111. #define MICFIL_VAD0_STAT_IF BIT(0)
  112. /* MICFIL Output Control Register */
  113. #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
  114. /* Constants */
  115. #define MICFIL_OUTPUT_CHANNELS 8
  116. #define MICFIL_FIFO_NUM 8
  117. #define FIFO_PTRWID 3
  118. #define FIFO_LEN BIT(FIFO_PTRWID)
  119. #define MICFIL_IRQ_LINES 2
  120. #define MICFIL_MAX_RETRY 25
  121. #define MICFIL_SLEEP_MIN 90000 /* in us */
  122. #define MICFIL_SLEEP_MAX 100000 /* in us */
  123. #define MICFIL_DMA_MAXBURST_RX 6
  124. #endif /* _FSL_MICFIL_H */