fsl_micfil.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright 2018 NXP
  3. #include <linux/bitfield.h>
  4. #include <linux/clk.h>
  5. #include <linux/device.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/kobject.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regmap.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/types.h>
  18. #include <linux/dma/imx-dma.h>
  19. #include <sound/dmaengine_pcm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/soc.h>
  22. #include <sound/tlv.h>
  23. #include <sound/core.h>
  24. #include "fsl_micfil.h"
  25. #include "fsl_utils.h"
  26. #define MICFIL_OSR_DEFAULT 16
  27. enum quality {
  28. QUALITY_HIGH,
  29. QUALITY_MEDIUM,
  30. QUALITY_LOW,
  31. QUALITY_VLOW0,
  32. QUALITY_VLOW1,
  33. QUALITY_VLOW2,
  34. };
  35. struct fsl_micfil {
  36. struct platform_device *pdev;
  37. struct regmap *regmap;
  38. const struct fsl_micfil_soc_data *soc;
  39. struct clk *busclk;
  40. struct clk *mclk;
  41. struct clk *pll8k_clk;
  42. struct clk *pll11k_clk;
  43. struct snd_dmaengine_dai_dma_data dma_params_rx;
  44. struct sdma_peripheral_config sdmacfg;
  45. unsigned int dataline;
  46. char name[32];
  47. int irq[MICFIL_IRQ_LINES];
  48. enum quality quality;
  49. int dc_remover;
  50. };
  51. struct fsl_micfil_soc_data {
  52. unsigned int fifos;
  53. unsigned int fifo_depth;
  54. unsigned int dataline;
  55. bool imx;
  56. u64 formats;
  57. };
  58. static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
  59. .imx = true,
  60. .fifos = 8,
  61. .fifo_depth = 8,
  62. .dataline = 0xf,
  63. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  64. };
  65. static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
  66. .imx = true,
  67. .fifos = 8,
  68. .fifo_depth = 32,
  69. .dataline = 0xf,
  70. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  71. };
  72. static const struct of_device_id fsl_micfil_dt_ids[] = {
  73. { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
  74. { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
  75. {}
  76. };
  77. MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
  78. static const char * const micfil_quality_select_texts[] = {
  79. [QUALITY_HIGH] = "High",
  80. [QUALITY_MEDIUM] = "Medium",
  81. [QUALITY_LOW] = "Low",
  82. [QUALITY_VLOW0] = "VLow0",
  83. [QUALITY_VLOW1] = "Vlow1",
  84. [QUALITY_VLOW2] = "Vlow2",
  85. };
  86. static const struct soc_enum fsl_micfil_quality_enum =
  87. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
  88. micfil_quality_select_texts);
  89. static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
  90. static int micfil_set_quality(struct fsl_micfil *micfil)
  91. {
  92. u32 qsel;
  93. switch (micfil->quality) {
  94. case QUALITY_HIGH:
  95. qsel = MICFIL_QSEL_HIGH_QUALITY;
  96. break;
  97. case QUALITY_MEDIUM:
  98. qsel = MICFIL_QSEL_MEDIUM_QUALITY;
  99. break;
  100. case QUALITY_LOW:
  101. qsel = MICFIL_QSEL_LOW_QUALITY;
  102. break;
  103. case QUALITY_VLOW0:
  104. qsel = MICFIL_QSEL_VLOW0_QUALITY;
  105. break;
  106. case QUALITY_VLOW1:
  107. qsel = MICFIL_QSEL_VLOW1_QUALITY;
  108. break;
  109. case QUALITY_VLOW2:
  110. qsel = MICFIL_QSEL_VLOW2_QUALITY;
  111. break;
  112. }
  113. return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
  114. MICFIL_CTRL2_QSEL,
  115. FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
  116. }
  117. static int micfil_quality_get(struct snd_kcontrol *kcontrol,
  118. struct snd_ctl_elem_value *ucontrol)
  119. {
  120. struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
  121. struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
  122. ucontrol->value.integer.value[0] = micfil->quality;
  123. return 0;
  124. }
  125. static int micfil_quality_set(struct snd_kcontrol *kcontrol,
  126. struct snd_ctl_elem_value *ucontrol)
  127. {
  128. struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
  129. struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
  130. micfil->quality = ucontrol->value.integer.value[0];
  131. return micfil_set_quality(micfil);
  132. }
  133. static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
  134. SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
  135. MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
  136. SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
  137. MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
  138. SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
  139. MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
  140. SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
  141. MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
  142. SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
  143. MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
  144. SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
  145. MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
  146. SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
  147. MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
  148. SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
  149. MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
  150. SOC_ENUM_EXT("MICFIL Quality Select",
  151. fsl_micfil_quality_enum,
  152. micfil_quality_get, micfil_quality_set),
  153. };
  154. /* The SRES is a self-negated bit which provides the CPU with the
  155. * capability to initialize the PDM Interface module through the
  156. * slave-bus interface. This bit always reads as zero, and this
  157. * bit is only effective when MDIS is cleared
  158. */
  159. static int fsl_micfil_reset(struct device *dev)
  160. {
  161. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  162. int ret;
  163. ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
  164. MICFIL_CTRL1_MDIS);
  165. if (ret)
  166. return ret;
  167. ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
  168. MICFIL_CTRL1_SRES);
  169. if (ret)
  170. return ret;
  171. /*
  172. * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
  173. * as non-volatile register, so SRES still remain in regmap
  174. * cache after set, that every update of REG_MICFIL_CTRL1,
  175. * software reset happens. so clear it explicitly.
  176. */
  177. ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
  178. MICFIL_CTRL1_SRES);
  179. if (ret)
  180. return ret;
  181. /*
  182. * Set SRES should clear CHnF flags, But even add delay here
  183. * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
  184. */
  185. ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
  186. if (ret)
  187. return ret;
  188. return 0;
  189. }
  190. static int fsl_micfil_startup(struct snd_pcm_substream *substream,
  191. struct snd_soc_dai *dai)
  192. {
  193. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  194. if (!micfil) {
  195. dev_err(dai->dev, "micfil dai priv_data not set\n");
  196. return -EINVAL;
  197. }
  198. return 0;
  199. }
  200. static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
  201. struct snd_soc_dai *dai)
  202. {
  203. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  204. struct device *dev = &micfil->pdev->dev;
  205. int ret;
  206. switch (cmd) {
  207. case SNDRV_PCM_TRIGGER_START:
  208. case SNDRV_PCM_TRIGGER_RESUME:
  209. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  210. ret = fsl_micfil_reset(dev);
  211. if (ret) {
  212. dev_err(dev, "failed to soft reset\n");
  213. return ret;
  214. }
  215. /* DMA Interrupt Selection - DISEL bits
  216. * 00 - DMA and IRQ disabled
  217. * 01 - DMA req enabled
  218. * 10 - IRQ enabled
  219. * 11 - reserved
  220. */
  221. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  222. MICFIL_CTRL1_DISEL,
  223. FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
  224. if (ret)
  225. return ret;
  226. /* Enable the module */
  227. ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
  228. MICFIL_CTRL1_PDMIEN);
  229. if (ret)
  230. return ret;
  231. break;
  232. case SNDRV_PCM_TRIGGER_STOP:
  233. case SNDRV_PCM_TRIGGER_SUSPEND:
  234. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  235. /* Disable the module */
  236. ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
  237. MICFIL_CTRL1_PDMIEN);
  238. if (ret)
  239. return ret;
  240. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  241. MICFIL_CTRL1_DISEL,
  242. FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
  243. if (ret)
  244. return ret;
  245. break;
  246. default:
  247. return -EINVAL;
  248. }
  249. return 0;
  250. }
  251. static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
  252. {
  253. struct device *dev = &micfil->pdev->dev;
  254. u64 ratio = sample_rate;
  255. struct clk *clk;
  256. int ret;
  257. /* Get root clock */
  258. clk = micfil->mclk;
  259. /* Disable clock first, for it was enabled by pm_runtime */
  260. clk_disable_unprepare(clk);
  261. fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
  262. micfil->pll11k_clk, ratio);
  263. ret = clk_prepare_enable(clk);
  264. if (ret)
  265. return ret;
  266. return 0;
  267. }
  268. static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
  269. struct snd_pcm_hw_params *params,
  270. struct snd_soc_dai *dai)
  271. {
  272. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  273. unsigned int channels = params_channels(params);
  274. unsigned int rate = params_rate(params);
  275. int clk_div = 8;
  276. int osr = MICFIL_OSR_DEFAULT;
  277. int ret;
  278. /* 1. Disable the module */
  279. ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
  280. MICFIL_CTRL1_PDMIEN);
  281. if (ret)
  282. return ret;
  283. /* enable channels */
  284. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  285. 0xFF, ((1 << channels) - 1));
  286. if (ret)
  287. return ret;
  288. ret = fsl_micfil_reparent_rootclk(micfil, rate);
  289. if (ret)
  290. return ret;
  291. ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
  292. if (ret)
  293. return ret;
  294. ret = micfil_set_quality(micfil);
  295. if (ret)
  296. return ret;
  297. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
  298. MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
  299. FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
  300. FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
  301. micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
  302. micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
  303. micfil->sdmacfg.n_fifos_src = channels;
  304. micfil->sdmacfg.sw_done = true;
  305. micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
  306. return 0;
  307. }
  308. static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
  309. .startup = fsl_micfil_startup,
  310. .trigger = fsl_micfil_trigger,
  311. .hw_params = fsl_micfil_hw_params,
  312. };
  313. static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
  314. {
  315. struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
  316. struct device *dev = cpu_dai->dev;
  317. unsigned int val = 0;
  318. int ret, i;
  319. micfil->quality = QUALITY_VLOW0;
  320. /* set default gain to 2 */
  321. regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
  322. /* set DC Remover in bypass mode*/
  323. for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
  324. val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
  325. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
  326. MICFIL_DC_CTRL_CONFIG, val);
  327. if (ret) {
  328. dev_err(dev, "failed to set DC Remover mode bits\n");
  329. return ret;
  330. }
  331. micfil->dc_remover = MICFIL_DC_BYPASS;
  332. snd_soc_dai_init_dma_data(cpu_dai, NULL,
  333. &micfil->dma_params_rx);
  334. /* FIFO Watermark Control - FIFOWMK*/
  335. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
  336. MICFIL_FIFO_CTRL_FIFOWMK,
  337. FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
  338. if (ret)
  339. return ret;
  340. return 0;
  341. }
  342. static struct snd_soc_dai_driver fsl_micfil_dai = {
  343. .probe = fsl_micfil_dai_probe,
  344. .capture = {
  345. .stream_name = "CPU-Capture",
  346. .channels_min = 1,
  347. .channels_max = 8,
  348. .rates = SNDRV_PCM_RATE_8000_48000,
  349. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  350. },
  351. .ops = &fsl_micfil_dai_ops,
  352. };
  353. static const struct snd_soc_component_driver fsl_micfil_component = {
  354. .name = "fsl-micfil-dai",
  355. .controls = fsl_micfil_snd_controls,
  356. .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
  357. .legacy_dai_naming = 1,
  358. };
  359. /* REGMAP */
  360. static const struct reg_default fsl_micfil_reg_defaults[] = {
  361. {REG_MICFIL_CTRL1, 0x00000000},
  362. {REG_MICFIL_CTRL2, 0x00000000},
  363. {REG_MICFIL_STAT, 0x00000000},
  364. {REG_MICFIL_FIFO_CTRL, 0x00000007},
  365. {REG_MICFIL_FIFO_STAT, 0x00000000},
  366. {REG_MICFIL_DATACH0, 0x00000000},
  367. {REG_MICFIL_DATACH1, 0x00000000},
  368. {REG_MICFIL_DATACH2, 0x00000000},
  369. {REG_MICFIL_DATACH3, 0x00000000},
  370. {REG_MICFIL_DATACH4, 0x00000000},
  371. {REG_MICFIL_DATACH5, 0x00000000},
  372. {REG_MICFIL_DATACH6, 0x00000000},
  373. {REG_MICFIL_DATACH7, 0x00000000},
  374. {REG_MICFIL_DC_CTRL, 0x00000000},
  375. {REG_MICFIL_OUT_CTRL, 0x00000000},
  376. {REG_MICFIL_OUT_STAT, 0x00000000},
  377. {REG_MICFIL_VAD0_CTRL1, 0x00000000},
  378. {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
  379. {REG_MICFIL_VAD0_STAT, 0x00000000},
  380. {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
  381. {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
  382. {REG_MICFIL_VAD0_NDATA, 0x00000000},
  383. {REG_MICFIL_VAD0_ZCD, 0x00000004},
  384. };
  385. static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
  386. {
  387. switch (reg) {
  388. case REG_MICFIL_CTRL1:
  389. case REG_MICFIL_CTRL2:
  390. case REG_MICFIL_STAT:
  391. case REG_MICFIL_FIFO_CTRL:
  392. case REG_MICFIL_FIFO_STAT:
  393. case REG_MICFIL_DATACH0:
  394. case REG_MICFIL_DATACH1:
  395. case REG_MICFIL_DATACH2:
  396. case REG_MICFIL_DATACH3:
  397. case REG_MICFIL_DATACH4:
  398. case REG_MICFIL_DATACH5:
  399. case REG_MICFIL_DATACH6:
  400. case REG_MICFIL_DATACH7:
  401. case REG_MICFIL_DC_CTRL:
  402. case REG_MICFIL_OUT_CTRL:
  403. case REG_MICFIL_OUT_STAT:
  404. case REG_MICFIL_VAD0_CTRL1:
  405. case REG_MICFIL_VAD0_CTRL2:
  406. case REG_MICFIL_VAD0_STAT:
  407. case REG_MICFIL_VAD0_SCONFIG:
  408. case REG_MICFIL_VAD0_NCONFIG:
  409. case REG_MICFIL_VAD0_NDATA:
  410. case REG_MICFIL_VAD0_ZCD:
  411. return true;
  412. default:
  413. return false;
  414. }
  415. }
  416. static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
  417. {
  418. switch (reg) {
  419. case REG_MICFIL_CTRL1:
  420. case REG_MICFIL_CTRL2:
  421. case REG_MICFIL_STAT: /* Write 1 to Clear */
  422. case REG_MICFIL_FIFO_CTRL:
  423. case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
  424. case REG_MICFIL_DC_CTRL:
  425. case REG_MICFIL_OUT_CTRL:
  426. case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
  427. case REG_MICFIL_VAD0_CTRL1:
  428. case REG_MICFIL_VAD0_CTRL2:
  429. case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
  430. case REG_MICFIL_VAD0_SCONFIG:
  431. case REG_MICFIL_VAD0_NCONFIG:
  432. case REG_MICFIL_VAD0_ZCD:
  433. return true;
  434. default:
  435. return false;
  436. }
  437. }
  438. static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
  439. {
  440. switch (reg) {
  441. case REG_MICFIL_STAT:
  442. case REG_MICFIL_DATACH0:
  443. case REG_MICFIL_DATACH1:
  444. case REG_MICFIL_DATACH2:
  445. case REG_MICFIL_DATACH3:
  446. case REG_MICFIL_DATACH4:
  447. case REG_MICFIL_DATACH5:
  448. case REG_MICFIL_DATACH6:
  449. case REG_MICFIL_DATACH7:
  450. case REG_MICFIL_VAD0_STAT:
  451. case REG_MICFIL_VAD0_NDATA:
  452. return true;
  453. default:
  454. return false;
  455. }
  456. }
  457. static const struct regmap_config fsl_micfil_regmap_config = {
  458. .reg_bits = 32,
  459. .reg_stride = 4,
  460. .val_bits = 32,
  461. .max_register = REG_MICFIL_VAD0_ZCD,
  462. .reg_defaults = fsl_micfil_reg_defaults,
  463. .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
  464. .readable_reg = fsl_micfil_readable_reg,
  465. .volatile_reg = fsl_micfil_volatile_reg,
  466. .writeable_reg = fsl_micfil_writeable_reg,
  467. .cache_type = REGCACHE_RBTREE,
  468. };
  469. /* END OF REGMAP */
  470. static irqreturn_t micfil_isr(int irq, void *devid)
  471. {
  472. struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
  473. struct platform_device *pdev = micfil->pdev;
  474. u32 stat_reg;
  475. u32 fifo_stat_reg;
  476. u32 ctrl1_reg;
  477. bool dma_enabled;
  478. int i;
  479. regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
  480. regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
  481. regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
  482. dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
  483. /* Channel 0-7 Output Data Flags */
  484. for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
  485. if (stat_reg & MICFIL_STAT_CHXF(i))
  486. dev_dbg(&pdev->dev,
  487. "Data available in Data Channel %d\n", i);
  488. /* if DMA is not enabled, field must be written with 1
  489. * to clear
  490. */
  491. if (!dma_enabled)
  492. regmap_write_bits(micfil->regmap,
  493. REG_MICFIL_STAT,
  494. MICFIL_STAT_CHXF(i),
  495. 1);
  496. }
  497. for (i = 0; i < MICFIL_FIFO_NUM; i++) {
  498. if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
  499. dev_dbg(&pdev->dev,
  500. "FIFO Overflow Exception flag for channel %d\n",
  501. i);
  502. if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
  503. dev_dbg(&pdev->dev,
  504. "FIFO Underflow Exception flag for channel %d\n",
  505. i);
  506. }
  507. return IRQ_HANDLED;
  508. }
  509. static irqreturn_t micfil_err_isr(int irq, void *devid)
  510. {
  511. struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
  512. struct platform_device *pdev = micfil->pdev;
  513. u32 stat_reg;
  514. regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
  515. if (stat_reg & MICFIL_STAT_BSY_FIL)
  516. dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
  517. if (stat_reg & MICFIL_STAT_FIR_RDY)
  518. dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
  519. if (stat_reg & MICFIL_STAT_LOWFREQF) {
  520. dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
  521. regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
  522. MICFIL_STAT_LOWFREQF, 1);
  523. }
  524. return IRQ_HANDLED;
  525. }
  526. static int fsl_micfil_probe(struct platform_device *pdev)
  527. {
  528. struct device_node *np = pdev->dev.of_node;
  529. struct fsl_micfil *micfil;
  530. struct resource *res;
  531. void __iomem *regs;
  532. int ret, i;
  533. micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
  534. if (!micfil)
  535. return -ENOMEM;
  536. micfil->pdev = pdev;
  537. strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
  538. micfil->soc = of_device_get_match_data(&pdev->dev);
  539. /* ipg_clk is used to control the registers
  540. * ipg_clk_app is used to operate the filter
  541. */
  542. micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
  543. if (IS_ERR(micfil->mclk)) {
  544. dev_err(&pdev->dev, "failed to get core clock: %ld\n",
  545. PTR_ERR(micfil->mclk));
  546. return PTR_ERR(micfil->mclk);
  547. }
  548. micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
  549. if (IS_ERR(micfil->busclk)) {
  550. dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
  551. PTR_ERR(micfil->busclk));
  552. return PTR_ERR(micfil->busclk);
  553. }
  554. fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
  555. &micfil->pll11k_clk);
  556. /* init regmap */
  557. regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  558. if (IS_ERR(regs))
  559. return PTR_ERR(regs);
  560. micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
  561. regs,
  562. &fsl_micfil_regmap_config);
  563. if (IS_ERR(micfil->regmap)) {
  564. dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
  565. PTR_ERR(micfil->regmap));
  566. return PTR_ERR(micfil->regmap);
  567. }
  568. /* dataline mask for RX */
  569. ret = of_property_read_u32_index(np,
  570. "fsl,dataline",
  571. 0,
  572. &micfil->dataline);
  573. if (ret)
  574. micfil->dataline = 1;
  575. if (micfil->dataline & ~micfil->soc->dataline) {
  576. dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
  577. micfil->soc->dataline);
  578. return -EINVAL;
  579. }
  580. /* get IRQs */
  581. for (i = 0; i < MICFIL_IRQ_LINES; i++) {
  582. micfil->irq[i] = platform_get_irq(pdev, i);
  583. if (micfil->irq[i] < 0)
  584. return micfil->irq[i];
  585. }
  586. /* Digital Microphone interface interrupt */
  587. ret = devm_request_irq(&pdev->dev, micfil->irq[0],
  588. micfil_isr, IRQF_SHARED,
  589. micfil->name, micfil);
  590. if (ret) {
  591. dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
  592. micfil->irq[0]);
  593. return ret;
  594. }
  595. /* Digital Microphone interface error interrupt */
  596. ret = devm_request_irq(&pdev->dev, micfil->irq[1],
  597. micfil_err_isr, IRQF_SHARED,
  598. micfil->name, micfil);
  599. if (ret) {
  600. dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
  601. micfil->irq[1]);
  602. return ret;
  603. }
  604. micfil->dma_params_rx.chan_name = "rx";
  605. micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
  606. micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
  607. platform_set_drvdata(pdev, micfil);
  608. pm_runtime_enable(&pdev->dev);
  609. regcache_cache_only(micfil->regmap, true);
  610. /*
  611. * Register platform component before registering cpu dai for there
  612. * is not defer probe for platform component in snd_soc_add_pcm_runtime().
  613. */
  614. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  615. if (ret) {
  616. dev_err(&pdev->dev, "failed to pcm register\n");
  617. goto err_pm_disable;
  618. }
  619. fsl_micfil_dai.capture.formats = micfil->soc->formats;
  620. ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
  621. &fsl_micfil_dai, 1);
  622. if (ret) {
  623. dev_err(&pdev->dev, "failed to register component %s\n",
  624. fsl_micfil_component.name);
  625. goto err_pm_disable;
  626. }
  627. return ret;
  628. err_pm_disable:
  629. pm_runtime_disable(&pdev->dev);
  630. return ret;
  631. }
  632. static void fsl_micfil_remove(struct platform_device *pdev)
  633. {
  634. pm_runtime_disable(&pdev->dev);
  635. }
  636. static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
  637. {
  638. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  639. regcache_cache_only(micfil->regmap, true);
  640. clk_disable_unprepare(micfil->mclk);
  641. clk_disable_unprepare(micfil->busclk);
  642. return 0;
  643. }
  644. static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
  645. {
  646. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  647. int ret;
  648. ret = clk_prepare_enable(micfil->busclk);
  649. if (ret < 0)
  650. return ret;
  651. ret = clk_prepare_enable(micfil->mclk);
  652. if (ret < 0) {
  653. clk_disable_unprepare(micfil->busclk);
  654. return ret;
  655. }
  656. regcache_cache_only(micfil->regmap, false);
  657. regcache_mark_dirty(micfil->regmap);
  658. regcache_sync(micfil->regmap);
  659. return 0;
  660. }
  661. static int __maybe_unused fsl_micfil_suspend(struct device *dev)
  662. {
  663. pm_runtime_force_suspend(dev);
  664. return 0;
  665. }
  666. static int __maybe_unused fsl_micfil_resume(struct device *dev)
  667. {
  668. pm_runtime_force_resume(dev);
  669. return 0;
  670. }
  671. static const struct dev_pm_ops fsl_micfil_pm_ops = {
  672. SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
  673. fsl_micfil_runtime_resume,
  674. NULL)
  675. SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
  676. fsl_micfil_resume)
  677. };
  678. static struct platform_driver fsl_micfil_driver = {
  679. .probe = fsl_micfil_probe,
  680. .remove_new = fsl_micfil_remove,
  681. .driver = {
  682. .name = "fsl-micfil-dai",
  683. .pm = &fsl_micfil_pm_ops,
  684. .of_match_table = fsl_micfil_dt_ids,
  685. },
  686. };
  687. module_platform_driver(fsl_micfil_driver);
  688. MODULE_AUTHOR("Cosmin-Gabriel Samoila <[email protected]>");
  689. MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
  690. MODULE_LICENSE("GPL v2");