fsl_easrc.c 58 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright 2019 NXP
  3. #include <linux/atomic.h>
  4. #include <linux/clk.h>
  5. #include <linux/device.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/firmware.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kobject.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/miscdevice.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <linux/sched/signal.h>
  20. #include <linux/sysfs.h>
  21. #include <linux/types.h>
  22. #include <linux/gcd.h>
  23. #include <sound/dmaengine_pcm.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/tlv.h>
  28. #include <sound/core.h>
  29. #include "fsl_easrc.h"
  30. #include "imx-pcm.h"
  31. #define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  32. SNDRV_PCM_FMTBIT_U16_LE | \
  33. SNDRV_PCM_FMTBIT_S24_LE | \
  34. SNDRV_PCM_FMTBIT_S24_3LE | \
  35. SNDRV_PCM_FMTBIT_U24_LE | \
  36. SNDRV_PCM_FMTBIT_U24_3LE | \
  37. SNDRV_PCM_FMTBIT_S32_LE | \
  38. SNDRV_PCM_FMTBIT_U32_LE | \
  39. SNDRV_PCM_FMTBIT_S20_3LE | \
  40. SNDRV_PCM_FMTBIT_U20_3LE | \
  41. SNDRV_PCM_FMTBIT_FLOAT_LE)
  42. static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
  43. struct snd_ctl_elem_value *ucontrol)
  44. {
  45. struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
  46. struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
  47. struct fsl_easrc_priv *easrc_priv = easrc->private;
  48. struct soc_mreg_control *mc =
  49. (struct soc_mreg_control *)kcontrol->private_value;
  50. unsigned int regval = ucontrol->value.integer.value[0];
  51. easrc_priv->bps_iec958[mc->regbase] = regval;
  52. return 0;
  53. }
  54. static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
  55. struct snd_ctl_elem_value *ucontrol)
  56. {
  57. struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
  58. struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
  59. struct fsl_easrc_priv *easrc_priv = easrc->private;
  60. struct soc_mreg_control *mc =
  61. (struct soc_mreg_control *)kcontrol->private_value;
  62. ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase];
  63. return 0;
  64. }
  65. static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
  66. struct snd_ctl_elem_value *ucontrol)
  67. {
  68. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  69. struct soc_mreg_control *mc =
  70. (struct soc_mreg_control *)kcontrol->private_value;
  71. unsigned int regval;
  72. regval = snd_soc_component_read(component, mc->regbase);
  73. ucontrol->value.integer.value[0] = regval;
  74. return 0;
  75. }
  76. static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
  77. struct snd_ctl_elem_value *ucontrol)
  78. {
  79. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  80. struct soc_mreg_control *mc =
  81. (struct soc_mreg_control *)kcontrol->private_value;
  82. unsigned int regval = ucontrol->value.integer.value[0];
  83. int ret;
  84. ret = snd_soc_component_write(component, mc->regbase, regval);
  85. if (ret < 0)
  86. return ret;
  87. return 0;
  88. }
  89. #define SOC_SINGLE_REG_RW(xname, xreg) \
  90. { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
  91. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
  92. .info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
  93. .put = fsl_easrc_set_reg, \
  94. .private_value = (unsigned long)&(struct soc_mreg_control) \
  95. { .regbase = xreg, .regcount = 1, .nbits = 32, \
  96. .invert = 0, .min = 0, .max = 0xffffffff, } }
  97. #define SOC_SINGLE_VAL_RW(xname, xreg) \
  98. { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
  99. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
  100. .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \
  101. .put = fsl_easrc_iec958_put_bits, \
  102. .private_value = (unsigned long)&(struct soc_mreg_control) \
  103. { .regbase = xreg, .regcount = 1, .nbits = 32, \
  104. .invert = 0, .min = 0, .max = 2, } }
  105. static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
  106. SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0),
  107. SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0),
  108. SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0),
  109. SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0),
  110. SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0),
  111. SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0),
  112. SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0),
  113. SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0),
  114. SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0),
  115. SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1),
  116. SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
  117. SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
  118. SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
  119. SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
  120. SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
  121. SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
  122. SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
  123. SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
  124. SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
  125. SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
  126. SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
  127. SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
  128. SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
  129. SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
  130. SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
  131. SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
  132. SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
  133. SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
  134. SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
  135. SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
  136. SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
  137. SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
  138. SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
  139. SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
  140. SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
  141. SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
  142. };
  143. /*
  144. * fsl_easrc_set_rs_ratio
  145. *
  146. * According to the resample taps, calculate the resample ratio
  147. * ratio = in_rate / out_rate
  148. */
  149. static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx)
  150. {
  151. struct fsl_asrc *easrc = ctx->asrc;
  152. struct fsl_easrc_priv *easrc_priv = easrc->private;
  153. struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
  154. unsigned int in_rate = ctx_priv->in_params.norm_rate;
  155. unsigned int out_rate = ctx_priv->out_params.norm_rate;
  156. unsigned int frac_bits;
  157. u64 val;
  158. u32 *r;
  159. switch (easrc_priv->rs_num_taps) {
  160. case EASRC_RS_32_TAPS:
  161. /* integer bits = 5; */
  162. frac_bits = 39;
  163. break;
  164. case EASRC_RS_64_TAPS:
  165. /* integer bits = 6; */
  166. frac_bits = 38;
  167. break;
  168. case EASRC_RS_128_TAPS:
  169. /* integer bits = 7; */
  170. frac_bits = 37;
  171. break;
  172. default:
  173. return -EINVAL;
  174. }
  175. val = (u64)in_rate << frac_bits;
  176. do_div(val, out_rate);
  177. r = (uint32_t *)&val;
  178. if (r[1] & 0xFFFFF000) {
  179. dev_err(&easrc->pdev->dev, "ratio exceed range\n");
  180. return -EINVAL;
  181. }
  182. regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
  183. EASRC_RRL_RS_RL(r[0]));
  184. regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
  185. EASRC_RRH_RS_RH(r[1]));
  186. return 0;
  187. }
  188. /* Normalize input and output sample rates */
  189. static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx)
  190. {
  191. struct fsl_easrc_ctx_priv *ctx_priv;
  192. int a, b;
  193. if (!ctx)
  194. return;
  195. ctx_priv = ctx->private;
  196. a = ctx_priv->in_params.sample_rate;
  197. b = ctx_priv->out_params.sample_rate;
  198. a = gcd(a, b);
  199. /* Divide by gcd to normalize the rate */
  200. ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a;
  201. ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a;
  202. }
  203. /* Resets the pointer of the coeff memory pointers */
  204. static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
  205. unsigned int ctx_id, int mem_type)
  206. {
  207. struct device *dev;
  208. u32 reg, mask, val;
  209. if (!easrc)
  210. return -ENODEV;
  211. dev = &easrc->pdev->dev;
  212. switch (mem_type) {
  213. case EASRC_PF_COEFF_MEM:
  214. /* This resets the prefilter memory pointer addr */
  215. if (ctx_id >= EASRC_CTX_MAX_NUM) {
  216. dev_err(dev, "Invalid context id[%d]\n", ctx_id);
  217. return -EINVAL;
  218. }
  219. reg = REG_EASRC_CCE1(ctx_id);
  220. mask = EASRC_CCE1_COEF_MEM_RST_MASK;
  221. val = EASRC_CCE1_COEF_MEM_RST;
  222. break;
  223. case EASRC_RS_COEFF_MEM:
  224. /* This resets the resampling memory pointer addr */
  225. reg = REG_EASRC_CRCC;
  226. mask = EASRC_CRCC_RS_CPR_MASK;
  227. val = EASRC_CRCC_RS_CPR;
  228. break;
  229. default:
  230. dev_err(dev, "Unknown memory type\n");
  231. return -EINVAL;
  232. }
  233. /*
  234. * To reset the write pointer back to zero, the register field
  235. * ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from
  236. * 0x0 to 0x1 to 0x0.
  237. */
  238. regmap_update_bits(easrc->regmap, reg, mask, 0);
  239. regmap_update_bits(easrc->regmap, reg, mask, val);
  240. regmap_update_bits(easrc->regmap, reg, mask, 0);
  241. return 0;
  242. }
  243. static inline uint32_t bits_taps_to_val(unsigned int t)
  244. {
  245. switch (t) {
  246. case EASRC_RS_32_TAPS:
  247. return 32;
  248. case EASRC_RS_64_TAPS:
  249. return 64;
  250. case EASRC_RS_128_TAPS:
  251. return 128;
  252. }
  253. return 0;
  254. }
  255. static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
  256. {
  257. struct device *dev = &easrc->pdev->dev;
  258. struct fsl_easrc_priv *easrc_priv = easrc->private;
  259. struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr;
  260. struct interp_params *interp = easrc_priv->interp;
  261. struct interp_params *selected_interp = NULL;
  262. unsigned int num_coeff;
  263. unsigned int i;
  264. u64 *coef;
  265. u32 *r;
  266. int ret;
  267. if (!hdr) {
  268. dev_err(dev, "firmware not loaded!\n");
  269. return -ENODEV;
  270. }
  271. for (i = 0; i < hdr->interp_scen; i++) {
  272. if ((interp[i].num_taps - 1) !=
  273. bits_taps_to_val(easrc_priv->rs_num_taps))
  274. continue;
  275. coef = interp[i].coeff;
  276. selected_interp = &interp[i];
  277. dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n",
  278. selected_interp->num_taps,
  279. selected_interp->num_phases);
  280. break;
  281. }
  282. if (!selected_interp) {
  283. dev_err(dev, "failed to get interpreter configuration\n");
  284. return -EINVAL;
  285. }
  286. /*
  287. * RS_LOW - first half of center tap of the sinc function
  288. * RS_HIGH - second half of center tap of the sinc function
  289. * This is due to the fact the resampling function must be
  290. * symetrical - i.e. odd number of taps
  291. */
  292. r = (uint32_t *)&selected_interp->center_tap;
  293. regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
  294. regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
  295. /*
  296. * Write Number of Resampling Coefficient Taps
  297. * 00b - 32-Tap Resampling Filter
  298. * 01b - 64-Tap Resampling Filter
  299. * 10b - 128-Tap Resampling Filter
  300. * 11b - N/A
  301. */
  302. regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
  303. EASRC_CRCC_RS_TAPS_MASK,
  304. EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps));
  305. /* Reset prefilter coefficient pointer back to 0 */
  306. ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
  307. if (ret)
  308. return ret;
  309. /*
  310. * When the filter is programmed to run in:
  311. * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase
  312. * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase
  313. * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase
  314. * This means the number of writes is constant no matter
  315. * the mode we are using
  316. */
  317. num_coeff = 16 * 128 * 4;
  318. for (i = 0; i < num_coeff; i++) {
  319. r = (uint32_t *)&coef[i];
  320. regmap_write(easrc->regmap, REG_EASRC_CRCM,
  321. EASRC_CRCM_RS_CWD(r[0]));
  322. regmap_write(easrc->regmap, REG_EASRC_CRCM,
  323. EASRC_CRCM_RS_CWD(r[1]));
  324. }
  325. return 0;
  326. }
  327. /**
  328. * fsl_easrc_normalize_filter - Scale filter coefficients (64 bits float)
  329. * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
  330. * scale it by multiplying filter coefficients by 2^31
  331. * For input int[16, 24, 32] -> output float32
  332. * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
  333. * input:
  334. * @easrc: Structure pointer of fsl_asrc
  335. * @infilter : Pointer to non-scaled input filter
  336. * @shift: The multiply factor
  337. * output:
  338. * @outfilter: scaled filter
  339. */
  340. static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
  341. u64 *infilter,
  342. u64 *outfilter,
  343. int shift)
  344. {
  345. struct device *dev = &easrc->pdev->dev;
  346. u64 coef = *infilter;
  347. s64 exp = (coef & 0x7ff0000000000000ll) >> 52;
  348. u64 outcoef;
  349. /*
  350. * If exponent is zero (value == 0), or 7ff (value == NaNs)
  351. * dont touch the content
  352. */
  353. if (exp == 0 || exp == 0x7ff) {
  354. *outfilter = coef;
  355. return 0;
  356. }
  357. /* coef * 2^shift ==> exp + shift */
  358. exp += shift;
  359. if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) {
  360. dev_err(dev, "coef out of range\n");
  361. return -EINVAL;
  362. }
  363. outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52);
  364. *outfilter = outcoef;
  365. return 0;
  366. }
  367. static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
  368. u64 *coef, int n_taps, int shift)
  369. {
  370. struct device *dev = &easrc->pdev->dev;
  371. int ret = 0;
  372. int i;
  373. u32 *r;
  374. u64 tmp;
  375. /* If STx_NUM_TAPS is set to 0x0 then return */
  376. if (!n_taps)
  377. return 0;
  378. if (!coef) {
  379. dev_err(dev, "coef table is NULL\n");
  380. return -EINVAL;
  381. }
  382. /*
  383. * When switching between stages, the address pointer
  384. * should be reset back to 0x0 before performing a write
  385. */
  386. ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
  387. if (ret)
  388. return ret;
  389. for (i = 0; i < (n_taps + 1) / 2; i++) {
  390. ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
  391. if (ret)
  392. return ret;
  393. r = (uint32_t *)&tmp;
  394. regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
  395. EASRC_PCF_CD(r[0]));
  396. regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
  397. EASRC_PCF_CD(r[1]));
  398. }
  399. return 0;
  400. }
  401. static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
  402. unsigned int ctx_id)
  403. {
  404. struct prefil_params *prefil, *selected_prefil = NULL;
  405. struct fsl_easrc_ctx_priv *ctx_priv;
  406. struct fsl_easrc_priv *easrc_priv;
  407. struct asrc_firmware_hdr *hdr;
  408. struct fsl_asrc_pair *ctx;
  409. struct device *dev;
  410. u32 inrate, outrate, offset = 0;
  411. u32 in_s_rate, out_s_rate;
  412. snd_pcm_format_t in_s_fmt, out_s_fmt;
  413. int ret, i;
  414. if (!easrc)
  415. return -ENODEV;
  416. dev = &easrc->pdev->dev;
  417. if (ctx_id >= EASRC_CTX_MAX_NUM) {
  418. dev_err(dev, "Invalid context id[%d]\n", ctx_id);
  419. return -EINVAL;
  420. }
  421. easrc_priv = easrc->private;
  422. ctx = easrc->pair[ctx_id];
  423. ctx_priv = ctx->private;
  424. in_s_rate = ctx_priv->in_params.sample_rate;
  425. out_s_rate = ctx_priv->out_params.sample_rate;
  426. in_s_fmt = ctx_priv->in_params.sample_format;
  427. out_s_fmt = ctx_priv->out_params.sample_format;
  428. ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2;
  429. ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
  430. ctx_priv->st1_num_taps = 0;
  431. ctx_priv->st2_num_taps = 0;
  432. regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
  433. regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
  434. /*
  435. * The audio float point data range is (-1, 1), the asrc would output
  436. * all zero for float point input and integer output case, that is to
  437. * drop the fractional part of the data directly.
  438. *
  439. * In order to support float to int conversion or int to float
  440. * conversion we need to do special operation on the coefficient to
  441. * enlarge/reduce the data to the expected range.
  442. *
  443. * For float to int case:
  444. * Up sampling:
  445. * 1. Create a 1 tap filter with center tap (only tap) of 2^31
  446. * in 64 bits floating point.
  447. * double value = (double)(((uint64_t)1) << 31)
  448. * 2. Program 1 tap prefilter with center tap above.
  449. *
  450. * Down sampling,
  451. * 1. If the filter is single stage filter, add "shift" to the exponent
  452. * of stage 1 coefficients.
  453. * 2. If the filter is two stage filter , add "shift" to the exponent
  454. * of stage 2 coefficients.
  455. *
  456. * The "shift" is 31, same for int16, int24, int32 case.
  457. *
  458. * For int to float case:
  459. * Up sampling:
  460. * 1. Create a 1 tap filter with center tap (only tap) of 2^-31
  461. * in 64 bits floating point.
  462. * 2. Program 1 tap prefilter with center tap above.
  463. *
  464. * Down sampling,
  465. * 1. If the filter is single stage filter, subtract "shift" to the
  466. * exponent of stage 1 coefficients.
  467. * 2. If the filter is two stage filter , subtract "shift" to the
  468. * exponent of stage 2 coefficients.
  469. *
  470. * The "shift" is 15,23,31, different for int16, int24, int32 case.
  471. *
  472. */
  473. if (out_s_rate >= in_s_rate) {
  474. if (out_s_rate == in_s_rate)
  475. regmap_update_bits(easrc->regmap,
  476. REG_EASRC_CCE1(ctx_id),
  477. EASRC_CCE1_RS_BYPASS_MASK,
  478. EASRC_CCE1_RS_BYPASS);
  479. ctx_priv->st1_num_taps = 1;
  480. ctx_priv->st1_coeff = &easrc_priv->const_coeff;
  481. ctx_priv->st1_num_exp = 1;
  482. ctx_priv->st2_num_taps = 0;
  483. if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
  484. out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE)
  485. ctx_priv->st1_addexp = 31;
  486. else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
  487. out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE)
  488. ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
  489. } else {
  490. inrate = ctx_priv->in_params.norm_rate;
  491. outrate = ctx_priv->out_params.norm_rate;
  492. hdr = easrc_priv->firmware_hdr;
  493. prefil = easrc_priv->prefil;
  494. for (i = 0; i < hdr->prefil_scen; i++) {
  495. if (inrate == prefil[i].insr &&
  496. outrate == prefil[i].outsr) {
  497. selected_prefil = &prefil[i];
  498. dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n",
  499. selected_prefil->insr,
  500. selected_prefil->outsr,
  501. selected_prefil->st1_taps,
  502. selected_prefil->st2_taps);
  503. break;
  504. }
  505. }
  506. if (!selected_prefil) {
  507. dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n",
  508. in_s_rate, inrate,
  509. out_s_rate, outrate);
  510. return -EINVAL;
  511. }
  512. /*
  513. * In prefilter coeff array, first st1_num_taps represent the
  514. * stage1 prefilter coefficients followed by next st2_num_taps
  515. * representing stage 2 coefficients
  516. */
  517. ctx_priv->st1_num_taps = selected_prefil->st1_taps;
  518. ctx_priv->st1_coeff = selected_prefil->coeff;
  519. ctx_priv->st1_num_exp = selected_prefil->st1_exp;
  520. offset = ((selected_prefil->st1_taps + 1) / 2);
  521. ctx_priv->st2_num_taps = selected_prefil->st2_taps;
  522. ctx_priv->st2_coeff = selected_prefil->coeff + offset;
  523. if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
  524. out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) {
  525. /* only change stage2 coefficient for 2 stage case */
  526. if (ctx_priv->st2_num_taps > 0)
  527. ctx_priv->st2_addexp = 31;
  528. else
  529. ctx_priv->st1_addexp = 31;
  530. } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
  531. out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) {
  532. if (ctx_priv->st2_num_taps > 0)
  533. ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp;
  534. else
  535. ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
  536. }
  537. }
  538. ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp +
  539. ctx_priv->st2_num_taps / 2;
  540. ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
  541. if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0)
  542. ctx_priv->out_missed_sample += 1;
  543. /*
  544. * To modify the value of a prefilter coefficient, the user must
  545. * perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA]
  546. * while the respective context RUN_EN bit is set to 0b0
  547. */
  548. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
  549. EASRC_CC_EN_MASK, 0);
  550. if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
  551. dev_err(dev, "ST1 taps [%d] mus be lower than %d\n",
  552. ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS);
  553. ret = -EINVAL;
  554. goto ctx_error;
  555. }
  556. /* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */
  557. regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
  558. EASRC_CCE2_ST1_TAPS_MASK,
  559. EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1));
  560. /* Prefilter Coefficient Write Select to write in ST1 coeff */
  561. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  562. EASRC_CCE1_COEF_WS_MASK,
  563. EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
  564. ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
  565. ctx_priv->st1_coeff,
  566. ctx_priv->st1_num_taps,
  567. ctx_priv->st1_addexp);
  568. if (ret)
  569. goto ctx_error;
  570. if (ctx_priv->st2_num_taps > 0) {
  571. if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
  572. dev_err(dev, "ST2 taps [%d] mus be lower than %d\n",
  573. ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS);
  574. ret = -EINVAL;
  575. goto ctx_error;
  576. }
  577. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  578. EASRC_CCE1_PF_TSEN_MASK,
  579. EASRC_CCE1_PF_TSEN);
  580. /*
  581. * Enable prefilter stage1 writeback floating point
  582. * which is used for FLOAT_LE case
  583. */
  584. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  585. EASRC_CCE1_PF_ST1_WBFP_MASK,
  586. EASRC_CCE1_PF_ST1_WBFP);
  587. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  588. EASRC_CCE1_PF_EXP_MASK,
  589. EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1));
  590. /* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */
  591. regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
  592. EASRC_CCE2_ST2_TAPS_MASK,
  593. EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1));
  594. /* Prefilter Coefficient Write Select to write in ST2 coeff */
  595. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  596. EASRC_CCE1_COEF_WS_MASK,
  597. EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
  598. ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
  599. ctx_priv->st2_coeff,
  600. ctx_priv->st2_num_taps,
  601. ctx_priv->st2_addexp);
  602. if (ret)
  603. goto ctx_error;
  604. }
  605. return 0;
  606. ctx_error:
  607. return ret;
  608. }
  609. static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx,
  610. struct fsl_easrc_slot *slot)
  611. {
  612. struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
  613. int st1_mem_alloc = 0, st2_mem_alloc = 0;
  614. int pf_mem_alloc = 0;
  615. int max_channels = 8 - slot->num_channel;
  616. int channels = 0;
  617. if (ctx_priv->st1_num_taps > 0) {
  618. if (ctx_priv->st2_num_taps > 0)
  619. st1_mem_alloc =
  620. (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1;
  621. else
  622. st1_mem_alloc = ctx_priv->st1_num_taps;
  623. }
  624. if (ctx_priv->st2_num_taps > 0)
  625. st2_mem_alloc = ctx_priv->st2_num_taps;
  626. pf_mem_alloc = st1_mem_alloc + st2_mem_alloc;
  627. if (pf_mem_alloc != 0)
  628. channels = (6144 - slot->pf_mem_used) / pf_mem_alloc;
  629. else
  630. channels = 8;
  631. if (channels < max_channels)
  632. max_channels = channels;
  633. return max_channels;
  634. }
  635. static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx,
  636. struct fsl_easrc_slot *slot,
  637. unsigned int slot_ctx_idx,
  638. unsigned int *req_channels,
  639. unsigned int *start_channel,
  640. unsigned int *avail_channel)
  641. {
  642. struct fsl_asrc *easrc = ctx->asrc;
  643. struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
  644. int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc;
  645. unsigned int reg0, reg1, reg2, reg3;
  646. unsigned int addr;
  647. if (slot->slot_index == 0) {
  648. reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx);
  649. reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx);
  650. reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx);
  651. reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx);
  652. } else {
  653. reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx);
  654. reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx);
  655. reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx);
  656. reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx);
  657. }
  658. if (*req_channels <= *avail_channel) {
  659. slot->num_channel = *req_channels;
  660. *req_channels = 0;
  661. } else {
  662. slot->num_channel = *avail_channel;
  663. *req_channels -= *avail_channel;
  664. }
  665. slot->min_channel = *start_channel;
  666. slot->max_channel = *start_channel + slot->num_channel - 1;
  667. slot->ctx_index = ctx->index;
  668. slot->busy = true;
  669. *start_channel += slot->num_channel;
  670. regmap_update_bits(easrc->regmap, reg0,
  671. EASRC_DPCS0R0_MAXCH_MASK,
  672. EASRC_DPCS0R0_MAXCH(slot->max_channel));
  673. regmap_update_bits(easrc->regmap, reg0,
  674. EASRC_DPCS0R0_MINCH_MASK,
  675. EASRC_DPCS0R0_MINCH(slot->min_channel));
  676. regmap_update_bits(easrc->regmap, reg0,
  677. EASRC_DPCS0R0_NUMCH_MASK,
  678. EASRC_DPCS0R0_NUMCH(slot->num_channel - 1));
  679. regmap_update_bits(easrc->regmap, reg0,
  680. EASRC_DPCS0R0_CTXNUM_MASK,
  681. EASRC_DPCS0R0_CTXNUM(slot->ctx_index));
  682. if (ctx_priv->st1_num_taps > 0) {
  683. if (ctx_priv->st2_num_taps > 0)
  684. st1_mem_alloc =
  685. (ctx_priv->st1_num_taps - 1) * slot->num_channel *
  686. ctx_priv->st1_num_exp + slot->num_channel;
  687. else
  688. st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel;
  689. slot->pf_mem_used = st1_mem_alloc;
  690. regmap_update_bits(easrc->regmap, reg2,
  691. EASRC_DPCS0R2_ST1_MA_MASK,
  692. EASRC_DPCS0R2_ST1_MA(st1_mem_alloc));
  693. if (slot->slot_index == 1)
  694. addr = PREFILTER_MEM_LEN - st1_mem_alloc;
  695. else
  696. addr = 0;
  697. regmap_update_bits(easrc->regmap, reg2,
  698. EASRC_DPCS0R2_ST1_SA_MASK,
  699. EASRC_DPCS0R2_ST1_SA(addr));
  700. }
  701. if (ctx_priv->st2_num_taps > 0) {
  702. st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1);
  703. regmap_update_bits(easrc->regmap, reg1,
  704. EASRC_DPCS0R1_ST1_EXP_MASK,
  705. EASRC_DPCS0R1_ST1_EXP(st1_chanxexp));
  706. st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps;
  707. slot->pf_mem_used += st2_mem_alloc;
  708. regmap_update_bits(easrc->regmap, reg3,
  709. EASRC_DPCS0R3_ST2_MA_MASK,
  710. EASRC_DPCS0R3_ST2_MA(st2_mem_alloc));
  711. if (slot->slot_index == 1)
  712. addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc;
  713. else
  714. addr = st1_mem_alloc;
  715. regmap_update_bits(easrc->regmap, reg3,
  716. EASRC_DPCS0R3_ST2_SA_MASK,
  717. EASRC_DPCS0R3_ST2_SA(addr));
  718. }
  719. regmap_update_bits(easrc->regmap, reg0,
  720. EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN);
  721. return 0;
  722. }
  723. /*
  724. * fsl_easrc_config_slot
  725. *
  726. * A single context can be split amongst any of the 4 context processing pipes
  727. * in the design.
  728. * The total number of channels consumed within the context processor must be
  729. * less than or equal to 8. if a single context is configured to contain more
  730. * than 8 channels then it must be distributed across multiple context
  731. * processing pipe slots.
  732. *
  733. */
  734. static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
  735. {
  736. struct fsl_easrc_priv *easrc_priv = easrc->private;
  737. struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
  738. int req_channels = ctx->channels;
  739. int start_channel = 0, avail_channel;
  740. struct fsl_easrc_slot *slot0, *slot1;
  741. struct fsl_easrc_slot *slota, *slotb;
  742. int i, ret;
  743. if (req_channels <= 0)
  744. return -EINVAL;
  745. for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
  746. slot0 = &easrc_priv->slot[i][0];
  747. slot1 = &easrc_priv->slot[i][1];
  748. if (slot0->busy && slot1->busy) {
  749. continue;
  750. } else if ((slot0->busy && slot0->ctx_index == ctx->index) ||
  751. (slot1->busy && slot1->ctx_index == ctx->index)) {
  752. continue;
  753. } else if (!slot0->busy) {
  754. slota = slot0;
  755. slotb = slot1;
  756. slota->slot_index = 0;
  757. } else if (!slot1->busy) {
  758. slota = slot1;
  759. slotb = slot0;
  760. slota->slot_index = 1;
  761. }
  762. if (!slota || !slotb)
  763. continue;
  764. avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb);
  765. if (avail_channel <= 0)
  766. continue;
  767. ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels,
  768. &start_channel, &avail_channel);
  769. if (ret)
  770. return ret;
  771. if (req_channels > 0)
  772. continue;
  773. else
  774. break;
  775. }
  776. if (req_channels > 0) {
  777. dev_err(&easrc->pdev->dev, "no avail slot.\n");
  778. return -EINVAL;
  779. }
  780. return 0;
  781. }
  782. /*
  783. * fsl_easrc_release_slot
  784. *
  785. * Clear the slot configuration
  786. */
  787. static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
  788. {
  789. struct fsl_easrc_priv *easrc_priv = easrc->private;
  790. struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
  791. int i;
  792. for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
  793. if (easrc_priv->slot[i][0].busy &&
  794. easrc_priv->slot[i][0].ctx_index == ctx->index) {
  795. easrc_priv->slot[i][0].busy = false;
  796. easrc_priv->slot[i][0].num_channel = 0;
  797. easrc_priv->slot[i][0].pf_mem_used = 0;
  798. /* set registers */
  799. regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
  800. regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
  801. regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
  802. regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
  803. }
  804. if (easrc_priv->slot[i][1].busy &&
  805. easrc_priv->slot[i][1].ctx_index == ctx->index) {
  806. easrc_priv->slot[i][1].busy = false;
  807. easrc_priv->slot[i][1].num_channel = 0;
  808. easrc_priv->slot[i][1].pf_mem_used = 0;
  809. /* set registers */
  810. regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
  811. regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
  812. regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
  813. regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
  814. }
  815. }
  816. return 0;
  817. }
  818. /*
  819. * fsl_easrc_config_context
  820. *
  821. * Configure the register relate with context.
  822. */
  823. static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
  824. {
  825. struct fsl_easrc_ctx_priv *ctx_priv;
  826. struct fsl_asrc_pair *ctx;
  827. struct device *dev;
  828. unsigned long lock_flags;
  829. int ret;
  830. if (!easrc)
  831. return -ENODEV;
  832. dev = &easrc->pdev->dev;
  833. if (ctx_id >= EASRC_CTX_MAX_NUM) {
  834. dev_err(dev, "Invalid context id[%d]\n", ctx_id);
  835. return -EINVAL;
  836. }
  837. ctx = easrc->pair[ctx_id];
  838. ctx_priv = ctx->private;
  839. fsl_easrc_normalize_rates(ctx);
  840. ret = fsl_easrc_set_rs_ratio(ctx);
  841. if (ret)
  842. return ret;
  843. /* Initialize the context coeficients */
  844. ret = fsl_easrc_prefilter_config(easrc, ctx->index);
  845. if (ret)
  846. return ret;
  847. spin_lock_irqsave(&easrc->lock, lock_flags);
  848. ret = fsl_easrc_config_slot(easrc, ctx->index);
  849. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  850. if (ret)
  851. return ret;
  852. /*
  853. * Both prefilter and resampling filters can use following
  854. * initialization modes:
  855. * 2 - zero-fil mode
  856. * 1 - replication mode
  857. * 0 - software control
  858. */
  859. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  860. EASRC_CCE1_RS_INIT_MASK,
  861. EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode));
  862. regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
  863. EASRC_CCE1_PF_INIT_MASK,
  864. EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode));
  865. /*
  866. * Context Input FIFO Watermark
  867. * DMA request is generated when input FIFO < FIFO_WTMK
  868. */
  869. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
  870. EASRC_CC_FIFO_WTMK_MASK,
  871. EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk));
  872. /*
  873. * Context Output FIFO Watermark
  874. * DMA request is generated when output FIFO > FIFO_WTMK
  875. * So we set fifo_wtmk -1 to register.
  876. */
  877. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
  878. EASRC_COC_FIFO_WTMK_MASK,
  879. EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1));
  880. /* Number of channels */
  881. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
  882. EASRC_CC_CHEN_MASK,
  883. EASRC_CC_CHEN(ctx->channels - 1));
  884. return 0;
  885. }
  886. static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx,
  887. struct fsl_easrc_data_fmt *fmt,
  888. snd_pcm_format_t raw_fmt)
  889. {
  890. struct fsl_asrc *easrc = ctx->asrc;
  891. struct fsl_easrc_priv *easrc_priv = easrc->private;
  892. int ret;
  893. if (!fmt)
  894. return -EINVAL;
  895. /*
  896. * Context Input Floating Point Format
  897. * 0 - Integer Format
  898. * 1 - Single Precision FP Format
  899. */
  900. fmt->floating_point = !snd_pcm_format_linear(raw_fmt);
  901. fmt->sample_pos = 0;
  902. fmt->iec958 = 0;
  903. /* Get the data width */
  904. switch (snd_pcm_format_width(raw_fmt)) {
  905. case 16:
  906. fmt->width = EASRC_WIDTH_16_BIT;
  907. fmt->addexp = 15;
  908. break;
  909. case 20:
  910. fmt->width = EASRC_WIDTH_20_BIT;
  911. fmt->addexp = 19;
  912. break;
  913. case 24:
  914. fmt->width = EASRC_WIDTH_24_BIT;
  915. fmt->addexp = 23;
  916. break;
  917. case 32:
  918. fmt->width = EASRC_WIDTH_32_BIT;
  919. fmt->addexp = 31;
  920. break;
  921. default:
  922. return -EINVAL;
  923. }
  924. switch (raw_fmt) {
  925. case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
  926. fmt->width = easrc_priv->bps_iec958[ctx->index];
  927. fmt->iec958 = 1;
  928. fmt->floating_point = 0;
  929. if (fmt->width == EASRC_WIDTH_16_BIT) {
  930. fmt->sample_pos = 12;
  931. fmt->addexp = 15;
  932. } else if (fmt->width == EASRC_WIDTH_20_BIT) {
  933. fmt->sample_pos = 8;
  934. fmt->addexp = 19;
  935. } else if (fmt->width == EASRC_WIDTH_24_BIT) {
  936. fmt->sample_pos = 4;
  937. fmt->addexp = 23;
  938. }
  939. break;
  940. default:
  941. break;
  942. }
  943. /*
  944. * Data Endianness
  945. * 0 - Little-Endian
  946. * 1 - Big-Endian
  947. */
  948. ret = snd_pcm_format_big_endian(raw_fmt);
  949. if (ret < 0)
  950. return ret;
  951. fmt->endianness = ret;
  952. /*
  953. * Input Data sign
  954. * 0b - Signed Format
  955. * 1b - Unsigned Format
  956. */
  957. fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0;
  958. return 0;
  959. }
  960. static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx,
  961. snd_pcm_format_t *in_raw_format,
  962. snd_pcm_format_t *out_raw_format)
  963. {
  964. struct fsl_asrc *easrc = ctx->asrc;
  965. struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
  966. struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt;
  967. struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt;
  968. int ret = 0;
  969. /* Get the bitfield values for input data format */
  970. if (in_raw_format && out_raw_format) {
  971. ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format);
  972. if (ret)
  973. return ret;
  974. }
  975. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  976. EASRC_CC_BPS_MASK,
  977. EASRC_CC_BPS(in_fmt->width));
  978. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  979. EASRC_CC_ENDIANNESS_MASK,
  980. in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT);
  981. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  982. EASRC_CC_FMT_MASK,
  983. in_fmt->floating_point << EASRC_CC_FMT_SHIFT);
  984. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  985. EASRC_CC_INSIGN_MASK,
  986. in_fmt->unsign << EASRC_CC_INSIGN_SHIFT);
  987. /* In Sample Position */
  988. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  989. EASRC_CC_SAMPLE_POS_MASK,
  990. EASRC_CC_SAMPLE_POS(in_fmt->sample_pos));
  991. /* Get the bitfield values for input data format */
  992. if (in_raw_format && out_raw_format) {
  993. ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format);
  994. if (ret)
  995. return ret;
  996. }
  997. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  998. EASRC_COC_BPS_MASK,
  999. EASRC_COC_BPS(out_fmt->width));
  1000. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1001. EASRC_COC_ENDIANNESS_MASK,
  1002. out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT);
  1003. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1004. EASRC_COC_FMT_MASK,
  1005. out_fmt->floating_point << EASRC_COC_FMT_SHIFT);
  1006. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1007. EASRC_COC_OUTSIGN_MASK,
  1008. out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT);
  1009. /* Out Sample Position */
  1010. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1011. EASRC_COC_SAMPLE_POS_MASK,
  1012. EASRC_COC_SAMPLE_POS(out_fmt->sample_pos));
  1013. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1014. EASRC_COC_IEC_EN_MASK,
  1015. out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT);
  1016. return ret;
  1017. }
  1018. /*
  1019. * The ASRC provides interleaving support in hardware to ensure that a
  1020. * variety of sample sources can be internally combined
  1021. * to conform with this format. Interleaving parameters are accessed
  1022. * through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers
  1023. */
  1024. static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx)
  1025. {
  1026. struct fsl_easrc_ctx_priv *ctx_priv;
  1027. struct fsl_asrc *easrc;
  1028. if (!ctx)
  1029. return -ENODEV;
  1030. easrc = ctx->asrc;
  1031. ctx_priv = ctx->private;
  1032. /* input interleaving parameters */
  1033. regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
  1034. EASRC_CIA_ITER_MASK,
  1035. EASRC_CIA_ITER(ctx_priv->in_params.iterations));
  1036. regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
  1037. EASRC_CIA_GRLEN_MASK,
  1038. EASRC_CIA_GRLEN(ctx_priv->in_params.group_len));
  1039. regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
  1040. EASRC_CIA_ACCLEN_MASK,
  1041. EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len));
  1042. /* output interleaving parameters */
  1043. regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
  1044. EASRC_COA_ITER_MASK,
  1045. EASRC_COA_ITER(ctx_priv->out_params.iterations));
  1046. regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
  1047. EASRC_COA_GRLEN_MASK,
  1048. EASRC_COA_GRLEN(ctx_priv->out_params.group_len));
  1049. regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
  1050. EASRC_COA_ACCLEN_MASK,
  1051. EASRC_COA_ACCLEN(ctx_priv->out_params.access_len));
  1052. return 0;
  1053. }
  1054. /*
  1055. * Request one of the available contexts
  1056. *
  1057. * Returns a negative number on error and >=0 as context id
  1058. * on success
  1059. */
  1060. static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx)
  1061. {
  1062. enum asrc_pair_index index = ASRC_INVALID_PAIR;
  1063. struct fsl_asrc *easrc = ctx->asrc;
  1064. struct device *dev;
  1065. unsigned long lock_flags;
  1066. int ret = 0;
  1067. int i;
  1068. dev = &easrc->pdev->dev;
  1069. spin_lock_irqsave(&easrc->lock, lock_flags);
  1070. for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
  1071. if (easrc->pair[i])
  1072. continue;
  1073. index = i;
  1074. break;
  1075. }
  1076. if (index == ASRC_INVALID_PAIR) {
  1077. dev_err(dev, "all contexts are busy\n");
  1078. ret = -EBUSY;
  1079. } else if (channels > easrc->channel_avail) {
  1080. dev_err(dev, "can't give the required channels: %d\n",
  1081. channels);
  1082. ret = -EINVAL;
  1083. } else {
  1084. ctx->index = index;
  1085. ctx->channels = channels;
  1086. easrc->pair[index] = ctx;
  1087. easrc->channel_avail -= channels;
  1088. }
  1089. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  1090. return ret;
  1091. }
  1092. /*
  1093. * Release the context
  1094. *
  1095. * This funciton is mainly doing the revert thing in request context
  1096. */
  1097. static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx)
  1098. {
  1099. unsigned long lock_flags;
  1100. struct fsl_asrc *easrc;
  1101. if (!ctx)
  1102. return;
  1103. easrc = ctx->asrc;
  1104. spin_lock_irqsave(&easrc->lock, lock_flags);
  1105. fsl_easrc_release_slot(easrc, ctx->index);
  1106. easrc->channel_avail += ctx->channels;
  1107. easrc->pair[ctx->index] = NULL;
  1108. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  1109. }
  1110. /*
  1111. * Start the context
  1112. *
  1113. * Enable the DMA request and context
  1114. */
  1115. static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx)
  1116. {
  1117. struct fsl_asrc *easrc = ctx->asrc;
  1118. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  1119. EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE);
  1120. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1121. EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE);
  1122. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  1123. EASRC_CC_EN_MASK, EASRC_CC_EN);
  1124. return 0;
  1125. }
  1126. /*
  1127. * Stop the context
  1128. *
  1129. * Disable the DMA request and context
  1130. */
  1131. static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx)
  1132. {
  1133. struct fsl_asrc *easrc = ctx->asrc;
  1134. int val, i;
  1135. int size;
  1136. int retry = 200;
  1137. regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
  1138. if (val & EASRC_CC_EN_MASK) {
  1139. regmap_update_bits(easrc->regmap,
  1140. REG_EASRC_CC(ctx->index),
  1141. EASRC_CC_STOP_MASK, EASRC_CC_STOP);
  1142. do {
  1143. regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
  1144. val &= EASRC_SFS_NSGO_MASK;
  1145. size = val >> EASRC_SFS_NSGO_SHIFT;
  1146. /* Read FIFO, drop the data */
  1147. for (i = 0; i < size * ctx->channels; i++)
  1148. regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
  1149. /* Check RUN_STOP_DONE */
  1150. regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
  1151. if (val & EASRC_IRQF_RSD(1 << ctx->index)) {
  1152. /*Clear RUN_STOP_DONE*/
  1153. regmap_write_bits(easrc->regmap,
  1154. REG_EASRC_IRQF,
  1155. EASRC_IRQF_RSD(1 << ctx->index),
  1156. EASRC_IRQF_RSD(1 << ctx->index));
  1157. break;
  1158. }
  1159. udelay(100);
  1160. } while (--retry);
  1161. if (retry == 0)
  1162. dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
  1163. }
  1164. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  1165. EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0);
  1166. regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
  1167. EASRC_CC_FWMDE_MASK, 0);
  1168. regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
  1169. EASRC_COC_FWMDE_MASK, 0);
  1170. return 0;
  1171. }
  1172. static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx,
  1173. bool dir)
  1174. {
  1175. struct fsl_asrc *easrc = ctx->asrc;
  1176. enum asrc_pair_index index = ctx->index;
  1177. char name[8];
  1178. /* Example of dma name: ctx0_rx */
  1179. sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't');
  1180. return dma_request_slave_channel(&easrc->pdev->dev, name);
  1181. };
  1182. static const unsigned int easrc_rates[] = {
  1183. 8000, 11025, 12000, 16000,
  1184. 22050, 24000, 32000, 44100,
  1185. 48000, 64000, 88200, 96000,
  1186. 128000, 176400, 192000, 256000,
  1187. 352800, 384000, 705600, 768000,
  1188. };
  1189. static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = {
  1190. .count = ARRAY_SIZE(easrc_rates),
  1191. .list = easrc_rates,
  1192. };
  1193. static int fsl_easrc_startup(struct snd_pcm_substream *substream,
  1194. struct snd_soc_dai *dai)
  1195. {
  1196. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  1197. SNDRV_PCM_HW_PARAM_RATE,
  1198. &easrc_rate_constraints);
  1199. }
  1200. static int fsl_easrc_trigger(struct snd_pcm_substream *substream,
  1201. int cmd, struct snd_soc_dai *dai)
  1202. {
  1203. struct snd_pcm_runtime *runtime = substream->runtime;
  1204. struct fsl_asrc_pair *ctx = runtime->private_data;
  1205. int ret;
  1206. switch (cmd) {
  1207. case SNDRV_PCM_TRIGGER_START:
  1208. case SNDRV_PCM_TRIGGER_RESUME:
  1209. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1210. ret = fsl_easrc_start_context(ctx);
  1211. if (ret)
  1212. return ret;
  1213. break;
  1214. case SNDRV_PCM_TRIGGER_STOP:
  1215. case SNDRV_PCM_TRIGGER_SUSPEND:
  1216. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1217. ret = fsl_easrc_stop_context(ctx);
  1218. if (ret)
  1219. return ret;
  1220. break;
  1221. default:
  1222. return -EINVAL;
  1223. }
  1224. return 0;
  1225. }
  1226. static int fsl_easrc_hw_params(struct snd_pcm_substream *substream,
  1227. struct snd_pcm_hw_params *params,
  1228. struct snd_soc_dai *dai)
  1229. {
  1230. struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
  1231. struct snd_pcm_runtime *runtime = substream->runtime;
  1232. struct device *dev = &easrc->pdev->dev;
  1233. struct fsl_asrc_pair *ctx = runtime->private_data;
  1234. struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
  1235. unsigned int channels = params_channels(params);
  1236. unsigned int rate = params_rate(params);
  1237. snd_pcm_format_t format = params_format(params);
  1238. int ret;
  1239. ret = fsl_easrc_request_context(channels, ctx);
  1240. if (ret) {
  1241. dev_err(dev, "failed to request context\n");
  1242. return ret;
  1243. }
  1244. ctx_priv->ctx_streams |= BIT(substream->stream);
  1245. /*
  1246. * Set the input and output ratio so we can compute
  1247. * the resampling ratio in RS_LOW/HIGH
  1248. */
  1249. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1250. ctx_priv->in_params.sample_rate = rate;
  1251. ctx_priv->in_params.sample_format = format;
  1252. ctx_priv->out_params.sample_rate = easrc->asrc_rate;
  1253. ctx_priv->out_params.sample_format = easrc->asrc_format;
  1254. } else {
  1255. ctx_priv->out_params.sample_rate = rate;
  1256. ctx_priv->out_params.sample_format = format;
  1257. ctx_priv->in_params.sample_rate = easrc->asrc_rate;
  1258. ctx_priv->in_params.sample_format = easrc->asrc_format;
  1259. }
  1260. ctx->channels = channels;
  1261. ctx_priv->in_params.fifo_wtmk = 0x20;
  1262. ctx_priv->out_params.fifo_wtmk = 0x20;
  1263. /*
  1264. * Do only rate conversion and keep the same format for input
  1265. * and output data
  1266. */
  1267. ret = fsl_easrc_set_ctx_format(ctx,
  1268. &ctx_priv->in_params.sample_format,
  1269. &ctx_priv->out_params.sample_format);
  1270. if (ret) {
  1271. dev_err(dev, "failed to set format %d", ret);
  1272. return ret;
  1273. }
  1274. ret = fsl_easrc_config_context(easrc, ctx->index);
  1275. if (ret) {
  1276. dev_err(dev, "failed to config context\n");
  1277. return ret;
  1278. }
  1279. ctx_priv->in_params.iterations = 1;
  1280. ctx_priv->in_params.group_len = ctx->channels;
  1281. ctx_priv->in_params.access_len = ctx->channels;
  1282. ctx_priv->out_params.iterations = 1;
  1283. ctx_priv->out_params.group_len = ctx->channels;
  1284. ctx_priv->out_params.access_len = ctx->channels;
  1285. ret = fsl_easrc_set_ctx_organziation(ctx);
  1286. if (ret) {
  1287. dev_err(dev, "failed to set fifo organization\n");
  1288. return ret;
  1289. }
  1290. return 0;
  1291. }
  1292. static int fsl_easrc_hw_free(struct snd_pcm_substream *substream,
  1293. struct snd_soc_dai *dai)
  1294. {
  1295. struct snd_pcm_runtime *runtime = substream->runtime;
  1296. struct fsl_asrc_pair *ctx = runtime->private_data;
  1297. struct fsl_easrc_ctx_priv *ctx_priv;
  1298. if (!ctx)
  1299. return -EINVAL;
  1300. ctx_priv = ctx->private;
  1301. if (ctx_priv->ctx_streams & BIT(substream->stream)) {
  1302. ctx_priv->ctx_streams &= ~BIT(substream->stream);
  1303. fsl_easrc_release_context(ctx);
  1304. }
  1305. return 0;
  1306. }
  1307. static const struct snd_soc_dai_ops fsl_easrc_dai_ops = {
  1308. .startup = fsl_easrc_startup,
  1309. .trigger = fsl_easrc_trigger,
  1310. .hw_params = fsl_easrc_hw_params,
  1311. .hw_free = fsl_easrc_hw_free,
  1312. };
  1313. static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai)
  1314. {
  1315. struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
  1316. snd_soc_dai_init_dma_data(cpu_dai,
  1317. &easrc->dma_params_tx,
  1318. &easrc->dma_params_rx);
  1319. return 0;
  1320. }
  1321. static struct snd_soc_dai_driver fsl_easrc_dai = {
  1322. .probe = fsl_easrc_dai_probe,
  1323. .playback = {
  1324. .stream_name = "ASRC-Playback",
  1325. .channels_min = 1,
  1326. .channels_max = 32,
  1327. .rate_min = 8000,
  1328. .rate_max = 768000,
  1329. .rates = SNDRV_PCM_RATE_KNOT,
  1330. .formats = FSL_EASRC_FORMATS,
  1331. },
  1332. .capture = {
  1333. .stream_name = "ASRC-Capture",
  1334. .channels_min = 1,
  1335. .channels_max = 32,
  1336. .rate_min = 8000,
  1337. .rate_max = 768000,
  1338. .rates = SNDRV_PCM_RATE_KNOT,
  1339. .formats = FSL_EASRC_FORMATS |
  1340. SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
  1341. },
  1342. .ops = &fsl_easrc_dai_ops,
  1343. };
  1344. static const struct snd_soc_component_driver fsl_easrc_component = {
  1345. .name = "fsl-easrc-dai",
  1346. .controls = fsl_easrc_snd_controls,
  1347. .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls),
  1348. .legacy_dai_naming = 1,
  1349. };
  1350. static const struct reg_default fsl_easrc_reg_defaults[] = {
  1351. {REG_EASRC_WRFIFO(0), 0x00000000},
  1352. {REG_EASRC_WRFIFO(1), 0x00000000},
  1353. {REG_EASRC_WRFIFO(2), 0x00000000},
  1354. {REG_EASRC_WRFIFO(3), 0x00000000},
  1355. {REG_EASRC_RDFIFO(0), 0x00000000},
  1356. {REG_EASRC_RDFIFO(1), 0x00000000},
  1357. {REG_EASRC_RDFIFO(2), 0x00000000},
  1358. {REG_EASRC_RDFIFO(3), 0x00000000},
  1359. {REG_EASRC_CC(0), 0x00000000},
  1360. {REG_EASRC_CC(1), 0x00000000},
  1361. {REG_EASRC_CC(2), 0x00000000},
  1362. {REG_EASRC_CC(3), 0x00000000},
  1363. {REG_EASRC_CCE1(0), 0x00000000},
  1364. {REG_EASRC_CCE1(1), 0x00000000},
  1365. {REG_EASRC_CCE1(2), 0x00000000},
  1366. {REG_EASRC_CCE1(3), 0x00000000},
  1367. {REG_EASRC_CCE2(0), 0x00000000},
  1368. {REG_EASRC_CCE2(1), 0x00000000},
  1369. {REG_EASRC_CCE2(2), 0x00000000},
  1370. {REG_EASRC_CCE2(3), 0x00000000},
  1371. {REG_EASRC_CIA(0), 0x00000000},
  1372. {REG_EASRC_CIA(1), 0x00000000},
  1373. {REG_EASRC_CIA(2), 0x00000000},
  1374. {REG_EASRC_CIA(3), 0x00000000},
  1375. {REG_EASRC_DPCS0R0(0), 0x00000000},
  1376. {REG_EASRC_DPCS0R0(1), 0x00000000},
  1377. {REG_EASRC_DPCS0R0(2), 0x00000000},
  1378. {REG_EASRC_DPCS0R0(3), 0x00000000},
  1379. {REG_EASRC_DPCS0R1(0), 0x00000000},
  1380. {REG_EASRC_DPCS0R1(1), 0x00000000},
  1381. {REG_EASRC_DPCS0R1(2), 0x00000000},
  1382. {REG_EASRC_DPCS0R1(3), 0x00000000},
  1383. {REG_EASRC_DPCS0R2(0), 0x00000000},
  1384. {REG_EASRC_DPCS0R2(1), 0x00000000},
  1385. {REG_EASRC_DPCS0R2(2), 0x00000000},
  1386. {REG_EASRC_DPCS0R2(3), 0x00000000},
  1387. {REG_EASRC_DPCS0R3(0), 0x00000000},
  1388. {REG_EASRC_DPCS0R3(1), 0x00000000},
  1389. {REG_EASRC_DPCS0R3(2), 0x00000000},
  1390. {REG_EASRC_DPCS0R3(3), 0x00000000},
  1391. {REG_EASRC_DPCS1R0(0), 0x00000000},
  1392. {REG_EASRC_DPCS1R0(1), 0x00000000},
  1393. {REG_EASRC_DPCS1R0(2), 0x00000000},
  1394. {REG_EASRC_DPCS1R0(3), 0x00000000},
  1395. {REG_EASRC_DPCS1R1(0), 0x00000000},
  1396. {REG_EASRC_DPCS1R1(1), 0x00000000},
  1397. {REG_EASRC_DPCS1R1(2), 0x00000000},
  1398. {REG_EASRC_DPCS1R1(3), 0x00000000},
  1399. {REG_EASRC_DPCS1R2(0), 0x00000000},
  1400. {REG_EASRC_DPCS1R2(1), 0x00000000},
  1401. {REG_EASRC_DPCS1R2(2), 0x00000000},
  1402. {REG_EASRC_DPCS1R2(3), 0x00000000},
  1403. {REG_EASRC_DPCS1R3(0), 0x00000000},
  1404. {REG_EASRC_DPCS1R3(1), 0x00000000},
  1405. {REG_EASRC_DPCS1R3(2), 0x00000000},
  1406. {REG_EASRC_DPCS1R3(3), 0x00000000},
  1407. {REG_EASRC_COC(0), 0x00000000},
  1408. {REG_EASRC_COC(1), 0x00000000},
  1409. {REG_EASRC_COC(2), 0x00000000},
  1410. {REG_EASRC_COC(3), 0x00000000},
  1411. {REG_EASRC_COA(0), 0x00000000},
  1412. {REG_EASRC_COA(1), 0x00000000},
  1413. {REG_EASRC_COA(2), 0x00000000},
  1414. {REG_EASRC_COA(3), 0x00000000},
  1415. {REG_EASRC_SFS(0), 0x00000000},
  1416. {REG_EASRC_SFS(1), 0x00000000},
  1417. {REG_EASRC_SFS(2), 0x00000000},
  1418. {REG_EASRC_SFS(3), 0x00000000},
  1419. {REG_EASRC_RRL(0), 0x00000000},
  1420. {REG_EASRC_RRL(1), 0x00000000},
  1421. {REG_EASRC_RRL(2), 0x00000000},
  1422. {REG_EASRC_RRL(3), 0x00000000},
  1423. {REG_EASRC_RRH(0), 0x00000000},
  1424. {REG_EASRC_RRH(1), 0x00000000},
  1425. {REG_EASRC_RRH(2), 0x00000000},
  1426. {REG_EASRC_RRH(3), 0x00000000},
  1427. {REG_EASRC_RUC(0), 0x00000000},
  1428. {REG_EASRC_RUC(1), 0x00000000},
  1429. {REG_EASRC_RUC(2), 0x00000000},
  1430. {REG_EASRC_RUC(3), 0x00000000},
  1431. {REG_EASRC_RUR(0), 0x7FFFFFFF},
  1432. {REG_EASRC_RUR(1), 0x7FFFFFFF},
  1433. {REG_EASRC_RUR(2), 0x7FFFFFFF},
  1434. {REG_EASRC_RUR(3), 0x7FFFFFFF},
  1435. {REG_EASRC_RCTCL, 0x00000000},
  1436. {REG_EASRC_RCTCH, 0x00000000},
  1437. {REG_EASRC_PCF(0), 0x00000000},
  1438. {REG_EASRC_PCF(1), 0x00000000},
  1439. {REG_EASRC_PCF(2), 0x00000000},
  1440. {REG_EASRC_PCF(3), 0x00000000},
  1441. {REG_EASRC_CRCM, 0x00000000},
  1442. {REG_EASRC_CRCC, 0x00000000},
  1443. {REG_EASRC_IRQC, 0x00000FFF},
  1444. {REG_EASRC_IRQF, 0x00000000},
  1445. {REG_EASRC_CS0(0), 0x00000000},
  1446. {REG_EASRC_CS0(1), 0x00000000},
  1447. {REG_EASRC_CS0(2), 0x00000000},
  1448. {REG_EASRC_CS0(3), 0x00000000},
  1449. {REG_EASRC_CS1(0), 0x00000000},
  1450. {REG_EASRC_CS1(1), 0x00000000},
  1451. {REG_EASRC_CS1(2), 0x00000000},
  1452. {REG_EASRC_CS1(3), 0x00000000},
  1453. {REG_EASRC_CS2(0), 0x00000000},
  1454. {REG_EASRC_CS2(1), 0x00000000},
  1455. {REG_EASRC_CS2(2), 0x00000000},
  1456. {REG_EASRC_CS2(3), 0x00000000},
  1457. {REG_EASRC_CS3(0), 0x00000000},
  1458. {REG_EASRC_CS3(1), 0x00000000},
  1459. {REG_EASRC_CS3(2), 0x00000000},
  1460. {REG_EASRC_CS3(3), 0x00000000},
  1461. {REG_EASRC_CS4(0), 0x00000000},
  1462. {REG_EASRC_CS4(1), 0x00000000},
  1463. {REG_EASRC_CS4(2), 0x00000000},
  1464. {REG_EASRC_CS4(3), 0x00000000},
  1465. {REG_EASRC_CS5(0), 0x00000000},
  1466. {REG_EASRC_CS5(1), 0x00000000},
  1467. {REG_EASRC_CS5(2), 0x00000000},
  1468. {REG_EASRC_CS5(3), 0x00000000},
  1469. {REG_EASRC_DBGC, 0x00000000},
  1470. {REG_EASRC_DBGS, 0x00000000},
  1471. };
  1472. static const struct regmap_range fsl_easrc_readable_ranges[] = {
  1473. regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH),
  1474. regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)),
  1475. regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS),
  1476. };
  1477. static const struct regmap_access_table fsl_easrc_readable_table = {
  1478. .yes_ranges = fsl_easrc_readable_ranges,
  1479. .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges),
  1480. };
  1481. static const struct regmap_range fsl_easrc_writeable_ranges[] = {
  1482. regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)),
  1483. regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)),
  1484. regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH),
  1485. regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC),
  1486. };
  1487. static const struct regmap_access_table fsl_easrc_writeable_table = {
  1488. .yes_ranges = fsl_easrc_writeable_ranges,
  1489. .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges),
  1490. };
  1491. static const struct regmap_range fsl_easrc_volatileable_ranges[] = {
  1492. regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)),
  1493. regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)),
  1494. regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF),
  1495. regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS),
  1496. };
  1497. static const struct regmap_access_table fsl_easrc_volatileable_table = {
  1498. .yes_ranges = fsl_easrc_volatileable_ranges,
  1499. .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges),
  1500. };
  1501. static const struct regmap_config fsl_easrc_regmap_config = {
  1502. .reg_bits = 32,
  1503. .reg_stride = 4,
  1504. .val_bits = 32,
  1505. .max_register = REG_EASRC_DBGS,
  1506. .reg_defaults = fsl_easrc_reg_defaults,
  1507. .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults),
  1508. .rd_table = &fsl_easrc_readable_table,
  1509. .wr_table = &fsl_easrc_writeable_table,
  1510. .volatile_table = &fsl_easrc_volatileable_table,
  1511. .cache_type = REGCACHE_RBTREE,
  1512. };
  1513. #ifdef DEBUG
  1514. static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
  1515. {
  1516. struct fsl_easrc_priv *easrc_priv = easrc->private;
  1517. struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr;
  1518. struct interp_params *interp = easrc_priv->interp;
  1519. struct prefil_params *prefil = easrc_priv->prefil;
  1520. struct device *dev = &easrc->pdev->dev;
  1521. int i;
  1522. if (firm->magic != FIRMWARE_MAGIC) {
  1523. dev_err(dev, "Wrong magic. Something went wrong!");
  1524. return;
  1525. }
  1526. dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version);
  1527. dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen);
  1528. dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen);
  1529. dev_dbg(dev, "\nInterpolation scenarios:\n");
  1530. for (i = 0; i < firm->interp_scen; i++) {
  1531. if (interp[i].magic != FIRMWARE_MAGIC) {
  1532. dev_dbg(dev, "%d. wrong interp magic: %x\n",
  1533. i, interp[i].magic);
  1534. continue;
  1535. }
  1536. dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i,
  1537. interp[i].num_taps, interp[i].num_phases,
  1538. interp[i].center_tap);
  1539. }
  1540. for (i = 0; i < firm->prefil_scen; i++) {
  1541. if (prefil[i].magic != FIRMWARE_MAGIC) {
  1542. dev_dbg(dev, "%d. wrong prefil magic: %x\n",
  1543. i, prefil[i].magic);
  1544. continue;
  1545. }
  1546. dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i,
  1547. prefil[i].insr, prefil[i].outsr,
  1548. prefil[i].st1_taps, prefil[i].st2_taps);
  1549. }
  1550. dev_dbg(dev, "end of firmware dump\n");
  1551. }
  1552. #endif
  1553. static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
  1554. {
  1555. struct fsl_easrc_priv *easrc_priv;
  1556. const struct firmware **fw_p;
  1557. u32 pnum, inum, offset;
  1558. const u8 *data;
  1559. int ret;
  1560. if (!easrc)
  1561. return -EINVAL;
  1562. easrc_priv = easrc->private;
  1563. fw_p = &easrc_priv->fw;
  1564. ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
  1565. if (ret)
  1566. return ret;
  1567. data = easrc_priv->fw->data;
  1568. easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data;
  1569. pnum = easrc_priv->firmware_hdr->prefil_scen;
  1570. inum = easrc_priv->firmware_hdr->interp_scen;
  1571. if (inum) {
  1572. offset = sizeof(struct asrc_firmware_hdr);
  1573. easrc_priv->interp = (struct interp_params *)(data + offset);
  1574. }
  1575. if (pnum) {
  1576. offset = sizeof(struct asrc_firmware_hdr) +
  1577. inum * sizeof(struct interp_params);
  1578. easrc_priv->prefil = (struct prefil_params *)(data + offset);
  1579. }
  1580. #ifdef DEBUG
  1581. fsl_easrc_dump_firmware(easrc);
  1582. #endif
  1583. return 0;
  1584. }
  1585. static irqreturn_t fsl_easrc_isr(int irq, void *dev_id)
  1586. {
  1587. struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
  1588. struct device *dev = &easrc->pdev->dev;
  1589. int val;
  1590. regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
  1591. if (val & EASRC_IRQF_OER_MASK)
  1592. dev_dbg(dev, "output FIFO underflow\n");
  1593. if (val & EASRC_IRQF_IFO_MASK)
  1594. dev_dbg(dev, "input FIFO overflow\n");
  1595. return IRQ_HANDLED;
  1596. }
  1597. static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
  1598. {
  1599. return REG_EASRC_FIFO(dir, index);
  1600. }
  1601. static const struct of_device_id fsl_easrc_dt_ids[] = {
  1602. { .compatible = "fsl,imx8mn-easrc",},
  1603. {}
  1604. };
  1605. MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids);
  1606. static int fsl_easrc_probe(struct platform_device *pdev)
  1607. {
  1608. struct fsl_easrc_priv *easrc_priv;
  1609. struct device *dev = &pdev->dev;
  1610. struct fsl_asrc *easrc;
  1611. struct resource *res;
  1612. struct device_node *np;
  1613. void __iomem *regs;
  1614. u32 asrc_fmt = 0;
  1615. int ret, irq;
  1616. easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
  1617. if (!easrc)
  1618. return -ENOMEM;
  1619. easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL);
  1620. if (!easrc_priv)
  1621. return -ENOMEM;
  1622. easrc->pdev = pdev;
  1623. easrc->private = easrc_priv;
  1624. np = dev->of_node;
  1625. regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  1626. if (IS_ERR(regs))
  1627. return PTR_ERR(regs);
  1628. easrc->paddr = res->start;
  1629. easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config);
  1630. if (IS_ERR(easrc->regmap)) {
  1631. dev_err(dev, "failed to init regmap");
  1632. return PTR_ERR(easrc->regmap);
  1633. }
  1634. irq = platform_get_irq(pdev, 0);
  1635. if (irq < 0)
  1636. return irq;
  1637. ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
  1638. dev_name(dev), easrc);
  1639. if (ret) {
  1640. dev_err(dev, "failed to claim irq %u: %d\n", irq, ret);
  1641. return ret;
  1642. }
  1643. easrc->mem_clk = devm_clk_get(dev, "mem");
  1644. if (IS_ERR(easrc->mem_clk)) {
  1645. dev_err(dev, "failed to get mem clock\n");
  1646. return PTR_ERR(easrc->mem_clk);
  1647. }
  1648. /* Set default value */
  1649. easrc->channel_avail = 32;
  1650. easrc->get_dma_channel = fsl_easrc_get_dma_channel;
  1651. easrc->request_pair = fsl_easrc_request_context;
  1652. easrc->release_pair = fsl_easrc_release_context;
  1653. easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
  1654. easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
  1655. easrc_priv->rs_num_taps = EASRC_RS_32_TAPS;
  1656. easrc_priv->const_coeff = 0x3FF0000000000000;
  1657. ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
  1658. if (ret) {
  1659. dev_err(dev, "failed to asrc rate\n");
  1660. return ret;
  1661. }
  1662. ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
  1663. easrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
  1664. if (ret) {
  1665. dev_err(dev, "failed to asrc format\n");
  1666. return ret;
  1667. }
  1668. if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) {
  1669. dev_warn(dev, "unsupported format, switching to S24_LE\n");
  1670. easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
  1671. }
  1672. ret = of_property_read_string(np, "firmware-name",
  1673. &easrc_priv->fw_name);
  1674. if (ret) {
  1675. dev_err(dev, "failed to get firmware name\n");
  1676. return ret;
  1677. }
  1678. platform_set_drvdata(pdev, easrc);
  1679. pm_runtime_enable(dev);
  1680. spin_lock_init(&easrc->lock);
  1681. regcache_cache_only(easrc->regmap, true);
  1682. ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
  1683. &fsl_easrc_dai, 1);
  1684. if (ret) {
  1685. dev_err(dev, "failed to register ASoC DAI\n");
  1686. goto err_pm_disable;
  1687. }
  1688. ret = devm_snd_soc_register_component(dev, &fsl_asrc_component,
  1689. NULL, 0);
  1690. if (ret) {
  1691. dev_err(&pdev->dev, "failed to register ASoC platform\n");
  1692. goto err_pm_disable;
  1693. }
  1694. return 0;
  1695. err_pm_disable:
  1696. pm_runtime_disable(&pdev->dev);
  1697. return ret;
  1698. }
  1699. static int fsl_easrc_remove(struct platform_device *pdev)
  1700. {
  1701. pm_runtime_disable(&pdev->dev);
  1702. return 0;
  1703. }
  1704. static __maybe_unused int fsl_easrc_runtime_suspend(struct device *dev)
  1705. {
  1706. struct fsl_asrc *easrc = dev_get_drvdata(dev);
  1707. struct fsl_easrc_priv *easrc_priv = easrc->private;
  1708. unsigned long lock_flags;
  1709. regcache_cache_only(easrc->regmap, true);
  1710. clk_disable_unprepare(easrc->mem_clk);
  1711. spin_lock_irqsave(&easrc->lock, lock_flags);
  1712. easrc_priv->firmware_loaded = 0;
  1713. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  1714. return 0;
  1715. }
  1716. static __maybe_unused int fsl_easrc_runtime_resume(struct device *dev)
  1717. {
  1718. struct fsl_asrc *easrc = dev_get_drvdata(dev);
  1719. struct fsl_easrc_priv *easrc_priv = easrc->private;
  1720. struct fsl_easrc_ctx_priv *ctx_priv;
  1721. struct fsl_asrc_pair *ctx;
  1722. unsigned long lock_flags;
  1723. int ret;
  1724. int i;
  1725. ret = clk_prepare_enable(easrc->mem_clk);
  1726. if (ret)
  1727. return ret;
  1728. regcache_cache_only(easrc->regmap, false);
  1729. regcache_mark_dirty(easrc->regmap);
  1730. regcache_sync(easrc->regmap);
  1731. spin_lock_irqsave(&easrc->lock, lock_flags);
  1732. if (easrc_priv->firmware_loaded) {
  1733. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  1734. goto skip_load;
  1735. }
  1736. easrc_priv->firmware_loaded = 1;
  1737. spin_unlock_irqrestore(&easrc->lock, lock_flags);
  1738. ret = fsl_easrc_get_firmware(easrc);
  1739. if (ret) {
  1740. dev_err(dev, "failed to get firmware\n");
  1741. goto disable_mem_clk;
  1742. }
  1743. /*
  1744. * Write Resampling Coefficients
  1745. * The coefficient RAM must be configured prior to beginning of
  1746. * any context processing within the ASRC
  1747. */
  1748. ret = fsl_easrc_resampler_config(easrc);
  1749. if (ret) {
  1750. dev_err(dev, "resampler config failed\n");
  1751. goto disable_mem_clk;
  1752. }
  1753. for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
  1754. ctx = easrc->pair[i];
  1755. if (!ctx)
  1756. continue;
  1757. ctx_priv = ctx->private;
  1758. fsl_easrc_set_rs_ratio(ctx);
  1759. ctx_priv->out_missed_sample = ctx_priv->in_filled_sample *
  1760. ctx_priv->out_params.sample_rate /
  1761. ctx_priv->in_params.sample_rate;
  1762. if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate
  1763. % ctx_priv->in_params.sample_rate != 0)
  1764. ctx_priv->out_missed_sample += 1;
  1765. ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
  1766. ctx_priv->st1_coeff,
  1767. ctx_priv->st1_num_taps,
  1768. ctx_priv->st1_addexp);
  1769. if (ret)
  1770. goto disable_mem_clk;
  1771. ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
  1772. ctx_priv->st2_coeff,
  1773. ctx_priv->st2_num_taps,
  1774. ctx_priv->st2_addexp);
  1775. if (ret)
  1776. goto disable_mem_clk;
  1777. }
  1778. skip_load:
  1779. return 0;
  1780. disable_mem_clk:
  1781. clk_disable_unprepare(easrc->mem_clk);
  1782. return ret;
  1783. }
  1784. static const struct dev_pm_ops fsl_easrc_pm_ops = {
  1785. SET_RUNTIME_PM_OPS(fsl_easrc_runtime_suspend,
  1786. fsl_easrc_runtime_resume,
  1787. NULL)
  1788. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1789. pm_runtime_force_resume)
  1790. };
  1791. static struct platform_driver fsl_easrc_driver = {
  1792. .probe = fsl_easrc_probe,
  1793. .remove = fsl_easrc_remove,
  1794. .driver = {
  1795. .name = "fsl-easrc",
  1796. .pm = &fsl_easrc_pm_ops,
  1797. .of_match_table = fsl_easrc_dt_ids,
  1798. },
  1799. };
  1800. module_platform_driver(fsl_easrc_driver);
  1801. MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");
  1802. MODULE_LICENSE("GPL v2");