fsl_audmix.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
  4. *
  5. * Copyright 2017 NXP
  6. */
  7. #ifndef __FSL_AUDMIX_H
  8. #define __FSL_AUDMIX_H
  9. #define FSL_AUDMIX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  10. SNDRV_PCM_FMTBIT_S24_LE |\
  11. SNDRV_PCM_FMTBIT_S32_LE)
  12. /* AUDMIX Registers */
  13. #define FSL_AUDMIX_CTR 0x200 /* Control */
  14. #define FSL_AUDMIX_STR 0x204 /* Status */
  15. #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
  16. #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
  17. #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
  18. #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
  19. #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
  20. #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
  21. #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
  22. #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
  23. #define FSL_AUDMIX_ATIVAL1 0x22c /* Attenuation Initial Value */
  24. #define FSL_AUDMIX_ATSTPUP1 0x230 /* Attenuation step up factor */
  25. #define FSL_AUDMIX_ATSTPDN1 0x234 /* Attenuation step down factor */
  26. #define FSL_AUDMIX_ATSTPTGT1 0x238 /* Attenuation step target */
  27. #define FSL_AUDMIX_ATTNVAL1 0x23c /* Attenuation Value */
  28. #define FSL_AUDMIX_ATSTP1 0x240 /* Attenuation step number */
  29. /* AUDMIX Control Register */
  30. #define FSL_AUDMIX_CTR_MIXCLK_SHIFT 0
  31. #define FSL_AUDMIX_CTR_MIXCLK_MASK BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT)
  32. #define FSL_AUDMIX_CTR_MIXCLK(i) ((i) << FSL_AUDMIX_CTR_MIXCLK_SHIFT)
  33. #define FSL_AUDMIX_CTR_OUTSRC_SHIFT 1
  34. #define FSL_AUDMIX_CTR_OUTSRC_MASK (0x3 << FSL_AUDMIX_CTR_OUTSRC_SHIFT)
  35. #define FSL_AUDMIX_CTR_OUTSRC(i) (((i) << FSL_AUDMIX_CTR_OUTSRC_SHIFT)\
  36. & FSL_AUDMIX_CTR_OUTSRC_MASK)
  37. #define FSL_AUDMIX_CTR_OUTWIDTH_SHIFT 3
  38. #define FSL_AUDMIX_CTR_OUTWIDTH_MASK (0x7 << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)
  39. #define FSL_AUDMIX_CTR_OUTWIDTH(i) (((i) << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)\
  40. & FSL_AUDMIX_CTR_OUTWIDTH_MASK)
  41. #define FSL_AUDMIX_CTR_OUTCKPOL_SHIFT 6
  42. #define FSL_AUDMIX_CTR_OUTCKPOL_MASK BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
  43. #define FSL_AUDMIX_CTR_OUTCKPOL(i) ((i) << FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
  44. #define FSL_AUDMIX_CTR_MASKRTDF_SHIFT 7
  45. #define FSL_AUDMIX_CTR_MASKRTDF_MASK BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
  46. #define FSL_AUDMIX_CTR_MASKRTDF(i) ((i) << FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
  47. #define FSL_AUDMIX_CTR_MASKCKDF_SHIFT 8
  48. #define FSL_AUDMIX_CTR_MASKCKDF_MASK BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
  49. #define FSL_AUDMIX_CTR_MASKCKDF(i) ((i) << FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
  50. #define FSL_AUDMIX_CTR_SYNCMODE_SHIFT 9
  51. #define FSL_AUDMIX_CTR_SYNCMODE_MASK BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
  52. #define FSL_AUDMIX_CTR_SYNCMODE(i) ((i) << FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
  53. #define FSL_AUDMIX_CTR_SYNCSRC_SHIFT 10
  54. #define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
  55. #define FSL_AUDMIX_CTR_SYNCSRC(i) ((i) << FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
  56. /* AUDMIX Status Register */
  57. #define FSL_AUDMIX_STR_RATEDIFF BIT(0)
  58. #define FSL_AUDMIX_STR_CLKDIFF BIT(1)
  59. #define FSL_AUDMIX_STR_MIXSTAT_SHIFT 2
  60. #define FSL_AUDMIX_STR_MIXSTAT_MASK (0x3 << FSL_AUDMIX_STR_MIXSTAT_SHIFT)
  61. #define FSL_AUDMIX_STR_MIXSTAT(i) (((i) & FSL_AUDMIX_STR_MIXSTAT_MASK) \
  62. >> FSL_AUDMIX_STR_MIXSTAT_SHIFT)
  63. /* AUDMIX Attenuation Control Register */
  64. #define FSL_AUDMIX_ATCR_AT_EN BIT(0)
  65. #define FSL_AUDMIX_ATCR_AT_UPDN BIT(1)
  66. #define FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT 2
  67. #define FSL_AUDMIX_ATCR_ATSTPDFI_MASK \
  68. (0xfff << FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT)
  69. /* AUDMIX Attenuation Initial Value Register */
  70. #define FSL_AUDMIX_ATIVAL_ATINVAL_MASK 0x3FFFF
  71. /* AUDMIX Attenuation Step Up Factor Register */
  72. #define FSL_AUDMIX_ATSTPUP_ATSTEPUP_MASK 0x3FFFF
  73. /* AUDMIX Attenuation Step Down Factor Register */
  74. #define FSL_AUDMIX_ATSTPDN_ATSTEPDN_MASK 0x3FFFF
  75. /* AUDMIX Attenuation Step Target Register */
  76. #define FSL_AUDMIX_ATSTPTGT_ATSTPTG_MASK 0x3FFFF
  77. /* AUDMIX Attenuation Value Register */
  78. #define FSL_AUDMIX_ATTNVAL_ATCURVAL_MASK 0x3FFFF
  79. /* AUDMIX Attenuation Step Number Register */
  80. #define FSL_AUDMIX_ATSTP_STPCTR_MASK 0x3FFFF
  81. #define FSL_AUDMIX_MAX_DAIS 2
  82. struct fsl_audmix {
  83. struct platform_device *pdev;
  84. struct regmap *regmap;
  85. struct clk *ipg_clk;
  86. spinlock_t lock; /* Protect tdms */
  87. u8 tdms;
  88. };
  89. #endif /* __FSL_AUDMIX_H */