fsl_asrc.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
  4. //
  5. // Copyright (C) 2014 Freescale Semiconductor, Inc.
  6. //
  7. // Author: Nicolin Chen <[email protected]>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/module.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/dma/imx-dma.h>
  14. #include <linux/pm_runtime.h>
  15. #include <sound/dmaengine_pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include "fsl_asrc.h"
  18. #define IDEAL_RATIO_DECIMAL_DEPTH 26
  19. #define DIVIDER_NUM 64
  20. #define INIT_RETRY_NUM 50
  21. #define pair_err(fmt, ...) \
  22. dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
  23. #define pair_dbg(fmt, ...) \
  24. dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
  25. #define pair_warn(fmt, ...) \
  26. dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
  27. /* Corresponding to process_option */
  28. static unsigned int supported_asrc_rate[] = {
  29. 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
  30. 64000, 88200, 96000, 128000, 176400, 192000,
  31. };
  32. static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
  33. .count = ARRAY_SIZE(supported_asrc_rate),
  34. .list = supported_asrc_rate,
  35. };
  36. /*
  37. * The following tables map the relationship between asrc_inclk/asrc_outclk in
  38. * fsl_asrc.h and the registers of ASRCSR
  39. */
  40. static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
  41. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  42. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  43. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  44. };
  45. static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
  46. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  47. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  48. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  49. };
  50. /* i.MX53 uses the same map for input and output */
  51. static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
  52. /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
  53. 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
  54. 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
  55. 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
  56. };
  57. static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
  58. /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
  59. 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
  60. 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
  61. 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
  62. };
  63. /*
  64. * i.MX8QM/i.MX8QXP uses the same map for input and output.
  65. * clk_map_imx8qm[0] is for i.MX8QM asrc0
  66. * clk_map_imx8qm[1] is for i.MX8QM asrc1
  67. * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
  68. * clk_map_imx8qxp[1] is for i.MX8QXP asrc1
  69. */
  70. static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
  71. {
  72. 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
  73. 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  74. 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  75. },
  76. {
  77. 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
  78. 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  79. 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  80. },
  81. };
  82. static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
  83. {
  84. 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
  85. 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
  86. 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  87. },
  88. {
  89. 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
  90. 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  91. 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
  92. },
  93. };
  94. /*
  95. * According to RM, the divider range is 1 ~ 8,
  96. * prescaler is power of 2 from 1 ~ 128.
  97. */
  98. static int asrc_clk_divider[DIVIDER_NUM] = {
  99. 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
  100. 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
  101. 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
  102. 4, 8, 16, 32, 64, 128, 256, 512, /* divider = 4 */
  103. 5, 10, 20, 40, 80, 160, 320, 640, /* divider = 5 */
  104. 6, 12, 24, 48, 96, 192, 384, 768, /* divider = 6 */
  105. 7, 14, 28, 56, 112, 224, 448, 896, /* divider = 7 */
  106. 8, 16, 32, 64, 128, 256, 512, 1024, /* divider = 8 */
  107. };
  108. /*
  109. * Check if the divider is available for internal ratio mode
  110. */
  111. static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div)
  112. {
  113. u32 rem, i;
  114. u64 n;
  115. if (div)
  116. *div = 0;
  117. if (clk_rate == 0 || rate == 0)
  118. return false;
  119. n = clk_rate;
  120. rem = do_div(n, rate);
  121. if (div)
  122. *div = n;
  123. if (rem != 0)
  124. return false;
  125. for (i = 0; i < DIVIDER_NUM; i++) {
  126. if (n == asrc_clk_divider[i])
  127. break;
  128. }
  129. if (i == DIVIDER_NUM)
  130. return false;
  131. return true;
  132. }
  133. /**
  134. * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
  135. * @inrate: input sample rate
  136. * @outrate: output sample rate
  137. * @pre_proc: return value for pre-processing option
  138. * @post_proc: return value for post-processing option
  139. *
  140. * Make sure to exclude following unsupported cases before
  141. * calling this function:
  142. * 1) inrate > 8.125 * outrate
  143. * 2) inrate > 16.125 * outrate
  144. *
  145. */
  146. static void fsl_asrc_sel_proc(int inrate, int outrate,
  147. int *pre_proc, int *post_proc)
  148. {
  149. bool post_proc_cond2;
  150. bool post_proc_cond0;
  151. /* select pre_proc between [0, 2] */
  152. if (inrate * 8 > 33 * outrate)
  153. *pre_proc = 2;
  154. else if (inrate * 8 > 15 * outrate) {
  155. if (inrate > 152000)
  156. *pre_proc = 2;
  157. else
  158. *pre_proc = 1;
  159. } else if (inrate < 76000)
  160. *pre_proc = 0;
  161. else if (inrate > 152000)
  162. *pre_proc = 2;
  163. else
  164. *pre_proc = 1;
  165. /* Condition for selection of post-processing */
  166. post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
  167. (inrate > 56000 && outrate < 56000);
  168. post_proc_cond0 = inrate * 23 < outrate * 8;
  169. if (post_proc_cond2)
  170. *post_proc = 2;
  171. else if (post_proc_cond0)
  172. *post_proc = 0;
  173. else
  174. *post_proc = 1;
  175. }
  176. /**
  177. * fsl_asrc_request_pair - Request ASRC pair
  178. * @channels: number of channels
  179. * @pair: pointer to pair
  180. *
  181. * It assigns pair by the order of A->C->B because allocation of pair B,
  182. * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
  183. * while pair A and pair C are comparatively independent.
  184. */
  185. static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
  186. {
  187. enum asrc_pair_index index = ASRC_INVALID_PAIR;
  188. struct fsl_asrc *asrc = pair->asrc;
  189. struct device *dev = &asrc->pdev->dev;
  190. unsigned long lock_flags;
  191. int i, ret = 0;
  192. spin_lock_irqsave(&asrc->lock, lock_flags);
  193. for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
  194. if (asrc->pair[i] != NULL)
  195. continue;
  196. index = i;
  197. if (i != ASRC_PAIR_B)
  198. break;
  199. }
  200. if (index == ASRC_INVALID_PAIR) {
  201. dev_err(dev, "all pairs are busy now\n");
  202. ret = -EBUSY;
  203. } else if (asrc->channel_avail < channels) {
  204. dev_err(dev, "can't afford required channels: %d\n", channels);
  205. ret = -EINVAL;
  206. } else {
  207. asrc->channel_avail -= channels;
  208. asrc->pair[index] = pair;
  209. pair->channels = channels;
  210. pair->index = index;
  211. }
  212. spin_unlock_irqrestore(&asrc->lock, lock_flags);
  213. return ret;
  214. }
  215. /**
  216. * fsl_asrc_release_pair - Release ASRC pair
  217. * @pair: pair to release
  218. *
  219. * It clears the resource from asrc and releases the occupied channels.
  220. */
  221. static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
  222. {
  223. struct fsl_asrc *asrc = pair->asrc;
  224. enum asrc_pair_index index = pair->index;
  225. unsigned long lock_flags;
  226. /* Make sure the pair is disabled */
  227. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  228. ASRCTR_ASRCEi_MASK(index), 0);
  229. spin_lock_irqsave(&asrc->lock, lock_flags);
  230. asrc->channel_avail += pair->channels;
  231. asrc->pair[index] = NULL;
  232. pair->error = 0;
  233. spin_unlock_irqrestore(&asrc->lock, lock_flags);
  234. }
  235. /**
  236. * fsl_asrc_set_watermarks- configure input and output thresholds
  237. * @pair: pointer to pair
  238. * @in: input threshold
  239. * @out: output threshold
  240. */
  241. static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
  242. {
  243. struct fsl_asrc *asrc = pair->asrc;
  244. enum asrc_pair_index index = pair->index;
  245. regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
  246. ASRMCRi_EXTTHRSHi_MASK |
  247. ASRMCRi_INFIFO_THRESHOLD_MASK |
  248. ASRMCRi_OUTFIFO_THRESHOLD_MASK,
  249. ASRMCRi_EXTTHRSHi |
  250. ASRMCRi_INFIFO_THRESHOLD(in) |
  251. ASRMCRi_OUTFIFO_THRESHOLD(out));
  252. }
  253. /**
  254. * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate
  255. * @pair: pointer to pair
  256. * @div: divider
  257. *
  258. * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
  259. */
  260. static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
  261. {
  262. u32 ps;
  263. /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
  264. for (ps = 0; div > 8; ps++)
  265. div >>= 1;
  266. return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
  267. }
  268. /**
  269. * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only
  270. * @pair: pointer to pair
  271. * @inrate: input rate
  272. * @outrate: output rate
  273. *
  274. * The ratio is a 32-bit fixed point value with 26 fractional bits.
  275. */
  276. static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
  277. int inrate, int outrate)
  278. {
  279. struct fsl_asrc *asrc = pair->asrc;
  280. enum asrc_pair_index index = pair->index;
  281. unsigned long ratio;
  282. int i;
  283. if (!outrate) {
  284. pair_err("output rate should not be zero\n");
  285. return -EINVAL;
  286. }
  287. /* Calculate the intergal part of the ratio */
  288. ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
  289. /* ... and then the 26 depth decimal part */
  290. inrate %= outrate;
  291. for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
  292. inrate <<= 1;
  293. if (inrate < outrate)
  294. continue;
  295. ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
  296. inrate -= outrate;
  297. if (!inrate)
  298. break;
  299. }
  300. regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
  301. regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
  302. return 0;
  303. }
  304. /**
  305. * fsl_asrc_config_pair - Configure the assigned ASRC pair
  306. * @pair: pointer to pair
  307. * @use_ideal_rate: boolean configuration
  308. *
  309. * It configures those ASRC registers according to a configuration instance
  310. * of struct asrc_config which includes in/output sample rate, width, channel
  311. * and clock settings.
  312. *
  313. * Note:
  314. * The ideal ratio configuration can work with a flexible clock rate setting.
  315. * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
  316. * For a regular audio playback, the clock rate should not be slower than an
  317. * clock rate aligning with the output sample rate; For a use case requiring
  318. * faster conversion, set use_ideal_rate to have the faster speed.
  319. */
  320. static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
  321. {
  322. struct fsl_asrc_pair_priv *pair_priv = pair->private;
  323. struct asrc_config *config = pair_priv->config;
  324. struct fsl_asrc *asrc = pair->asrc;
  325. struct fsl_asrc_priv *asrc_priv = asrc->private;
  326. enum asrc_pair_index index = pair->index;
  327. enum asrc_word_width input_word_width;
  328. enum asrc_word_width output_word_width;
  329. u32 inrate, outrate, indiv, outdiv;
  330. u32 clk_index[2], div[2];
  331. u64 clk_rate;
  332. int in, out, channels;
  333. int pre_proc, post_proc;
  334. struct clk *clk;
  335. bool ideal, div_avail;
  336. if (!config) {
  337. pair_err("invalid pair config\n");
  338. return -EINVAL;
  339. }
  340. /* Validate channels */
  341. if (config->channel_num < 1 || config->channel_num > 10) {
  342. pair_err("does not support %d channels\n", config->channel_num);
  343. return -EINVAL;
  344. }
  345. switch (snd_pcm_format_width(config->input_format)) {
  346. case 8:
  347. input_word_width = ASRC_WIDTH_8_BIT;
  348. break;
  349. case 16:
  350. input_word_width = ASRC_WIDTH_16_BIT;
  351. break;
  352. case 24:
  353. input_word_width = ASRC_WIDTH_24_BIT;
  354. break;
  355. default:
  356. pair_err("does not support this input format, %d\n",
  357. config->input_format);
  358. return -EINVAL;
  359. }
  360. switch (snd_pcm_format_width(config->output_format)) {
  361. case 16:
  362. output_word_width = ASRC_WIDTH_16_BIT;
  363. break;
  364. case 24:
  365. output_word_width = ASRC_WIDTH_24_BIT;
  366. break;
  367. default:
  368. pair_err("does not support this output format, %d\n",
  369. config->output_format);
  370. return -EINVAL;
  371. }
  372. inrate = config->input_sample_rate;
  373. outrate = config->output_sample_rate;
  374. ideal = config->inclk == INCLK_NONE;
  375. /* Validate input and output sample rates */
  376. for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
  377. if (inrate == supported_asrc_rate[in])
  378. break;
  379. if (in == ARRAY_SIZE(supported_asrc_rate)) {
  380. pair_err("unsupported input sample rate: %dHz\n", inrate);
  381. return -EINVAL;
  382. }
  383. for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
  384. if (outrate == supported_asrc_rate[out])
  385. break;
  386. if (out == ARRAY_SIZE(supported_asrc_rate)) {
  387. pair_err("unsupported output sample rate: %dHz\n", outrate);
  388. return -EINVAL;
  389. }
  390. if ((outrate >= 5512 && outrate <= 30000) &&
  391. (outrate > 24 * inrate || inrate > 8 * outrate)) {
  392. pair_err("exceed supported ratio range [1/24, 8] for \
  393. inrate/outrate: %d/%d\n", inrate, outrate);
  394. return -EINVAL;
  395. }
  396. /* Validate input and output clock sources */
  397. clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
  398. clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
  399. /* We only have output clock for ideal ratio mode */
  400. clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
  401. clk_rate = clk_get_rate(clk);
  402. div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]);
  403. /*
  404. * The divider range is [1, 1024], defined by the hardware. For non-
  405. * ideal ratio configuration, clock rate has to be strictly aligned
  406. * with the sample rate. For ideal ratio configuration, clock rates
  407. * only result in different converting speeds. So remainder does not
  408. * matter, as long as we keep the divider within its valid range.
  409. */
  410. if (div[IN] == 0 || (!ideal && !div_avail)) {
  411. pair_err("failed to support input sample rate %dHz by asrck_%x\n",
  412. inrate, clk_index[ideal ? OUT : IN]);
  413. return -EINVAL;
  414. }
  415. div[IN] = min_t(u32, 1024, div[IN]);
  416. clk = asrc_priv->asrck_clk[clk_index[OUT]];
  417. clk_rate = clk_get_rate(clk);
  418. if (ideal && use_ideal_rate)
  419. div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]);
  420. else
  421. div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]);
  422. /* Output divider has the same limitation as the input one */
  423. if (div[OUT] == 0 || (!ideal && !div_avail)) {
  424. pair_err("failed to support output sample rate %dHz by asrck_%x\n",
  425. outrate, clk_index[OUT]);
  426. return -EINVAL;
  427. }
  428. div[OUT] = min_t(u32, 1024, div[OUT]);
  429. /* Set the channel number */
  430. channels = config->channel_num;
  431. if (asrc_priv->soc->channel_bits < 4)
  432. channels /= 2;
  433. /* Update channels for current pair */
  434. regmap_update_bits(asrc->regmap, REG_ASRCNCR,
  435. ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
  436. ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
  437. /* Default setting: Automatic selection for processing mode */
  438. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  439. ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
  440. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  441. ASRCTR_USRi_MASK(index), 0);
  442. /* Set the input and output clock sources */
  443. regmap_update_bits(asrc->regmap, REG_ASRCSR,
  444. ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
  445. ASRCSR_AICS(index, clk_index[IN]) |
  446. ASRCSR_AOCS(index, clk_index[OUT]));
  447. /* Calculate the input clock divisors */
  448. indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
  449. outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
  450. /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
  451. regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
  452. ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
  453. ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
  454. ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
  455. /* Implement word_width configurations */
  456. regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
  457. ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
  458. ASRMCR1i_OW16(output_word_width) |
  459. ASRMCR1i_IWD(input_word_width));
  460. /* Enable BUFFER STALL */
  461. regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
  462. ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
  463. /* Set default thresholds for input and output FIFO */
  464. fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
  465. ASRC_INPUTFIFO_THRESHOLD);
  466. /* Configure the following only for Ideal Ratio mode */
  467. if (!ideal)
  468. return 0;
  469. /* Clear ASTSx bit to use Ideal Ratio mode */
  470. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  471. ASRCTR_ATSi_MASK(index), 0);
  472. /* Enable Ideal Ratio mode */
  473. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  474. ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
  475. ASRCTR_IDR(index) | ASRCTR_USR(index));
  476. fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
  477. /* Apply configurations for pre- and post-processing */
  478. regmap_update_bits(asrc->regmap, REG_ASRCFG,
  479. ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
  480. ASRCFG_PREMOD(index, pre_proc) |
  481. ASRCFG_POSTMOD(index, post_proc));
  482. return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
  483. }
  484. /**
  485. * fsl_asrc_start_pair - Start the assigned ASRC pair
  486. * @pair: pointer to pair
  487. *
  488. * It enables the assigned pair and makes it stopped at the stall level.
  489. */
  490. static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
  491. {
  492. struct fsl_asrc *asrc = pair->asrc;
  493. enum asrc_pair_index index = pair->index;
  494. int reg, retry = INIT_RETRY_NUM, i;
  495. /* Enable the current pair */
  496. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  497. ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
  498. /* Wait for status of initialization */
  499. do {
  500. udelay(5);
  501. regmap_read(asrc->regmap, REG_ASRCFG, &reg);
  502. reg &= ASRCFG_INIRQi_MASK(index);
  503. } while (!reg && --retry);
  504. /* NOTE: Doesn't treat initialization timeout as an error */
  505. if (!retry)
  506. pair_warn("initialization isn't finished\n");
  507. /* Make the input fifo to ASRC STALL level */
  508. regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
  509. for (i = 0; i < pair->channels * 4; i++)
  510. regmap_write(asrc->regmap, REG_ASRDI(index), 0);
  511. /* Enable overload interrupt */
  512. regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
  513. }
  514. /**
  515. * fsl_asrc_stop_pair - Stop the assigned ASRC pair
  516. * @pair: pointer to pair
  517. */
  518. static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
  519. {
  520. struct fsl_asrc *asrc = pair->asrc;
  521. enum asrc_pair_index index = pair->index;
  522. /* Stop the current pair */
  523. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  524. ASRCTR_ASRCEi_MASK(index), 0);
  525. }
  526. /**
  527. * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction.
  528. * @pair: pointer to pair
  529. * @dir: DMA direction
  530. */
  531. static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair,
  532. bool dir)
  533. {
  534. struct fsl_asrc *asrc = pair->asrc;
  535. enum asrc_pair_index index = pair->index;
  536. char name[4];
  537. sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
  538. return dma_request_slave_channel(&asrc->pdev->dev, name);
  539. }
  540. static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
  541. struct snd_soc_dai *dai)
  542. {
  543. struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
  544. struct fsl_asrc_priv *asrc_priv = asrc->private;
  545. /* Odd channel number is not valid for older ASRC (channel_bits==3) */
  546. if (asrc_priv->soc->channel_bits == 3)
  547. snd_pcm_hw_constraint_step(substream->runtime, 0,
  548. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  549. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  550. SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
  551. }
  552. /* Select proper clock source for internal ratio mode */
  553. static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
  554. struct fsl_asrc_pair *pair,
  555. int in_rate,
  556. int out_rate)
  557. {
  558. struct fsl_asrc_pair_priv *pair_priv = pair->private;
  559. struct asrc_config *config = pair_priv->config;
  560. int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
  561. int clk_rate, clk_index;
  562. int i, j;
  563. rate[IN] = in_rate;
  564. rate[OUT] = out_rate;
  565. /* Select proper clock source for internal ratio mode */
  566. for (j = 0; j < 2; j++) {
  567. for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
  568. clk_index = asrc_priv->clk_map[j][i];
  569. clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
  570. /* Only match a perfect clock source with no remainder */
  571. if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL))
  572. break;
  573. }
  574. select_clk[j] = i;
  575. }
  576. /* Switch to ideal ratio mode if there is no proper clock source */
  577. if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) {
  578. select_clk[IN] = INCLK_NONE;
  579. select_clk[OUT] = OUTCLK_ASRCK1_CLK;
  580. }
  581. config->inclk = select_clk[IN];
  582. config->outclk = select_clk[OUT];
  583. }
  584. static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
  585. struct snd_pcm_hw_params *params,
  586. struct snd_soc_dai *dai)
  587. {
  588. struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
  589. struct fsl_asrc_priv *asrc_priv = asrc->private;
  590. struct snd_pcm_runtime *runtime = substream->runtime;
  591. struct fsl_asrc_pair *pair = runtime->private_data;
  592. struct fsl_asrc_pair_priv *pair_priv = pair->private;
  593. unsigned int channels = params_channels(params);
  594. unsigned int rate = params_rate(params);
  595. struct asrc_config config;
  596. int ret;
  597. ret = fsl_asrc_request_pair(channels, pair);
  598. if (ret) {
  599. dev_err(dai->dev, "fail to request asrc pair\n");
  600. return ret;
  601. }
  602. pair_priv->config = &config;
  603. config.pair = pair->index;
  604. config.channel_num = channels;
  605. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  606. config.input_format = params_format(params);
  607. config.output_format = asrc->asrc_format;
  608. config.input_sample_rate = rate;
  609. config.output_sample_rate = asrc->asrc_rate;
  610. } else {
  611. config.input_format = asrc->asrc_format;
  612. config.output_format = params_format(params);
  613. config.input_sample_rate = asrc->asrc_rate;
  614. config.output_sample_rate = rate;
  615. }
  616. fsl_asrc_select_clk(asrc_priv, pair,
  617. config.input_sample_rate,
  618. config.output_sample_rate);
  619. ret = fsl_asrc_config_pair(pair, false);
  620. if (ret) {
  621. dev_err(dai->dev, "fail to config asrc pair\n");
  622. return ret;
  623. }
  624. return 0;
  625. }
  626. static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
  627. struct snd_soc_dai *dai)
  628. {
  629. struct snd_pcm_runtime *runtime = substream->runtime;
  630. struct fsl_asrc_pair *pair = runtime->private_data;
  631. if (pair)
  632. fsl_asrc_release_pair(pair);
  633. return 0;
  634. }
  635. static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  636. struct snd_soc_dai *dai)
  637. {
  638. struct snd_pcm_runtime *runtime = substream->runtime;
  639. struct fsl_asrc_pair *pair = runtime->private_data;
  640. switch (cmd) {
  641. case SNDRV_PCM_TRIGGER_START:
  642. case SNDRV_PCM_TRIGGER_RESUME:
  643. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  644. fsl_asrc_start_pair(pair);
  645. break;
  646. case SNDRV_PCM_TRIGGER_STOP:
  647. case SNDRV_PCM_TRIGGER_SUSPEND:
  648. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  649. fsl_asrc_stop_pair(pair);
  650. break;
  651. default:
  652. return -EINVAL;
  653. }
  654. return 0;
  655. }
  656. static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
  657. .startup = fsl_asrc_dai_startup,
  658. .hw_params = fsl_asrc_dai_hw_params,
  659. .hw_free = fsl_asrc_dai_hw_free,
  660. .trigger = fsl_asrc_dai_trigger,
  661. };
  662. static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
  663. {
  664. struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
  665. snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
  666. &asrc->dma_params_rx);
  667. return 0;
  668. }
  669. #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
  670. SNDRV_PCM_FMTBIT_S16_LE | \
  671. SNDRV_PCM_FMTBIT_S24_3LE)
  672. static struct snd_soc_dai_driver fsl_asrc_dai = {
  673. .probe = fsl_asrc_dai_probe,
  674. .playback = {
  675. .stream_name = "ASRC-Playback",
  676. .channels_min = 1,
  677. .channels_max = 10,
  678. .rate_min = 5512,
  679. .rate_max = 192000,
  680. .rates = SNDRV_PCM_RATE_KNOT,
  681. .formats = FSL_ASRC_FORMATS |
  682. SNDRV_PCM_FMTBIT_S8,
  683. },
  684. .capture = {
  685. .stream_name = "ASRC-Capture",
  686. .channels_min = 1,
  687. .channels_max = 10,
  688. .rate_min = 5512,
  689. .rate_max = 192000,
  690. .rates = SNDRV_PCM_RATE_KNOT,
  691. .formats = FSL_ASRC_FORMATS,
  692. },
  693. .ops = &fsl_asrc_dai_ops,
  694. };
  695. static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
  696. {
  697. switch (reg) {
  698. case REG_ASRCTR:
  699. case REG_ASRIER:
  700. case REG_ASRCNCR:
  701. case REG_ASRCFG:
  702. case REG_ASRCSR:
  703. case REG_ASRCDR1:
  704. case REG_ASRCDR2:
  705. case REG_ASRSTR:
  706. case REG_ASRPM1:
  707. case REG_ASRPM2:
  708. case REG_ASRPM3:
  709. case REG_ASRPM4:
  710. case REG_ASRPM5:
  711. case REG_ASRTFR1:
  712. case REG_ASRCCR:
  713. case REG_ASRDOA:
  714. case REG_ASRDOB:
  715. case REG_ASRDOC:
  716. case REG_ASRIDRHA:
  717. case REG_ASRIDRLA:
  718. case REG_ASRIDRHB:
  719. case REG_ASRIDRLB:
  720. case REG_ASRIDRHC:
  721. case REG_ASRIDRLC:
  722. case REG_ASR76K:
  723. case REG_ASR56K:
  724. case REG_ASRMCRA:
  725. case REG_ASRFSTA:
  726. case REG_ASRMCRB:
  727. case REG_ASRFSTB:
  728. case REG_ASRMCRC:
  729. case REG_ASRFSTC:
  730. case REG_ASRMCR1A:
  731. case REG_ASRMCR1B:
  732. case REG_ASRMCR1C:
  733. return true;
  734. default:
  735. return false;
  736. }
  737. }
  738. static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
  739. {
  740. switch (reg) {
  741. case REG_ASRSTR:
  742. case REG_ASRDIA:
  743. case REG_ASRDIB:
  744. case REG_ASRDIC:
  745. case REG_ASRDOA:
  746. case REG_ASRDOB:
  747. case REG_ASRDOC:
  748. case REG_ASRFSTA:
  749. case REG_ASRFSTB:
  750. case REG_ASRFSTC:
  751. case REG_ASRCFG:
  752. return true;
  753. default:
  754. return false;
  755. }
  756. }
  757. static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
  758. {
  759. switch (reg) {
  760. case REG_ASRCTR:
  761. case REG_ASRIER:
  762. case REG_ASRCNCR:
  763. case REG_ASRCFG:
  764. case REG_ASRCSR:
  765. case REG_ASRCDR1:
  766. case REG_ASRCDR2:
  767. case REG_ASRSTR:
  768. case REG_ASRPM1:
  769. case REG_ASRPM2:
  770. case REG_ASRPM3:
  771. case REG_ASRPM4:
  772. case REG_ASRPM5:
  773. case REG_ASRTFR1:
  774. case REG_ASRCCR:
  775. case REG_ASRDIA:
  776. case REG_ASRDIB:
  777. case REG_ASRDIC:
  778. case REG_ASRIDRHA:
  779. case REG_ASRIDRLA:
  780. case REG_ASRIDRHB:
  781. case REG_ASRIDRLB:
  782. case REG_ASRIDRHC:
  783. case REG_ASRIDRLC:
  784. case REG_ASR76K:
  785. case REG_ASR56K:
  786. case REG_ASRMCRA:
  787. case REG_ASRMCRB:
  788. case REG_ASRMCRC:
  789. case REG_ASRMCR1A:
  790. case REG_ASRMCR1B:
  791. case REG_ASRMCR1C:
  792. return true;
  793. default:
  794. return false;
  795. }
  796. }
  797. static struct reg_default fsl_asrc_reg[] = {
  798. { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
  799. { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
  800. { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
  801. { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
  802. { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
  803. { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
  804. { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
  805. { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
  806. { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
  807. { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
  808. { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
  809. { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
  810. { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
  811. { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
  812. { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
  813. { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
  814. { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
  815. { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
  816. { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
  817. { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
  818. { REG_ASRMCR1C, 0x0000 },
  819. };
  820. static const struct regmap_config fsl_asrc_regmap_config = {
  821. .reg_bits = 32,
  822. .reg_stride = 4,
  823. .val_bits = 32,
  824. .max_register = REG_ASRMCR1C,
  825. .reg_defaults = fsl_asrc_reg,
  826. .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
  827. .readable_reg = fsl_asrc_readable_reg,
  828. .volatile_reg = fsl_asrc_volatile_reg,
  829. .writeable_reg = fsl_asrc_writeable_reg,
  830. .cache_type = REGCACHE_FLAT,
  831. };
  832. /**
  833. * fsl_asrc_init - Initialize ASRC registers with a default configuration
  834. * @asrc: ASRC context
  835. */
  836. static int fsl_asrc_init(struct fsl_asrc *asrc)
  837. {
  838. unsigned long ipg_rate;
  839. /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
  840. regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
  841. /* Disable interrupt by default */
  842. regmap_write(asrc->regmap, REG_ASRIER, 0x0);
  843. /* Apply recommended settings for parameters from Reference Manual */
  844. regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
  845. regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
  846. regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
  847. regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
  848. regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
  849. /* Base address for task queue FIFO. Set to 0x7C */
  850. regmap_update_bits(asrc->regmap, REG_ASRTFR1,
  851. ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
  852. /*
  853. * Set the period of the 76KHz and 56KHz sampling clocks based on
  854. * the ASRC processing clock.
  855. * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947
  856. */
  857. ipg_rate = clk_get_rate(asrc->ipg_clk);
  858. regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);
  859. return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);
  860. }
  861. /**
  862. * fsl_asrc_isr- Interrupt handler for ASRC
  863. * @irq: irq number
  864. * @dev_id: ASRC context
  865. */
  866. static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
  867. {
  868. struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
  869. struct device *dev = &asrc->pdev->dev;
  870. enum asrc_pair_index index;
  871. u32 status;
  872. regmap_read(asrc->regmap, REG_ASRSTR, &status);
  873. /* Clean overload error */
  874. regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
  875. /*
  876. * We here use dev_dbg() for all exceptions because ASRC itself does
  877. * not care if FIFO overflowed or underrun while a warning in the
  878. * interrupt would result a ridged conversion.
  879. */
  880. for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
  881. if (!asrc->pair[index])
  882. continue;
  883. if (status & ASRSTR_ATQOL) {
  884. asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
  885. dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
  886. }
  887. if (status & ASRSTR_AOOL(index)) {
  888. asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
  889. pair_dbg("Output Task Overload\n");
  890. }
  891. if (status & ASRSTR_AIOL(index)) {
  892. asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
  893. pair_dbg("Input Task Overload\n");
  894. }
  895. if (status & ASRSTR_AODO(index)) {
  896. asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
  897. pair_dbg("Output Data Buffer has overflowed\n");
  898. }
  899. if (status & ASRSTR_AIDU(index)) {
  900. asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
  901. pair_dbg("Input Data Buffer has underflowed\n");
  902. }
  903. }
  904. return IRQ_HANDLED;
  905. }
  906. static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
  907. {
  908. return REG_ASRDx(dir, index);
  909. }
  910. static int fsl_asrc_runtime_resume(struct device *dev);
  911. static int fsl_asrc_runtime_suspend(struct device *dev);
  912. static int fsl_asrc_probe(struct platform_device *pdev)
  913. {
  914. struct device_node *np = pdev->dev.of_node;
  915. struct fsl_asrc_priv *asrc_priv;
  916. struct fsl_asrc *asrc;
  917. struct resource *res;
  918. void __iomem *regs;
  919. int irq, ret, i;
  920. u32 asrc_fmt = 0;
  921. u32 map_idx;
  922. char tmp[16];
  923. u32 width;
  924. asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
  925. if (!asrc)
  926. return -ENOMEM;
  927. asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
  928. if (!asrc_priv)
  929. return -ENOMEM;
  930. asrc->pdev = pdev;
  931. asrc->private = asrc_priv;
  932. /* Get the addresses and IRQ */
  933. regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  934. if (IS_ERR(regs))
  935. return PTR_ERR(regs);
  936. asrc->paddr = res->start;
  937. asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config);
  938. if (IS_ERR(asrc->regmap)) {
  939. dev_err(&pdev->dev, "failed to init regmap\n");
  940. return PTR_ERR(asrc->regmap);
  941. }
  942. irq = platform_get_irq(pdev, 0);
  943. if (irq < 0)
  944. return irq;
  945. ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
  946. dev_name(&pdev->dev), asrc);
  947. if (ret) {
  948. dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
  949. return ret;
  950. }
  951. asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
  952. if (IS_ERR(asrc->mem_clk)) {
  953. dev_err(&pdev->dev, "failed to get mem clock\n");
  954. return PTR_ERR(asrc->mem_clk);
  955. }
  956. asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  957. if (IS_ERR(asrc->ipg_clk)) {
  958. dev_err(&pdev->dev, "failed to get ipg clock\n");
  959. return PTR_ERR(asrc->ipg_clk);
  960. }
  961. asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
  962. if (IS_ERR(asrc->spba_clk))
  963. dev_warn(&pdev->dev, "failed to get spba clock\n");
  964. for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
  965. sprintf(tmp, "asrck_%x", i);
  966. asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
  967. if (IS_ERR(asrc_priv->asrck_clk[i])) {
  968. dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
  969. return PTR_ERR(asrc_priv->asrck_clk[i]);
  970. }
  971. }
  972. asrc_priv->soc = of_device_get_match_data(&pdev->dev);
  973. asrc->use_edma = asrc_priv->soc->use_edma;
  974. asrc->get_dma_channel = fsl_asrc_get_dma_channel;
  975. asrc->request_pair = fsl_asrc_request_pair;
  976. asrc->release_pair = fsl_asrc_release_pair;
  977. asrc->get_fifo_addr = fsl_asrc_get_fifo_addr;
  978. asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv);
  979. if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
  980. asrc_priv->clk_map[IN] = input_clk_map_imx35;
  981. asrc_priv->clk_map[OUT] = output_clk_map_imx35;
  982. } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
  983. asrc_priv->clk_map[IN] = input_clk_map_imx53;
  984. asrc_priv->clk_map[OUT] = output_clk_map_imx53;
  985. } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
  986. of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
  987. ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
  988. if (ret) {
  989. dev_err(&pdev->dev, "failed to get clk map index\n");
  990. return ret;
  991. }
  992. if (map_idx > 1) {
  993. dev_err(&pdev->dev, "unsupported clk map index\n");
  994. return -EINVAL;
  995. }
  996. if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
  997. asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
  998. asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
  999. } else {
  1000. asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
  1001. asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
  1002. }
  1003. }
  1004. asrc->channel_avail = 10;
  1005. ret = of_property_read_u32(np, "fsl,asrc-rate",
  1006. &asrc->asrc_rate);
  1007. if (ret) {
  1008. dev_err(&pdev->dev, "failed to get output rate\n");
  1009. return ret;
  1010. }
  1011. ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
  1012. asrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
  1013. if (ret) {
  1014. ret = of_property_read_u32(np, "fsl,asrc-width", &width);
  1015. if (ret) {
  1016. dev_err(&pdev->dev, "failed to decide output format\n");
  1017. return ret;
  1018. }
  1019. switch (width) {
  1020. case 16:
  1021. asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
  1022. break;
  1023. case 24:
  1024. asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
  1025. break;
  1026. default:
  1027. dev_warn(&pdev->dev,
  1028. "unsupported width, use default S24_LE\n");
  1029. asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
  1030. break;
  1031. }
  1032. }
  1033. if (!(FSL_ASRC_FORMATS & pcm_format_to_bits(asrc->asrc_format))) {
  1034. dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n");
  1035. asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
  1036. }
  1037. platform_set_drvdata(pdev, asrc);
  1038. spin_lock_init(&asrc->lock);
  1039. pm_runtime_enable(&pdev->dev);
  1040. if (!pm_runtime_enabled(&pdev->dev)) {
  1041. ret = fsl_asrc_runtime_resume(&pdev->dev);
  1042. if (ret)
  1043. goto err_pm_disable;
  1044. }
  1045. ret = pm_runtime_resume_and_get(&pdev->dev);
  1046. if (ret < 0)
  1047. goto err_pm_get_sync;
  1048. ret = fsl_asrc_init(asrc);
  1049. if (ret) {
  1050. dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
  1051. goto err_pm_get_sync;
  1052. }
  1053. ret = pm_runtime_put_sync(&pdev->dev);
  1054. if (ret < 0 && ret != -ENOSYS)
  1055. goto err_pm_get_sync;
  1056. ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
  1057. &fsl_asrc_dai, 1);
  1058. if (ret) {
  1059. dev_err(&pdev->dev, "failed to register ASoC DAI\n");
  1060. goto err_pm_get_sync;
  1061. }
  1062. return 0;
  1063. err_pm_get_sync:
  1064. if (!pm_runtime_status_suspended(&pdev->dev))
  1065. fsl_asrc_runtime_suspend(&pdev->dev);
  1066. err_pm_disable:
  1067. pm_runtime_disable(&pdev->dev);
  1068. return ret;
  1069. }
  1070. static int fsl_asrc_remove(struct platform_device *pdev)
  1071. {
  1072. pm_runtime_disable(&pdev->dev);
  1073. if (!pm_runtime_status_suspended(&pdev->dev))
  1074. fsl_asrc_runtime_suspend(&pdev->dev);
  1075. return 0;
  1076. }
  1077. static int fsl_asrc_runtime_resume(struct device *dev)
  1078. {
  1079. struct fsl_asrc *asrc = dev_get_drvdata(dev);
  1080. struct fsl_asrc_priv *asrc_priv = asrc->private;
  1081. int reg, retry = INIT_RETRY_NUM;
  1082. int i, ret;
  1083. u32 asrctr;
  1084. ret = clk_prepare_enable(asrc->mem_clk);
  1085. if (ret)
  1086. return ret;
  1087. ret = clk_prepare_enable(asrc->ipg_clk);
  1088. if (ret)
  1089. goto disable_mem_clk;
  1090. if (!IS_ERR(asrc->spba_clk)) {
  1091. ret = clk_prepare_enable(asrc->spba_clk);
  1092. if (ret)
  1093. goto disable_ipg_clk;
  1094. }
  1095. for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
  1096. ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
  1097. if (ret)
  1098. goto disable_asrck_clk;
  1099. }
  1100. /* Stop all pairs provisionally */
  1101. regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
  1102. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  1103. ASRCTR_ASRCEi_ALL_MASK, 0);
  1104. /* Restore all registers */
  1105. regcache_cache_only(asrc->regmap, false);
  1106. regcache_mark_dirty(asrc->regmap);
  1107. regcache_sync(asrc->regmap);
  1108. regmap_update_bits(asrc->regmap, REG_ASRCFG,
  1109. ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
  1110. ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
  1111. /* Restart enabled pairs */
  1112. regmap_update_bits(asrc->regmap, REG_ASRCTR,
  1113. ASRCTR_ASRCEi_ALL_MASK, asrctr);
  1114. /* Wait for status of initialization for all enabled pairs */
  1115. do {
  1116. udelay(5);
  1117. regmap_read(asrc->regmap, REG_ASRCFG, &reg);
  1118. reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7;
  1119. } while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry);
  1120. /*
  1121. * NOTE: Doesn't treat initialization timeout as an error
  1122. * Some of the pairs may success, then still can continue.
  1123. */
  1124. if (!retry) {
  1125. for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
  1126. if ((asrctr & ASRCTR_ASRCEi_MASK(i)) && !(reg & (1 << i)))
  1127. dev_warn(dev, "Pair %c initialization isn't finished\n", 'A' + i);
  1128. }
  1129. }
  1130. return 0;
  1131. disable_asrck_clk:
  1132. for (i--; i >= 0; i--)
  1133. clk_disable_unprepare(asrc_priv->asrck_clk[i]);
  1134. if (!IS_ERR(asrc->spba_clk))
  1135. clk_disable_unprepare(asrc->spba_clk);
  1136. disable_ipg_clk:
  1137. clk_disable_unprepare(asrc->ipg_clk);
  1138. disable_mem_clk:
  1139. clk_disable_unprepare(asrc->mem_clk);
  1140. return ret;
  1141. }
  1142. static int fsl_asrc_runtime_suspend(struct device *dev)
  1143. {
  1144. struct fsl_asrc *asrc = dev_get_drvdata(dev);
  1145. struct fsl_asrc_priv *asrc_priv = asrc->private;
  1146. int i;
  1147. regmap_read(asrc->regmap, REG_ASRCFG,
  1148. &asrc_priv->regcache_cfg);
  1149. regcache_cache_only(asrc->regmap, true);
  1150. for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
  1151. clk_disable_unprepare(asrc_priv->asrck_clk[i]);
  1152. if (!IS_ERR(asrc->spba_clk))
  1153. clk_disable_unprepare(asrc->spba_clk);
  1154. clk_disable_unprepare(asrc->ipg_clk);
  1155. clk_disable_unprepare(asrc->mem_clk);
  1156. return 0;
  1157. }
  1158. static const struct dev_pm_ops fsl_asrc_pm = {
  1159. SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
  1160. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1161. pm_runtime_force_resume)
  1162. };
  1163. static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
  1164. .use_edma = false,
  1165. .channel_bits = 3,
  1166. };
  1167. static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
  1168. .use_edma = false,
  1169. .channel_bits = 4,
  1170. };
  1171. static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
  1172. .use_edma = true,
  1173. .channel_bits = 4,
  1174. };
  1175. static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
  1176. .use_edma = true,
  1177. .channel_bits = 4,
  1178. };
  1179. static const struct of_device_id fsl_asrc_ids[] = {
  1180. { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
  1181. { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
  1182. { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
  1183. { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
  1184. {}
  1185. };
  1186. MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
  1187. static struct platform_driver fsl_asrc_driver = {
  1188. .probe = fsl_asrc_probe,
  1189. .remove = fsl_asrc_remove,
  1190. .driver = {
  1191. .name = "fsl-asrc",
  1192. .of_match_table = fsl_asrc_ids,
  1193. .pm = &fsl_asrc_pm,
  1194. },
  1195. };
  1196. module_platform_driver(fsl_asrc_driver);
  1197. MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
  1198. MODULE_AUTHOR("Nicolin Chen <[email protected]>");
  1199. MODULE_ALIAS("platform:fsl-asrc");
  1200. MODULE_LICENSE("GPL v2");