wm9090.h 40 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ALSA SoC WM9090 driver
  4. *
  5. * Copyright 2009 Wolfson Microelectronics
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #ifndef __WM9090_H
  10. #define __WM9090_H
  11. /*
  12. * Register values.
  13. */
  14. #define WM9090_SOFTWARE_RESET 0x00
  15. #define WM9090_POWER_MANAGEMENT_1 0x01
  16. #define WM9090_POWER_MANAGEMENT_2 0x02
  17. #define WM9090_POWER_MANAGEMENT_3 0x03
  18. #define WM9090_CLOCKING_1 0x06
  19. #define WM9090_IN1_LINE_CONTROL 0x16
  20. #define WM9090_IN2_LINE_CONTROL 0x17
  21. #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
  22. #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
  23. #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
  24. #define WM9090_IN2_LINE_INPUT_B_VOLUME 0x1B
  25. #define WM9090_LEFT_OUTPUT_VOLUME 0x1C
  26. #define WM9090_RIGHT_OUTPUT_VOLUME 0x1D
  27. #define WM9090_SPKMIXL_ATTENUATION 0x22
  28. #define WM9090_SPKOUT_MIXERS 0x24
  29. #define WM9090_CLASSD3 0x25
  30. #define WM9090_SPEAKER_VOLUME_LEFT 0x26
  31. #define WM9090_OUTPUT_MIXER1 0x2D
  32. #define WM9090_OUTPUT_MIXER2 0x2E
  33. #define WM9090_OUTPUT_MIXER3 0x2F
  34. #define WM9090_OUTPUT_MIXER4 0x30
  35. #define WM9090_SPEAKER_MIXER 0x36
  36. #define WM9090_ANTIPOP2 0x39
  37. #define WM9090_WRITE_SEQUENCER_0 0x46
  38. #define WM9090_WRITE_SEQUENCER_1 0x47
  39. #define WM9090_WRITE_SEQUENCER_2 0x48
  40. #define WM9090_WRITE_SEQUENCER_3 0x49
  41. #define WM9090_WRITE_SEQUENCER_4 0x4A
  42. #define WM9090_WRITE_SEQUENCER_5 0x4B
  43. #define WM9090_CHARGE_PUMP_1 0x4C
  44. #define WM9090_DC_SERVO_0 0x54
  45. #define WM9090_DC_SERVO_1 0x55
  46. #define WM9090_DC_SERVO_3 0x57
  47. #define WM9090_DC_SERVO_READBACK_0 0x58
  48. #define WM9090_DC_SERVO_READBACK_1 0x59
  49. #define WM9090_DC_SERVO_READBACK_2 0x5A
  50. #define WM9090_ANALOGUE_HP_0 0x60
  51. #define WM9090_AGC_CONTROL_0 0x62
  52. #define WM9090_AGC_CONTROL_1 0x63
  53. #define WM9090_AGC_CONTROL_2 0x64
  54. #define WM9090_REGISTER_COUNT 40
  55. #define WM9090_MAX_REGISTER 0x64
  56. /*
  57. * Field Definitions.
  58. */
  59. /*
  60. * R0 (0x00) - Software Reset
  61. */
  62. #define WM9090_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
  63. #define WM9090_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
  64. #define WM9090_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
  65. /*
  66. * R1 (0x01) - Power Management (1)
  67. */
  68. #define WM9090_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
  69. #define WM9090_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
  70. #define WM9090_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */
  71. #define WM9090_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
  72. #define WM9090_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
  73. #define WM9090_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
  74. #define WM9090_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */
  75. #define WM9090_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
  76. #define WM9090_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
  77. #define WM9090_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
  78. #define WM9090_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */
  79. #define WM9090_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
  80. #define WM9090_OSC_ENA 0x0008 /* OSC_ENA */
  81. #define WM9090_OSC_ENA_MASK 0x0008 /* OSC_ENA */
  82. #define WM9090_OSC_ENA_SHIFT 3 /* OSC_ENA */
  83. #define WM9090_OSC_ENA_WIDTH 1 /* OSC_ENA */
  84. #define WM9090_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
  85. #define WM9090_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */
  86. #define WM9090_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */
  87. #define WM9090_BIAS_ENA 0x0001 /* BIAS_ENA */
  88. #define WM9090_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
  89. #define WM9090_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
  90. #define WM9090_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
  91. /*
  92. * R2 (0x02) - Power Management (2)
  93. */
  94. #define WM9090_TSHUT 0x8000 /* TSHUT */
  95. #define WM9090_TSHUT_MASK 0x8000 /* TSHUT */
  96. #define WM9090_TSHUT_SHIFT 15 /* TSHUT */
  97. #define WM9090_TSHUT_WIDTH 1 /* TSHUT */
  98. #define WM9090_TSHUT_ENA 0x4000 /* TSHUT_ENA */
  99. #define WM9090_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
  100. #define WM9090_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
  101. #define WM9090_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
  102. #define WM9090_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
  103. #define WM9090_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
  104. #define WM9090_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
  105. #define WM9090_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
  106. #define WM9090_IN1A_ENA 0x0080 /* IN1A_ENA */
  107. #define WM9090_IN1A_ENA_MASK 0x0080 /* IN1A_ENA */
  108. #define WM9090_IN1A_ENA_SHIFT 7 /* IN1A_ENA */
  109. #define WM9090_IN1A_ENA_WIDTH 1 /* IN1A_ENA */
  110. #define WM9090_IN1B_ENA 0x0040 /* IN1B_ENA */
  111. #define WM9090_IN1B_ENA_MASK 0x0040 /* IN1B_ENA */
  112. #define WM9090_IN1B_ENA_SHIFT 6 /* IN1B_ENA */
  113. #define WM9090_IN1B_ENA_WIDTH 1 /* IN1B_ENA */
  114. #define WM9090_IN2A_ENA 0x0020 /* IN2A_ENA */
  115. #define WM9090_IN2A_ENA_MASK 0x0020 /* IN2A_ENA */
  116. #define WM9090_IN2A_ENA_SHIFT 5 /* IN2A_ENA */
  117. #define WM9090_IN2A_ENA_WIDTH 1 /* IN2A_ENA */
  118. #define WM9090_IN2B_ENA 0x0010 /* IN2B_ENA */
  119. #define WM9090_IN2B_ENA_MASK 0x0010 /* IN2B_ENA */
  120. #define WM9090_IN2B_ENA_SHIFT 4 /* IN2B_ENA */
  121. #define WM9090_IN2B_ENA_WIDTH 1 /* IN2B_ENA */
  122. /*
  123. * R3 (0x03) - Power Management (3)
  124. */
  125. #define WM9090_AGC_ENA 0x4000 /* AGC_ENA */
  126. #define WM9090_AGC_ENA_MASK 0x4000 /* AGC_ENA */
  127. #define WM9090_AGC_ENA_SHIFT 14 /* AGC_ENA */
  128. #define WM9090_AGC_ENA_WIDTH 1 /* AGC_ENA */
  129. #define WM9090_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
  130. #define WM9090_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
  131. #define WM9090_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */
  132. #define WM9090_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */
  133. #define WM9090_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
  134. #define WM9090_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
  135. #define WM9090_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */
  136. #define WM9090_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
  137. #define WM9090_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
  138. #define WM9090_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
  139. #define WM9090_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */
  140. #define WM9090_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
  141. #define WM9090_SPKMIX_ENA 0x0008 /* SPKMIX_ENA */
  142. #define WM9090_SPKMIX_ENA_MASK 0x0008 /* SPKMIX_ENA */
  143. #define WM9090_SPKMIX_ENA_SHIFT 3 /* SPKMIX_ENA */
  144. #define WM9090_SPKMIX_ENA_WIDTH 1 /* SPKMIX_ENA */
  145. /*
  146. * R6 (0x06) - Clocking 1
  147. */
  148. #define WM9090_TOCLK_RATE 0x8000 /* TOCLK_RATE */
  149. #define WM9090_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
  150. #define WM9090_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
  151. #define WM9090_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
  152. #define WM9090_TOCLK_ENA 0x4000 /* TOCLK_ENA */
  153. #define WM9090_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
  154. #define WM9090_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
  155. #define WM9090_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
  156. /*
  157. * R22 (0x16) - IN1 Line Control
  158. */
  159. #define WM9090_IN1_DIFF 0x0002 /* IN1_DIFF */
  160. #define WM9090_IN1_DIFF_MASK 0x0002 /* IN1_DIFF */
  161. #define WM9090_IN1_DIFF_SHIFT 1 /* IN1_DIFF */
  162. #define WM9090_IN1_DIFF_WIDTH 1 /* IN1_DIFF */
  163. #define WM9090_IN1_CLAMP 0x0001 /* IN1_CLAMP */
  164. #define WM9090_IN1_CLAMP_MASK 0x0001 /* IN1_CLAMP */
  165. #define WM9090_IN1_CLAMP_SHIFT 0 /* IN1_CLAMP */
  166. #define WM9090_IN1_CLAMP_WIDTH 1 /* IN1_CLAMP */
  167. /*
  168. * R23 (0x17) - IN2 Line Control
  169. */
  170. #define WM9090_IN2_DIFF 0x0002 /* IN2_DIFF */
  171. #define WM9090_IN2_DIFF_MASK 0x0002 /* IN2_DIFF */
  172. #define WM9090_IN2_DIFF_SHIFT 1 /* IN2_DIFF */
  173. #define WM9090_IN2_DIFF_WIDTH 1 /* IN2_DIFF */
  174. #define WM9090_IN2_CLAMP 0x0001 /* IN2_CLAMP */
  175. #define WM9090_IN2_CLAMP_MASK 0x0001 /* IN2_CLAMP */
  176. #define WM9090_IN2_CLAMP_SHIFT 0 /* IN2_CLAMP */
  177. #define WM9090_IN2_CLAMP_WIDTH 1 /* IN2_CLAMP */
  178. /*
  179. * R24 (0x18) - IN1 Line Input A Volume
  180. */
  181. #define WM9090_IN1_VU 0x0100 /* IN1_VU */
  182. #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
  183. #define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */
  184. #define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */
  185. #define WM9090_IN1A_MUTE 0x0080 /* IN1A_MUTE */
  186. #define WM9090_IN1A_MUTE_MASK 0x0080 /* IN1A_MUTE */
  187. #define WM9090_IN1A_MUTE_SHIFT 7 /* IN1A_MUTE */
  188. #define WM9090_IN1A_MUTE_WIDTH 1 /* IN1A_MUTE */
  189. #define WM9090_IN1A_ZC 0x0040 /* IN1A_ZC */
  190. #define WM9090_IN1A_ZC_MASK 0x0040 /* IN1A_ZC */
  191. #define WM9090_IN1A_ZC_SHIFT 6 /* IN1A_ZC */
  192. #define WM9090_IN1A_ZC_WIDTH 1 /* IN1A_ZC */
  193. #define WM9090_IN1A_VOL_MASK 0x0007 /* IN1A_VOL - [2:0] */
  194. #define WM9090_IN1A_VOL_SHIFT 0 /* IN1A_VOL - [2:0] */
  195. #define WM9090_IN1A_VOL_WIDTH 3 /* IN1A_VOL - [2:0] */
  196. /*
  197. * R25 (0x19) - IN1 Line Input B Volume
  198. */
  199. #define WM9090_IN1_VU 0x0100 /* IN1_VU */
  200. #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
  201. #define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */
  202. #define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */
  203. #define WM9090_IN1B_MUTE 0x0080 /* IN1B_MUTE */
  204. #define WM9090_IN1B_MUTE_MASK 0x0080 /* IN1B_MUTE */
  205. #define WM9090_IN1B_MUTE_SHIFT 7 /* IN1B_MUTE */
  206. #define WM9090_IN1B_MUTE_WIDTH 1 /* IN1B_MUTE */
  207. #define WM9090_IN1B_ZC 0x0040 /* IN1B_ZC */
  208. #define WM9090_IN1B_ZC_MASK 0x0040 /* IN1B_ZC */
  209. #define WM9090_IN1B_ZC_SHIFT 6 /* IN1B_ZC */
  210. #define WM9090_IN1B_ZC_WIDTH 1 /* IN1B_ZC */
  211. #define WM9090_IN1B_VOL_MASK 0x0007 /* IN1B_VOL - [2:0] */
  212. #define WM9090_IN1B_VOL_SHIFT 0 /* IN1B_VOL - [2:0] */
  213. #define WM9090_IN1B_VOL_WIDTH 3 /* IN1B_VOL - [2:0] */
  214. /*
  215. * R26 (0x1A) - IN2 Line Input A Volume
  216. */
  217. #define WM9090_IN2_VU 0x0100 /* IN2_VU */
  218. #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
  219. #define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */
  220. #define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */
  221. #define WM9090_IN2A_MUTE 0x0080 /* IN2A_MUTE */
  222. #define WM9090_IN2A_MUTE_MASK 0x0080 /* IN2A_MUTE */
  223. #define WM9090_IN2A_MUTE_SHIFT 7 /* IN2A_MUTE */
  224. #define WM9090_IN2A_MUTE_WIDTH 1 /* IN2A_MUTE */
  225. #define WM9090_IN2A_ZC 0x0040 /* IN2A_ZC */
  226. #define WM9090_IN2A_ZC_MASK 0x0040 /* IN2A_ZC */
  227. #define WM9090_IN2A_ZC_SHIFT 6 /* IN2A_ZC */
  228. #define WM9090_IN2A_ZC_WIDTH 1 /* IN2A_ZC */
  229. #define WM9090_IN2A_VOL_MASK 0x0007 /* IN2A_VOL - [2:0] */
  230. #define WM9090_IN2A_VOL_SHIFT 0 /* IN2A_VOL - [2:0] */
  231. #define WM9090_IN2A_VOL_WIDTH 3 /* IN2A_VOL - [2:0] */
  232. /*
  233. * R27 (0x1B) - IN2 Line Input B Volume
  234. */
  235. #define WM9090_IN2_VU 0x0100 /* IN2_VU */
  236. #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
  237. #define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */
  238. #define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */
  239. #define WM9090_IN2B_MUTE 0x0080 /* IN2B_MUTE */
  240. #define WM9090_IN2B_MUTE_MASK 0x0080 /* IN2B_MUTE */
  241. #define WM9090_IN2B_MUTE_SHIFT 7 /* IN2B_MUTE */
  242. #define WM9090_IN2B_MUTE_WIDTH 1 /* IN2B_MUTE */
  243. #define WM9090_IN2B_ZC 0x0040 /* IN2B_ZC */
  244. #define WM9090_IN2B_ZC_MASK 0x0040 /* IN2B_ZC */
  245. #define WM9090_IN2B_ZC_SHIFT 6 /* IN2B_ZC */
  246. #define WM9090_IN2B_ZC_WIDTH 1 /* IN2B_ZC */
  247. #define WM9090_IN2B_VOL_MASK 0x0007 /* IN2B_VOL - [2:0] */
  248. #define WM9090_IN2B_VOL_SHIFT 0 /* IN2B_VOL - [2:0] */
  249. #define WM9090_IN2B_VOL_WIDTH 3 /* IN2B_VOL - [2:0] */
  250. /*
  251. * R28 (0x1C) - Left Output Volume
  252. */
  253. #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
  254. #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
  255. #define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
  256. #define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
  257. #define WM9090_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
  258. #define WM9090_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
  259. #define WM9090_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
  260. #define WM9090_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
  261. #define WM9090_HPOUT1L_MUTE 0x0040 /* HPOUT1L_MUTE */
  262. #define WM9090_HPOUT1L_MUTE_MASK 0x0040 /* HPOUT1L_MUTE */
  263. #define WM9090_HPOUT1L_MUTE_SHIFT 6 /* HPOUT1L_MUTE */
  264. #define WM9090_HPOUT1L_MUTE_WIDTH 1 /* HPOUT1L_MUTE */
  265. #define WM9090_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
  266. #define WM9090_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
  267. #define WM9090_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
  268. /*
  269. * R29 (0x1D) - Right Output Volume
  270. */
  271. #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
  272. #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
  273. #define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
  274. #define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
  275. #define WM9090_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
  276. #define WM9090_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
  277. #define WM9090_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
  278. #define WM9090_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
  279. #define WM9090_HPOUT1R_MUTE 0x0040 /* HPOUT1R_MUTE */
  280. #define WM9090_HPOUT1R_MUTE_MASK 0x0040 /* HPOUT1R_MUTE */
  281. #define WM9090_HPOUT1R_MUTE_SHIFT 6 /* HPOUT1R_MUTE */
  282. #define WM9090_HPOUT1R_MUTE_WIDTH 1 /* HPOUT1R_MUTE */
  283. #define WM9090_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
  284. #define WM9090_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
  285. #define WM9090_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
  286. /*
  287. * R34 (0x22) - SPKMIXL Attenuation
  288. */
  289. #define WM9090_SPKMIX_MUTE 0x0100 /* SPKMIX_MUTE */
  290. #define WM9090_SPKMIX_MUTE_MASK 0x0100 /* SPKMIX_MUTE */
  291. #define WM9090_SPKMIX_MUTE_SHIFT 8 /* SPKMIX_MUTE */
  292. #define WM9090_SPKMIX_MUTE_WIDTH 1 /* SPKMIX_MUTE */
  293. #define WM9090_IN1A_SPKMIX_VOL_MASK 0x00C0 /* IN1A_SPKMIX_VOL - [7:6] */
  294. #define WM9090_IN1A_SPKMIX_VOL_SHIFT 6 /* IN1A_SPKMIX_VOL - [7:6] */
  295. #define WM9090_IN1A_SPKMIX_VOL_WIDTH 2 /* IN1A_SPKMIX_VOL - [7:6] */
  296. #define WM9090_IN1B_SPKMIX_VOL_MASK 0x0030 /* IN1B_SPKMIX_VOL - [5:4] */
  297. #define WM9090_IN1B_SPKMIX_VOL_SHIFT 4 /* IN1B_SPKMIX_VOL - [5:4] */
  298. #define WM9090_IN1B_SPKMIX_VOL_WIDTH 2 /* IN1B_SPKMIX_VOL - [5:4] */
  299. #define WM9090_IN2A_SPKMIX_VOL_MASK 0x000C /* IN2A_SPKMIX_VOL - [3:2] */
  300. #define WM9090_IN2A_SPKMIX_VOL_SHIFT 2 /* IN2A_SPKMIX_VOL - [3:2] */
  301. #define WM9090_IN2A_SPKMIX_VOL_WIDTH 2 /* IN2A_SPKMIX_VOL - [3:2] */
  302. #define WM9090_IN2B_SPKMIX_VOL_MASK 0x0003 /* IN2B_SPKMIX_VOL - [1:0] */
  303. #define WM9090_IN2B_SPKMIX_VOL_SHIFT 0 /* IN2B_SPKMIX_VOL - [1:0] */
  304. #define WM9090_IN2B_SPKMIX_VOL_WIDTH 2 /* IN2B_SPKMIX_VOL - [1:0] */
  305. /*
  306. * R36 (0x24) - SPKOUT Mixers
  307. */
  308. #define WM9090_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
  309. #define WM9090_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
  310. #define WM9090_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */
  311. #define WM9090_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */
  312. /*
  313. * R37 (0x25) - ClassD3
  314. */
  315. #define WM9090_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
  316. #define WM9090_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */
  317. #define WM9090_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */
  318. /*
  319. * R38 (0x26) - Speaker Volume Left
  320. */
  321. #define WM9090_SPKOUT_VU 0x0100 /* SPKOUT_VU */
  322. #define WM9090_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
  323. #define WM9090_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
  324. #define WM9090_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
  325. #define WM9090_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
  326. #define WM9090_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
  327. #define WM9090_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */
  328. #define WM9090_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
  329. #define WM9090_SPKOUTL_MUTE 0x0040 /* SPKOUTL_MUTE */
  330. #define WM9090_SPKOUTL_MUTE_MASK 0x0040 /* SPKOUTL_MUTE */
  331. #define WM9090_SPKOUTL_MUTE_SHIFT 6 /* SPKOUTL_MUTE */
  332. #define WM9090_SPKOUTL_MUTE_WIDTH 1 /* SPKOUTL_MUTE */
  333. #define WM9090_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
  334. #define WM9090_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
  335. #define WM9090_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
  336. /*
  337. * R45 (0x2D) - Output Mixer1
  338. */
  339. #define WM9090_IN1A_TO_MIXOUTL 0x0040 /* IN1A_TO_MIXOUTL */
  340. #define WM9090_IN1A_TO_MIXOUTL_MASK 0x0040 /* IN1A_TO_MIXOUTL */
  341. #define WM9090_IN1A_TO_MIXOUTL_SHIFT 6 /* IN1A_TO_MIXOUTL */
  342. #define WM9090_IN1A_TO_MIXOUTL_WIDTH 1 /* IN1A_TO_MIXOUTL */
  343. #define WM9090_IN2A_TO_MIXOUTL 0x0004 /* IN2A_TO_MIXOUTL */
  344. #define WM9090_IN2A_TO_MIXOUTL_MASK 0x0004 /* IN2A_TO_MIXOUTL */
  345. #define WM9090_IN2A_TO_MIXOUTL_SHIFT 2 /* IN2A_TO_MIXOUTL */
  346. #define WM9090_IN2A_TO_MIXOUTL_WIDTH 1 /* IN2A_TO_MIXOUTL */
  347. /*
  348. * R46 (0x2E) - Output Mixer2
  349. */
  350. #define WM9090_IN1A_TO_MIXOUTR 0x0040 /* IN1A_TO_MIXOUTR */
  351. #define WM9090_IN1A_TO_MIXOUTR_MASK 0x0040 /* IN1A_TO_MIXOUTR */
  352. #define WM9090_IN1A_TO_MIXOUTR_SHIFT 6 /* IN1A_TO_MIXOUTR */
  353. #define WM9090_IN1A_TO_MIXOUTR_WIDTH 1 /* IN1A_TO_MIXOUTR */
  354. #define WM9090_IN1B_TO_MIXOUTR 0x0010 /* IN1B_TO_MIXOUTR */
  355. #define WM9090_IN1B_TO_MIXOUTR_MASK 0x0010 /* IN1B_TO_MIXOUTR */
  356. #define WM9090_IN1B_TO_MIXOUTR_SHIFT 4 /* IN1B_TO_MIXOUTR */
  357. #define WM9090_IN1B_TO_MIXOUTR_WIDTH 1 /* IN1B_TO_MIXOUTR */
  358. #define WM9090_IN2A_TO_MIXOUTR 0x0004 /* IN2A_TO_MIXOUTR */
  359. #define WM9090_IN2A_TO_MIXOUTR_MASK 0x0004 /* IN2A_TO_MIXOUTR */
  360. #define WM9090_IN2A_TO_MIXOUTR_SHIFT 2 /* IN2A_TO_MIXOUTR */
  361. #define WM9090_IN2A_TO_MIXOUTR_WIDTH 1 /* IN2A_TO_MIXOUTR */
  362. #define WM9090_IN2B_TO_MIXOUTR 0x0001 /* IN2B_TO_MIXOUTR */
  363. #define WM9090_IN2B_TO_MIXOUTR_MASK 0x0001 /* IN2B_TO_MIXOUTR */
  364. #define WM9090_IN2B_TO_MIXOUTR_SHIFT 0 /* IN2B_TO_MIXOUTR */
  365. #define WM9090_IN2B_TO_MIXOUTR_WIDTH 1 /* IN2B_TO_MIXOUTR */
  366. /*
  367. * R47 (0x2F) - Output Mixer3
  368. */
  369. #define WM9090_MIXOUTL_MUTE 0x0100 /* MIXOUTL_MUTE */
  370. #define WM9090_MIXOUTL_MUTE_MASK 0x0100 /* MIXOUTL_MUTE */
  371. #define WM9090_MIXOUTL_MUTE_SHIFT 8 /* MIXOUTL_MUTE */
  372. #define WM9090_MIXOUTL_MUTE_WIDTH 1 /* MIXOUTL_MUTE */
  373. #define WM9090_IN1A_MIXOUTL_VOL_MASK 0x00C0 /* IN1A_MIXOUTL_VOL - [7:6] */
  374. #define WM9090_IN1A_MIXOUTL_VOL_SHIFT 6 /* IN1A_MIXOUTL_VOL - [7:6] */
  375. #define WM9090_IN1A_MIXOUTL_VOL_WIDTH 2 /* IN1A_MIXOUTL_VOL - [7:6] */
  376. #define WM9090_IN2A_MIXOUTL_VOL_MASK 0x000C /* IN2A_MIXOUTL_VOL - [3:2] */
  377. #define WM9090_IN2A_MIXOUTL_VOL_SHIFT 2 /* IN2A_MIXOUTL_VOL - [3:2] */
  378. #define WM9090_IN2A_MIXOUTL_VOL_WIDTH 2 /* IN2A_MIXOUTL_VOL - [3:2] */
  379. /*
  380. * R48 (0x30) - Output Mixer4
  381. */
  382. #define WM9090_MIXOUTR_MUTE 0x0100 /* MIXOUTR_MUTE */
  383. #define WM9090_MIXOUTR_MUTE_MASK 0x0100 /* MIXOUTR_MUTE */
  384. #define WM9090_MIXOUTR_MUTE_SHIFT 8 /* MIXOUTR_MUTE */
  385. #define WM9090_MIXOUTR_MUTE_WIDTH 1 /* MIXOUTR_MUTE */
  386. #define WM9090_IN1A_MIXOUTR_VOL_MASK 0x00C0 /* IN1A_MIXOUTR_VOL - [7:6] */
  387. #define WM9090_IN1A_MIXOUTR_VOL_SHIFT 6 /* IN1A_MIXOUTR_VOL - [7:6] */
  388. #define WM9090_IN1A_MIXOUTR_VOL_WIDTH 2 /* IN1A_MIXOUTR_VOL - [7:6] */
  389. #define WM9090_IN1B_MIXOUTR_VOL_MASK 0x0030 /* IN1B_MIXOUTR_VOL - [5:4] */
  390. #define WM9090_IN1B_MIXOUTR_VOL_SHIFT 4 /* IN1B_MIXOUTR_VOL - [5:4] */
  391. #define WM9090_IN1B_MIXOUTR_VOL_WIDTH 2 /* IN1B_MIXOUTR_VOL - [5:4] */
  392. #define WM9090_IN2A_MIXOUTR_VOL_MASK 0x000C /* IN2A_MIXOUTR_VOL - [3:2] */
  393. #define WM9090_IN2A_MIXOUTR_VOL_SHIFT 2 /* IN2A_MIXOUTR_VOL - [3:2] */
  394. #define WM9090_IN2A_MIXOUTR_VOL_WIDTH 2 /* IN2A_MIXOUTR_VOL - [3:2] */
  395. #define WM9090_IN2B_MIXOUTR_VOL_MASK 0x0003 /* IN2B_MIXOUTR_VOL - [1:0] */
  396. #define WM9090_IN2B_MIXOUTR_VOL_SHIFT 0 /* IN2B_MIXOUTR_VOL - [1:0] */
  397. #define WM9090_IN2B_MIXOUTR_VOL_WIDTH 2 /* IN2B_MIXOUTR_VOL - [1:0] */
  398. /*
  399. * R54 (0x36) - Speaker Mixer
  400. */
  401. #define WM9090_IN1A_TO_SPKMIX 0x0040 /* IN1A_TO_SPKMIX */
  402. #define WM9090_IN1A_TO_SPKMIX_MASK 0x0040 /* IN1A_TO_SPKMIX */
  403. #define WM9090_IN1A_TO_SPKMIX_SHIFT 6 /* IN1A_TO_SPKMIX */
  404. #define WM9090_IN1A_TO_SPKMIX_WIDTH 1 /* IN1A_TO_SPKMIX */
  405. #define WM9090_IN1B_TO_SPKMIX 0x0010 /* IN1B_TO_SPKMIX */
  406. #define WM9090_IN1B_TO_SPKMIX_MASK 0x0010 /* IN1B_TO_SPKMIX */
  407. #define WM9090_IN1B_TO_SPKMIX_SHIFT 4 /* IN1B_TO_SPKMIX */
  408. #define WM9090_IN1B_TO_SPKMIX_WIDTH 1 /* IN1B_TO_SPKMIX */
  409. #define WM9090_IN2A_TO_SPKMIX 0x0004 /* IN2A_TO_SPKMIX */
  410. #define WM9090_IN2A_TO_SPKMIX_MASK 0x0004 /* IN2A_TO_SPKMIX */
  411. #define WM9090_IN2A_TO_SPKMIX_SHIFT 2 /* IN2A_TO_SPKMIX */
  412. #define WM9090_IN2A_TO_SPKMIX_WIDTH 1 /* IN2A_TO_SPKMIX */
  413. #define WM9090_IN2B_TO_SPKMIX 0x0001 /* IN2B_TO_SPKMIX */
  414. #define WM9090_IN2B_TO_SPKMIX_MASK 0x0001 /* IN2B_TO_SPKMIX */
  415. #define WM9090_IN2B_TO_SPKMIX_SHIFT 0 /* IN2B_TO_SPKMIX */
  416. #define WM9090_IN2B_TO_SPKMIX_WIDTH 1 /* IN2B_TO_SPKMIX */
  417. /*
  418. * R57 (0x39) - AntiPOP2
  419. */
  420. #define WM9090_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
  421. #define WM9090_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
  422. #define WM9090_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */
  423. #define WM9090_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
  424. #define WM9090_VMID_ENA 0x0001 /* VMID_ENA */
  425. #define WM9090_VMID_ENA_MASK 0x0001 /* VMID_ENA */
  426. #define WM9090_VMID_ENA_SHIFT 0 /* VMID_ENA */
  427. #define WM9090_VMID_ENA_WIDTH 1 /* VMID_ENA */
  428. /*
  429. * R70 (0x46) - Write Sequencer 0
  430. */
  431. #define WM9090_WSEQ_ENA 0x0100 /* WSEQ_ENA */
  432. #define WM9090_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */
  433. #define WM9090_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */
  434. #define WM9090_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  435. #define WM9090_WSEQ_WRITE_INDEX_MASK 0x000F /* WSEQ_WRITE_INDEX - [3:0] */
  436. #define WM9090_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [3:0] */
  437. #define WM9090_WSEQ_WRITE_INDEX_WIDTH 4 /* WSEQ_WRITE_INDEX - [3:0] */
  438. /*
  439. * R71 (0x47) - Write Sequencer 1
  440. */
  441. #define WM9090_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
  442. #define WM9090_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */
  443. #define WM9090_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */
  444. #define WM9090_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
  445. #define WM9090_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */
  446. #define WM9090_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */
  447. #define WM9090_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
  448. #define WM9090_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
  449. #define WM9090_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
  450. /*
  451. * R72 (0x48) - Write Sequencer 2
  452. */
  453. #define WM9090_WSEQ_EOS 0x4000 /* WSEQ_EOS */
  454. #define WM9090_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */
  455. #define WM9090_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */
  456. #define WM9090_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
  457. #define WM9090_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
  458. #define WM9090_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */
  459. #define WM9090_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */
  460. #define WM9090_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
  461. #define WM9090_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
  462. #define WM9090_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
  463. /*
  464. * R73 (0x49) - Write Sequencer 3
  465. */
  466. #define WM9090_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
  467. #define WM9090_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
  468. #define WM9090_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
  469. #define WM9090_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  470. #define WM9090_WSEQ_START 0x0100 /* WSEQ_START */
  471. #define WM9090_WSEQ_START_MASK 0x0100 /* WSEQ_START */
  472. #define WM9090_WSEQ_START_SHIFT 8 /* WSEQ_START */
  473. #define WM9090_WSEQ_START_WIDTH 1 /* WSEQ_START */
  474. #define WM9090_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
  475. #define WM9090_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
  476. #define WM9090_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
  477. /*
  478. * R74 (0x4A) - Write Sequencer 4
  479. */
  480. #define WM9090_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
  481. #define WM9090_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
  482. #define WM9090_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
  483. #define WM9090_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  484. /*
  485. * R75 (0x4B) - Write Sequencer 5
  486. */
  487. #define WM9090_WSEQ_CURRENT_INDEX_MASK 0x003F /* WSEQ_CURRENT_INDEX - [5:0] */
  488. #define WM9090_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [5:0] */
  489. #define WM9090_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [5:0] */
  490. /*
  491. * R76 (0x4C) - Charge Pump 1
  492. */
  493. #define WM9090_CP_ENA 0x8000 /* CP_ENA */
  494. #define WM9090_CP_ENA_MASK 0x8000 /* CP_ENA */
  495. #define WM9090_CP_ENA_SHIFT 15 /* CP_ENA */
  496. #define WM9090_CP_ENA_WIDTH 1 /* CP_ENA */
  497. /*
  498. * R84 (0x54) - DC Servo 0
  499. */
  500. #define WM9090_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
  501. #define WM9090_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
  502. #define WM9090_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
  503. #define WM9090_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
  504. #define WM9090_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
  505. #define WM9090_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
  506. #define WM9090_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
  507. #define WM9090_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
  508. #define WM9090_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
  509. #define WM9090_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
  510. #define WM9090_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
  511. #define WM9090_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
  512. #define WM9090_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
  513. #define WM9090_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
  514. #define WM9090_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
  515. #define WM9090_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
  516. #define WM9090_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
  517. #define WM9090_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
  518. #define WM9090_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
  519. #define WM9090_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
  520. #define WM9090_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
  521. #define WM9090_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
  522. #define WM9090_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
  523. #define WM9090_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
  524. #define WM9090_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
  525. #define WM9090_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
  526. #define WM9090_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */
  527. #define WM9090_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
  528. #define WM9090_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
  529. #define WM9090_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
  530. #define WM9090_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */
  531. #define WM9090_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
  532. #define WM9090_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
  533. #define WM9090_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
  534. #define WM9090_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
  535. #define WM9090_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
  536. #define WM9090_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
  537. #define WM9090_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
  538. #define WM9090_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
  539. #define WM9090_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
  540. /*
  541. * R85 (0x55) - DC Servo 1
  542. */
  543. #define WM9090_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
  544. #define WM9090_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */
  545. #define WM9090_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */
  546. #define WM9090_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
  547. #define WM9090_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
  548. #define WM9090_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
  549. /*
  550. * R87 (0x57) - DC Servo 3
  551. */
  552. #define WM9090_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
  553. #define WM9090_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
  554. #define WM9090_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
  555. #define WM9090_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
  556. #define WM9090_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
  557. #define WM9090_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
  558. /*
  559. * R88 (0x58) - DC Servo Readback 0
  560. */
  561. #define WM9090_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
  562. #define WM9090_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */
  563. #define WM9090_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */
  564. #define WM9090_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
  565. #define WM9090_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */
  566. #define WM9090_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */
  567. #define WM9090_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
  568. #define WM9090_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
  569. #define WM9090_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
  570. /*
  571. * R89 (0x59) - DC Servo Readback 1
  572. */
  573. #define WM9090_DCS_DAC_WR_VAL_1_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_1_RD - [7:0] */
  574. #define WM9090_DCS_DAC_WR_VAL_1_RD_SHIFT 0 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
  575. #define WM9090_DCS_DAC_WR_VAL_1_RD_WIDTH 8 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
  576. /*
  577. * R90 (0x5A) - DC Servo Readback 2
  578. */
  579. #define WM9090_DCS_DAC_WR_VAL_0_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_0_RD - [7:0] */
  580. #define WM9090_DCS_DAC_WR_VAL_0_RD_SHIFT 0 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
  581. #define WM9090_DCS_DAC_WR_VAL_0_RD_WIDTH 8 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
  582. /*
  583. * R96 (0x60) - Analogue HP 0
  584. */
  585. #define WM9090_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
  586. #define WM9090_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
  587. #define WM9090_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
  588. #define WM9090_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
  589. #define WM9090_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
  590. #define WM9090_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
  591. #define WM9090_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
  592. #define WM9090_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
  593. #define WM9090_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
  594. #define WM9090_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
  595. #define WM9090_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
  596. #define WM9090_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
  597. #define WM9090_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
  598. #define WM9090_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
  599. #define WM9090_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
  600. #define WM9090_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
  601. #define WM9090_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
  602. #define WM9090_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
  603. #define WM9090_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
  604. #define WM9090_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
  605. #define WM9090_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
  606. #define WM9090_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
  607. #define WM9090_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
  608. #define WM9090_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
  609. /*
  610. * R98 (0x62) - AGC Control 0
  611. */
  612. #define WM9090_AGC_CLIP_ENA 0x8000 /* AGC_CLIP_ENA */
  613. #define WM9090_AGC_CLIP_ENA_MASK 0x8000 /* AGC_CLIP_ENA */
  614. #define WM9090_AGC_CLIP_ENA_SHIFT 15 /* AGC_CLIP_ENA */
  615. #define WM9090_AGC_CLIP_ENA_WIDTH 1 /* AGC_CLIP_ENA */
  616. #define WM9090_AGC_CLIP_THR_MASK 0x0F00 /* AGC_CLIP_THR - [11:8] */
  617. #define WM9090_AGC_CLIP_THR_SHIFT 8 /* AGC_CLIP_THR - [11:8] */
  618. #define WM9090_AGC_CLIP_THR_WIDTH 4 /* AGC_CLIP_THR - [11:8] */
  619. #define WM9090_AGC_CLIP_ATK_MASK 0x0070 /* AGC_CLIP_ATK - [6:4] */
  620. #define WM9090_AGC_CLIP_ATK_SHIFT 4 /* AGC_CLIP_ATK - [6:4] */
  621. #define WM9090_AGC_CLIP_ATK_WIDTH 3 /* AGC_CLIP_ATK - [6:4] */
  622. #define WM9090_AGC_CLIP_DCY_MASK 0x0007 /* AGC_CLIP_DCY - [2:0] */
  623. #define WM9090_AGC_CLIP_DCY_SHIFT 0 /* AGC_CLIP_DCY - [2:0] */
  624. #define WM9090_AGC_CLIP_DCY_WIDTH 3 /* AGC_CLIP_DCY - [2:0] */
  625. /*
  626. * R99 (0x63) - AGC Control 1
  627. */
  628. #define WM9090_AGC_PWR_ENA 0x8000 /* AGC_PWR_ENA */
  629. #define WM9090_AGC_PWR_ENA_MASK 0x8000 /* AGC_PWR_ENA */
  630. #define WM9090_AGC_PWR_ENA_SHIFT 15 /* AGC_PWR_ENA */
  631. #define WM9090_AGC_PWR_ENA_WIDTH 1 /* AGC_PWR_ENA */
  632. #define WM9090_AGC_PWR_AVG 0x1000 /* AGC_PWR_AVG */
  633. #define WM9090_AGC_PWR_AVG_MASK 0x1000 /* AGC_PWR_AVG */
  634. #define WM9090_AGC_PWR_AVG_SHIFT 12 /* AGC_PWR_AVG */
  635. #define WM9090_AGC_PWR_AVG_WIDTH 1 /* AGC_PWR_AVG */
  636. #define WM9090_AGC_PWR_THR_MASK 0x0F00 /* AGC_PWR_THR - [11:8] */
  637. #define WM9090_AGC_PWR_THR_SHIFT 8 /* AGC_PWR_THR - [11:8] */
  638. #define WM9090_AGC_PWR_THR_WIDTH 4 /* AGC_PWR_THR - [11:8] */
  639. #define WM9090_AGC_PWR_ATK_MASK 0x0070 /* AGC_PWR_ATK - [6:4] */
  640. #define WM9090_AGC_PWR_ATK_SHIFT 4 /* AGC_PWR_ATK - [6:4] */
  641. #define WM9090_AGC_PWR_ATK_WIDTH 3 /* AGC_PWR_ATK - [6:4] */
  642. #define WM9090_AGC_PWR_DCY_MASK 0x0007 /* AGC_PWR_DCY - [2:0] */
  643. #define WM9090_AGC_PWR_DCY_SHIFT 0 /* AGC_PWR_DCY - [2:0] */
  644. #define WM9090_AGC_PWR_DCY_WIDTH 3 /* AGC_PWR_DCY - [2:0] */
  645. /*
  646. * R100 (0x64) - AGC Control 2
  647. */
  648. #define WM9090_AGC_RAMP 0x0100 /* AGC_RAMP */
  649. #define WM9090_AGC_RAMP_MASK 0x0100 /* AGC_RAMP */
  650. #define WM9090_AGC_RAMP_SHIFT 8 /* AGC_RAMP */
  651. #define WM9090_AGC_RAMP_WIDTH 1 /* AGC_RAMP */
  652. #define WM9090_AGC_MINGAIN_MASK 0x003F /* AGC_MINGAIN - [5:0] */
  653. #define WM9090_AGC_MINGAIN_SHIFT 0 /* AGC_MINGAIN - [5:0] */
  654. #define WM9090_AGC_MINGAIN_WIDTH 6 /* AGC_MINGAIN - [5:0] */
  655. #endif