wm9081.h 40 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. #ifndef WM9081_H
  3. #define WM9081_H
  4. /*
  5. * wm9081.c -- WM9081 ALSA SoC Audio driver
  6. *
  7. * Author: Mark Brown
  8. *
  9. * Copyright 2009 Wolfson Microelectronics plc
  10. */
  11. #include <sound/soc.h>
  12. /*
  13. * SYSCLK sources
  14. */
  15. #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
  16. #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
  17. /*
  18. * Register values.
  19. */
  20. #define WM9081_SOFTWARE_RESET 0x00
  21. #define WM9081_ANALOGUE_LINEOUT 0x02
  22. #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
  23. #define WM9081_VMID_CONTROL 0x04
  24. #define WM9081_BIAS_CONTROL_1 0x05
  25. #define WM9081_ANALOGUE_MIXER 0x07
  26. #define WM9081_ANTI_POP_CONTROL 0x08
  27. #define WM9081_ANALOGUE_SPEAKER_1 0x09
  28. #define WM9081_ANALOGUE_SPEAKER_2 0x0A
  29. #define WM9081_POWER_MANAGEMENT 0x0B
  30. #define WM9081_CLOCK_CONTROL_1 0x0C
  31. #define WM9081_CLOCK_CONTROL_2 0x0D
  32. #define WM9081_CLOCK_CONTROL_3 0x0E
  33. #define WM9081_FLL_CONTROL_1 0x10
  34. #define WM9081_FLL_CONTROL_2 0x11
  35. #define WM9081_FLL_CONTROL_3 0x12
  36. #define WM9081_FLL_CONTROL_4 0x13
  37. #define WM9081_FLL_CONTROL_5 0x14
  38. #define WM9081_AUDIO_INTERFACE_1 0x16
  39. #define WM9081_AUDIO_INTERFACE_2 0x17
  40. #define WM9081_AUDIO_INTERFACE_3 0x18
  41. #define WM9081_AUDIO_INTERFACE_4 0x19
  42. #define WM9081_INTERRUPT_STATUS 0x1A
  43. #define WM9081_INTERRUPT_STATUS_MASK 0x1B
  44. #define WM9081_INTERRUPT_POLARITY 0x1C
  45. #define WM9081_INTERRUPT_CONTROL 0x1D
  46. #define WM9081_DAC_DIGITAL_1 0x1E
  47. #define WM9081_DAC_DIGITAL_2 0x1F
  48. #define WM9081_DRC_1 0x20
  49. #define WM9081_DRC_2 0x21
  50. #define WM9081_DRC_3 0x22
  51. #define WM9081_DRC_4 0x23
  52. #define WM9081_WRITE_SEQUENCER_1 0x26
  53. #define WM9081_WRITE_SEQUENCER_2 0x27
  54. #define WM9081_MW_SLAVE_1 0x28
  55. #define WM9081_EQ_1 0x2A
  56. #define WM9081_EQ_2 0x2B
  57. #define WM9081_EQ_3 0x2C
  58. #define WM9081_EQ_4 0x2D
  59. #define WM9081_EQ_5 0x2E
  60. #define WM9081_EQ_6 0x2F
  61. #define WM9081_EQ_7 0x30
  62. #define WM9081_EQ_8 0x31
  63. #define WM9081_EQ_9 0x32
  64. #define WM9081_EQ_10 0x33
  65. #define WM9081_EQ_11 0x34
  66. #define WM9081_EQ_12 0x35
  67. #define WM9081_EQ_13 0x36
  68. #define WM9081_EQ_14 0x37
  69. #define WM9081_EQ_15 0x38
  70. #define WM9081_EQ_16 0x39
  71. #define WM9081_EQ_17 0x3A
  72. #define WM9081_EQ_18 0x3B
  73. #define WM9081_EQ_19 0x3C
  74. #define WM9081_EQ_20 0x3D
  75. #define WM9081_REGISTER_COUNT 55
  76. #define WM9081_MAX_REGISTER 0x3D
  77. /*
  78. * Field Definitions.
  79. */
  80. /*
  81. * R0 (0x00) - Software Reset
  82. */
  83. #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  84. #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  85. #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  86. /*
  87. * R2 (0x02) - Analogue Lineout
  88. */
  89. #define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
  90. #define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
  91. #define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
  92. #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
  93. #define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
  94. #define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
  95. #define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
  96. #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
  97. #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
  98. #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
  99. #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
  100. /*
  101. * R3 (0x03) - Analogue Speaker PGA
  102. */
  103. #define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
  104. #define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
  105. #define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
  106. #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
  107. #define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
  108. #define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
  109. #define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
  110. #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
  111. #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
  112. #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
  113. #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
  114. /*
  115. * R4 (0x04) - VMID Control
  116. */
  117. #define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
  118. #define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
  119. #define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
  120. #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
  121. #define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
  122. #define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
  123. #define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
  124. #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
  125. #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
  126. #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
  127. #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
  128. #define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
  129. #define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
  130. #define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
  131. #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
  132. /*
  133. * R5 (0x05) - Bias Control 1
  134. */
  135. #define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
  136. #define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
  137. #define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
  138. #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
  139. #define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
  140. #define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
  141. #define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
  142. #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
  143. #define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
  144. #define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
  145. #define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
  146. #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
  147. #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
  148. #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
  149. #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
  150. #define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
  151. #define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
  152. #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
  153. #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
  154. #define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
  155. #define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
  156. #define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
  157. #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
  158. /*
  159. * R7 (0x07) - Analogue Mixer
  160. */
  161. #define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
  162. #define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
  163. #define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
  164. #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
  165. #define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
  166. #define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
  167. #define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
  168. #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
  169. #define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
  170. #define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
  171. #define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
  172. #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
  173. #define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
  174. #define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
  175. #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
  176. #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
  177. #define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
  178. #define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
  179. #define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
  180. #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
  181. /*
  182. * R8 (0x08) - Anti Pop Control
  183. */
  184. #define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
  185. #define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
  186. #define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
  187. #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
  188. #define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
  189. #define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
  190. #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
  191. #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
  192. #define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
  193. #define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
  194. #define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
  195. #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
  196. /*
  197. * R9 (0x09) - Analogue Speaker 1
  198. */
  199. #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
  200. #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
  201. #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
  202. #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
  203. #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
  204. #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
  205. /*
  206. * R10 (0x0A) - Analogue Speaker 2
  207. */
  208. #define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
  209. #define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
  210. #define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
  211. #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
  212. #define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
  213. #define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
  214. #define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
  215. #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
  216. #define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
  217. #define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
  218. #define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
  219. #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
  220. /*
  221. * R11 (0x0B) - Power Management
  222. */
  223. #define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
  224. #define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
  225. #define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
  226. #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
  227. #define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
  228. #define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
  229. #define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
  230. #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
  231. #define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
  232. #define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
  233. #define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
  234. #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
  235. #define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
  236. #define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
  237. #define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
  238. #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
  239. #define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
  240. #define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
  241. #define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
  242. #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
  243. #define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
  244. #define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
  245. #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
  246. #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
  247. #define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
  248. #define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
  249. #define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
  250. #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
  251. /*
  252. * R12 (0x0C) - Clock Control 1
  253. */
  254. #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
  255. #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
  256. #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
  257. #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
  258. #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
  259. #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
  260. #define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
  261. #define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
  262. #define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
  263. #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
  264. /*
  265. * R13 (0x0D) - Clock Control 2
  266. */
  267. #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
  268. #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
  269. #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
  270. #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
  271. #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
  272. #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
  273. /*
  274. * R14 (0x0E) - Clock Control 3
  275. */
  276. #define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
  277. #define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
  278. #define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
  279. #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
  280. #define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
  281. #define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
  282. #define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
  283. #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
  284. #define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
  285. #define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
  286. #define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
  287. #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
  288. #define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
  289. #define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
  290. #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
  291. #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
  292. #define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
  293. #define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
  294. #define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
  295. #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
  296. /*
  297. * R16 (0x10) - FLL Control 1
  298. */
  299. #define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
  300. #define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
  301. #define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
  302. #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
  303. #define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
  304. #define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
  305. #define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
  306. #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
  307. #define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
  308. #define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
  309. #define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
  310. #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
  311. /*
  312. * R17 (0x11) - FLL Control 2
  313. */
  314. #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
  315. #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
  316. #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
  317. #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
  318. #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
  319. #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
  320. #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
  321. #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
  322. #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
  323. /*
  324. * R18 (0x12) - FLL Control 3
  325. */
  326. #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
  327. #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
  328. #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
  329. /*
  330. * R19 (0x13) - FLL Control 4
  331. */
  332. #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
  333. #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
  334. #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
  335. #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
  336. #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
  337. #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
  338. /*
  339. * R20 (0x14) - FLL Control 5
  340. */
  341. #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
  342. #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
  343. #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
  344. #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
  345. #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
  346. #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
  347. /*
  348. * R22 (0x16) - Audio Interface 1
  349. */
  350. #define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
  351. #define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
  352. #define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
  353. #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
  354. #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
  355. #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
  356. #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
  357. #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
  358. #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
  359. #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
  360. #define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
  361. #define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
  362. #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
  363. #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
  364. #define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
  365. #define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
  366. #define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
  367. #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
  368. /*
  369. * R23 (0x17) - Audio Interface 2
  370. */
  371. #define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
  372. #define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
  373. #define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
  374. #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
  375. #define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
  376. #define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
  377. #define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
  378. #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
  379. #define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
  380. #define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
  381. #define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
  382. #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
  383. #define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
  384. #define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
  385. #define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
  386. #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
  387. #define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
  388. #define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
  389. #define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
  390. #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
  391. #define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
  392. #define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
  393. #define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
  394. #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
  395. #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
  396. #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
  397. #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
  398. #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
  399. #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
  400. #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
  401. /*
  402. * R24 (0x18) - Audio Interface 3
  403. */
  404. #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
  405. #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
  406. #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
  407. /*
  408. * R25 (0x19) - Audio Interface 4
  409. */
  410. #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
  411. #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
  412. #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
  413. /*
  414. * R26 (0x1A) - Interrupt Status
  415. */
  416. #define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
  417. #define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
  418. #define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
  419. #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
  420. #define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
  421. #define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
  422. #define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
  423. #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
  424. /*
  425. * R27 (0x1B) - Interrupt Status Mask
  426. */
  427. #define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
  428. #define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
  429. #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
  430. #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
  431. #define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
  432. #define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
  433. #define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
  434. #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
  435. /*
  436. * R28 (0x1C) - Interrupt Polarity
  437. */
  438. #define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
  439. #define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
  440. #define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
  441. #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
  442. /*
  443. * R29 (0x1D) - Interrupt Control
  444. */
  445. #define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
  446. #define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
  447. #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
  448. #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
  449. #define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
  450. #define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
  451. #define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
  452. #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
  453. /*
  454. * R30 (0x1E) - DAC Digital 1
  455. */
  456. #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
  457. #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
  458. #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
  459. /*
  460. * R31 (0x1F) - DAC Digital 2
  461. */
  462. #define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
  463. #define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
  464. #define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
  465. #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
  466. #define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
  467. #define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
  468. #define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
  469. #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
  470. #define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
  471. #define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
  472. #define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
  473. #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
  474. #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
  475. #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
  476. #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
  477. /*
  478. * R32 (0x20) - DRC 1
  479. */
  480. #define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
  481. #define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
  482. #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
  483. #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
  484. #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
  485. #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
  486. #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
  487. #define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
  488. #define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
  489. #define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
  490. #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
  491. #define WM9081_DRC_QR 0x0004 /* DRC_QR */
  492. #define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
  493. #define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
  494. #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
  495. #define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
  496. #define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
  497. #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
  498. #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
  499. /*
  500. * R33 (0x21) - DRC 2
  501. */
  502. #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
  503. #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
  504. #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
  505. #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
  506. #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
  507. #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
  508. #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
  509. #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
  510. #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
  511. #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
  512. #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
  513. #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
  514. #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
  515. #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
  516. #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
  517. #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
  518. #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
  519. #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
  520. /*
  521. * R34 (0x22) - DRC 3
  522. */
  523. #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
  524. #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
  525. #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
  526. #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
  527. #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
  528. #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
  529. /*
  530. * R35 (0x23) - DRC 4
  531. */
  532. #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
  533. #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
  534. #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
  535. #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
  536. #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
  537. #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
  538. /*
  539. * R38 (0x26) - Write Sequencer 1
  540. */
  541. #define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
  542. #define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
  543. #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
  544. #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  545. #define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
  546. #define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
  547. #define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
  548. #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  549. #define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
  550. #define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
  551. #define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
  552. #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
  553. #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
  554. #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
  555. #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
  556. /*
  557. * R39 (0x27) - Write Sequencer 2
  558. */
  559. #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
  560. #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
  561. #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
  562. #define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
  563. #define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
  564. #define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
  565. #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  566. /*
  567. * R40 (0x28) - MW Slave 1
  568. */
  569. #define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
  570. #define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
  571. #define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
  572. #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
  573. #define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
  574. #define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
  575. #define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
  576. #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
  577. #define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
  578. #define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
  579. #define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
  580. #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
  581. #define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
  582. #define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
  583. #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
  584. #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
  585. /*
  586. * R42 (0x2A) - EQ 1
  587. */
  588. #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
  589. #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
  590. #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
  591. #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
  592. #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
  593. #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
  594. #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
  595. #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
  596. #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
  597. #define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
  598. #define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
  599. #define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
  600. #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
  601. /*
  602. * R43 (0x2B) - EQ 2
  603. */
  604. #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
  605. #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
  606. #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
  607. #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
  608. #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
  609. #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
  610. /*
  611. * R44 (0x2C) - EQ 3
  612. */
  613. #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
  614. #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
  615. #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
  616. /*
  617. * R45 (0x2D) - EQ 4
  618. */
  619. #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
  620. #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
  621. #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
  622. /*
  623. * R46 (0x2E) - EQ 5
  624. */
  625. #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
  626. #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
  627. #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
  628. /*
  629. * R47 (0x2F) - EQ 6
  630. */
  631. #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
  632. #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
  633. #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
  634. /*
  635. * R48 (0x30) - EQ 7
  636. */
  637. #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
  638. #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
  639. #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
  640. /*
  641. * R49 (0x31) - EQ 8
  642. */
  643. #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
  644. #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
  645. #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
  646. /*
  647. * R50 (0x32) - EQ 9
  648. */
  649. #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
  650. #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
  651. #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
  652. /*
  653. * R51 (0x33) - EQ 10
  654. */
  655. #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
  656. #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
  657. #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
  658. /*
  659. * R52 (0x34) - EQ 11
  660. */
  661. #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
  662. #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
  663. #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
  664. /*
  665. * R53 (0x35) - EQ 12
  666. */
  667. #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
  668. #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
  669. #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
  670. /*
  671. * R54 (0x36) - EQ 13
  672. */
  673. #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
  674. #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
  675. #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
  676. /*
  677. * R55 (0x37) - EQ 14
  678. */
  679. #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
  680. #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
  681. #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
  682. /*
  683. * R56 (0x38) - EQ 15
  684. */
  685. #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
  686. #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
  687. #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
  688. /*
  689. * R57 (0x39) - EQ 16
  690. */
  691. #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
  692. #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
  693. #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
  694. /*
  695. * R58 (0x3A) - EQ 17
  696. */
  697. #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
  698. #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
  699. #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
  700. /*
  701. * R59 (0x3B) - EQ 18
  702. */
  703. #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
  704. #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
  705. #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
  706. /*
  707. * R60 (0x3C) - EQ 19
  708. */
  709. #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
  710. #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
  711. #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
  712. /*
  713. * R61 (0x3D) - EQ 20
  714. */
  715. #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
  716. #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
  717. #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
  718. #endif