wm9081.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm9081.c -- WM9081 ALSA SoC Audio driver
  4. *
  5. * Author: Mark Brown
  6. *
  7. * Copyright 2009-12 Wolfson Microelectronics plc
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/pm.h>
  15. #include <linux/i2c.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/initval.h>
  23. #include <sound/tlv.h>
  24. #include <sound/wm9081.h>
  25. #include "wm9081.h"
  26. static const struct reg_default wm9081_reg[] = {
  27. { 2, 0x00B9 }, /* R2 - Analogue Lineout */
  28. { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
  29. { 4, 0x0001 }, /* R4 - VMID Control */
  30. { 5, 0x0068 }, /* R5 - Bias Control 1 */
  31. { 7, 0x0000 }, /* R7 - Analogue Mixer */
  32. { 8, 0x0000 }, /* R8 - Anti Pop Control */
  33. { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
  34. { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
  35. { 11, 0x0180 }, /* R11 - Power Management */
  36. { 12, 0x0000 }, /* R12 - Clock Control 1 */
  37. { 13, 0x0038 }, /* R13 - Clock Control 2 */
  38. { 14, 0x4000 }, /* R14 - Clock Control 3 */
  39. { 16, 0x0000 }, /* R16 - FLL Control 1 */
  40. { 17, 0x0200 }, /* R17 - FLL Control 2 */
  41. { 18, 0x0000 }, /* R18 - FLL Control 3 */
  42. { 19, 0x0204 }, /* R19 - FLL Control 4 */
  43. { 20, 0x0000 }, /* R20 - FLL Control 5 */
  44. { 22, 0x0000 }, /* R22 - Audio Interface 1 */
  45. { 23, 0x0002 }, /* R23 - Audio Interface 2 */
  46. { 24, 0x0008 }, /* R24 - Audio Interface 3 */
  47. { 25, 0x0022 }, /* R25 - Audio Interface 4 */
  48. { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
  49. { 28, 0x0000 }, /* R28 - Interrupt Polarity */
  50. { 29, 0x0000 }, /* R29 - Interrupt Control */
  51. { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
  52. { 31, 0x0008 }, /* R31 - DAC Digital 2 */
  53. { 32, 0x09AF }, /* R32 - DRC 1 */
  54. { 33, 0x4201 }, /* R33 - DRC 2 */
  55. { 34, 0x0000 }, /* R34 - DRC 3 */
  56. { 35, 0x0000 }, /* R35 - DRC 4 */
  57. { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
  58. { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
  59. { 40, 0x0002 }, /* R40 - MW Slave 1 */
  60. { 42, 0x0000 }, /* R42 - EQ 1 */
  61. { 43, 0x0000 }, /* R43 - EQ 2 */
  62. { 44, 0x0FCA }, /* R44 - EQ 3 */
  63. { 45, 0x0400 }, /* R45 - EQ 4 */
  64. { 46, 0x00B8 }, /* R46 - EQ 5 */
  65. { 47, 0x1EB5 }, /* R47 - EQ 6 */
  66. { 48, 0xF145 }, /* R48 - EQ 7 */
  67. { 49, 0x0B75 }, /* R49 - EQ 8 */
  68. { 50, 0x01C5 }, /* R50 - EQ 9 */
  69. { 51, 0x169E }, /* R51 - EQ 10 */
  70. { 52, 0xF829 }, /* R52 - EQ 11 */
  71. { 53, 0x07AD }, /* R53 - EQ 12 */
  72. { 54, 0x1103 }, /* R54 - EQ 13 */
  73. { 55, 0x1C58 }, /* R55 - EQ 14 */
  74. { 56, 0xF373 }, /* R56 - EQ 15 */
  75. { 57, 0x0A54 }, /* R57 - EQ 16 */
  76. { 58, 0x0558 }, /* R58 - EQ 17 */
  77. { 59, 0x0564 }, /* R59 - EQ 18 */
  78. { 60, 0x0559 }, /* R60 - EQ 19 */
  79. { 61, 0x4000 }, /* R61 - EQ 20 */
  80. };
  81. static struct {
  82. int ratio;
  83. int clk_sys_rate;
  84. } clk_sys_rates[] = {
  85. { 64, 0 },
  86. { 128, 1 },
  87. { 192, 2 },
  88. { 256, 3 },
  89. { 384, 4 },
  90. { 512, 5 },
  91. { 768, 6 },
  92. { 1024, 7 },
  93. { 1408, 8 },
  94. { 1536, 9 },
  95. };
  96. static struct {
  97. int rate;
  98. int sample_rate;
  99. } sample_rates[] = {
  100. { 8000, 0 },
  101. { 11025, 1 },
  102. { 12000, 2 },
  103. { 16000, 3 },
  104. { 22050, 4 },
  105. { 24000, 5 },
  106. { 32000, 6 },
  107. { 44100, 7 },
  108. { 48000, 8 },
  109. { 88200, 9 },
  110. { 96000, 10 },
  111. };
  112. static struct {
  113. int div; /* *10 due to .5s */
  114. int bclk_div;
  115. } bclk_divs[] = {
  116. { 10, 0 },
  117. { 15, 1 },
  118. { 20, 2 },
  119. { 30, 3 },
  120. { 40, 4 },
  121. { 50, 5 },
  122. { 55, 6 },
  123. { 60, 7 },
  124. { 80, 8 },
  125. { 100, 9 },
  126. { 110, 10 },
  127. { 120, 11 },
  128. { 160, 12 },
  129. { 200, 13 },
  130. { 220, 14 },
  131. { 240, 15 },
  132. { 250, 16 },
  133. { 300, 17 },
  134. { 320, 18 },
  135. { 440, 19 },
  136. { 480, 20 },
  137. };
  138. struct wm9081_priv {
  139. struct regmap *regmap;
  140. int sysclk_source;
  141. int mclk_rate;
  142. int sysclk_rate;
  143. int fs;
  144. int bclk;
  145. int master;
  146. int fll_fref;
  147. int fll_fout;
  148. int tdm_width;
  149. struct wm9081_pdata pdata;
  150. };
  151. static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
  152. {
  153. switch (reg) {
  154. case WM9081_SOFTWARE_RESET:
  155. case WM9081_INTERRUPT_STATUS:
  156. return true;
  157. default:
  158. return false;
  159. }
  160. }
  161. static bool wm9081_readable_register(struct device *dev, unsigned int reg)
  162. {
  163. switch (reg) {
  164. case WM9081_SOFTWARE_RESET:
  165. case WM9081_ANALOGUE_LINEOUT:
  166. case WM9081_ANALOGUE_SPEAKER_PGA:
  167. case WM9081_VMID_CONTROL:
  168. case WM9081_BIAS_CONTROL_1:
  169. case WM9081_ANALOGUE_MIXER:
  170. case WM9081_ANTI_POP_CONTROL:
  171. case WM9081_ANALOGUE_SPEAKER_1:
  172. case WM9081_ANALOGUE_SPEAKER_2:
  173. case WM9081_POWER_MANAGEMENT:
  174. case WM9081_CLOCK_CONTROL_1:
  175. case WM9081_CLOCK_CONTROL_2:
  176. case WM9081_CLOCK_CONTROL_3:
  177. case WM9081_FLL_CONTROL_1:
  178. case WM9081_FLL_CONTROL_2:
  179. case WM9081_FLL_CONTROL_3:
  180. case WM9081_FLL_CONTROL_4:
  181. case WM9081_FLL_CONTROL_5:
  182. case WM9081_AUDIO_INTERFACE_1:
  183. case WM9081_AUDIO_INTERFACE_2:
  184. case WM9081_AUDIO_INTERFACE_3:
  185. case WM9081_AUDIO_INTERFACE_4:
  186. case WM9081_INTERRUPT_STATUS:
  187. case WM9081_INTERRUPT_STATUS_MASK:
  188. case WM9081_INTERRUPT_POLARITY:
  189. case WM9081_INTERRUPT_CONTROL:
  190. case WM9081_DAC_DIGITAL_1:
  191. case WM9081_DAC_DIGITAL_2:
  192. case WM9081_DRC_1:
  193. case WM9081_DRC_2:
  194. case WM9081_DRC_3:
  195. case WM9081_DRC_4:
  196. case WM9081_WRITE_SEQUENCER_1:
  197. case WM9081_WRITE_SEQUENCER_2:
  198. case WM9081_MW_SLAVE_1:
  199. case WM9081_EQ_1:
  200. case WM9081_EQ_2:
  201. case WM9081_EQ_3:
  202. case WM9081_EQ_4:
  203. case WM9081_EQ_5:
  204. case WM9081_EQ_6:
  205. case WM9081_EQ_7:
  206. case WM9081_EQ_8:
  207. case WM9081_EQ_9:
  208. case WM9081_EQ_10:
  209. case WM9081_EQ_11:
  210. case WM9081_EQ_12:
  211. case WM9081_EQ_13:
  212. case WM9081_EQ_14:
  213. case WM9081_EQ_15:
  214. case WM9081_EQ_16:
  215. case WM9081_EQ_17:
  216. case WM9081_EQ_18:
  217. case WM9081_EQ_19:
  218. case WM9081_EQ_20:
  219. return true;
  220. default:
  221. return false;
  222. }
  223. }
  224. static int wm9081_reset(struct regmap *map)
  225. {
  226. return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
  227. }
  228. static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
  229. static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
  230. static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
  231. static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
  232. 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
  233. 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
  234. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  235. 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
  236. );
  237. static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
  238. static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
  239. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  240. static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
  241. static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
  242. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  243. static const char *drc_high_text[] = {
  244. "1",
  245. "1/2",
  246. "1/4",
  247. "1/8",
  248. "1/16",
  249. "0",
  250. };
  251. static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text);
  252. static const char *drc_low_text[] = {
  253. "1",
  254. "1/2",
  255. "1/4",
  256. "1/8",
  257. "0",
  258. };
  259. static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text);
  260. static const char *drc_atk_text[] = {
  261. "181us",
  262. "181us",
  263. "363us",
  264. "726us",
  265. "1.45ms",
  266. "2.9ms",
  267. "5.8ms",
  268. "11.6ms",
  269. "23.2ms",
  270. "46.4ms",
  271. "92.8ms",
  272. "185.6ms",
  273. };
  274. static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text);
  275. static const char *drc_dcy_text[] = {
  276. "186ms",
  277. "372ms",
  278. "743ms",
  279. "1.49s",
  280. "2.97s",
  281. "5.94s",
  282. "11.89s",
  283. "23.78s",
  284. "47.56s",
  285. };
  286. static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text);
  287. static const char *drc_qr_dcy_text[] = {
  288. "0.725ms",
  289. "1.45ms",
  290. "5.8ms",
  291. };
  292. static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text);
  293. static const char *dac_deemph_text[] = {
  294. "None",
  295. "32kHz",
  296. "44.1kHz",
  297. "48kHz",
  298. };
  299. static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1,
  300. dac_deemph_text);
  301. static const char *speaker_mode_text[] = {
  302. "Class D",
  303. "Class AB",
  304. };
  305. static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
  306. speaker_mode_text);
  307. static int speaker_mode_get(struct snd_kcontrol *kcontrol,
  308. struct snd_ctl_elem_value *ucontrol)
  309. {
  310. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  311. unsigned int reg;
  312. reg = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
  313. if (reg & WM9081_SPK_MODE)
  314. ucontrol->value.enumerated.item[0] = 1;
  315. else
  316. ucontrol->value.enumerated.item[0] = 0;
  317. return 0;
  318. }
  319. /*
  320. * Stop any attempts to change speaker mode while the speaker is enabled.
  321. *
  322. * We also have some special anti-pop controls dependent on speaker
  323. * mode which must be changed along with the mode.
  324. */
  325. static int speaker_mode_put(struct snd_kcontrol *kcontrol,
  326. struct snd_ctl_elem_value *ucontrol)
  327. {
  328. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  329. unsigned int reg_pwr = snd_soc_component_read(component, WM9081_POWER_MANAGEMENT);
  330. unsigned int reg2 = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
  331. /* Are we changing anything? */
  332. if (ucontrol->value.enumerated.item[0] ==
  333. ((reg2 & WM9081_SPK_MODE) != 0))
  334. return 0;
  335. /* Don't try to change modes while enabled */
  336. if (reg_pwr & WM9081_SPK_ENA)
  337. return -EINVAL;
  338. if (ucontrol->value.enumerated.item[0]) {
  339. /* Class AB */
  340. reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
  341. reg2 |= WM9081_SPK_MODE;
  342. } else {
  343. /* Class D */
  344. reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
  345. reg2 &= ~WM9081_SPK_MODE;
  346. }
  347. snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2);
  348. return 0;
  349. }
  350. static const struct snd_kcontrol_new wm9081_snd_controls[] = {
  351. SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
  352. SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
  353. SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
  354. SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
  355. SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
  356. SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
  357. SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
  358. SOC_ENUM("DRC High Slope", drc_high),
  359. SOC_ENUM("DRC Low Slope", drc_low),
  360. SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
  361. SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
  362. SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
  363. SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
  364. SOC_ENUM("DRC Attack", drc_atk),
  365. SOC_ENUM("DRC Decay", drc_dcy),
  366. SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
  367. SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
  368. SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
  369. SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
  370. SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
  371. SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
  372. SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
  373. SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
  374. SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
  375. SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
  376. out_tlv),
  377. SOC_ENUM("DAC Deemphasis", dac_deemph),
  378. SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
  379. };
  380. static const struct snd_kcontrol_new wm9081_eq_controls[] = {
  381. SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
  382. SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
  383. SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
  384. SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
  385. SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
  386. };
  387. static const struct snd_kcontrol_new mixer[] = {
  388. SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
  389. SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
  390. SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
  391. };
  392. struct _fll_div {
  393. u16 fll_fratio;
  394. u16 fll_outdiv;
  395. u16 fll_clk_ref_div;
  396. u16 n;
  397. u16 k;
  398. };
  399. /* The size in bits of the FLL divide multiplied by 10
  400. * to allow rounding later */
  401. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  402. static struct {
  403. unsigned int min;
  404. unsigned int max;
  405. u16 fll_fratio;
  406. int ratio;
  407. } fll_fratios[] = {
  408. { 0, 64000, 4, 16 },
  409. { 64000, 128000, 3, 8 },
  410. { 128000, 256000, 2, 4 },
  411. { 256000, 1000000, 1, 2 },
  412. { 1000000, 13500000, 0, 1 },
  413. };
  414. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  415. unsigned int Fout)
  416. {
  417. u64 Kpart;
  418. unsigned int K, Ndiv, Nmod, target;
  419. unsigned int div;
  420. int i;
  421. /* Fref must be <=13.5MHz */
  422. div = 1;
  423. while ((Fref / div) > 13500000) {
  424. div *= 2;
  425. if (div > 8) {
  426. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  427. Fref);
  428. return -EINVAL;
  429. }
  430. }
  431. fll_div->fll_clk_ref_div = div / 2;
  432. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  433. /* Apply the division for our remaining calculations */
  434. Fref /= div;
  435. /* Fvco should be 90-100MHz; don't check the upper bound */
  436. div = 0;
  437. target = Fout * 2;
  438. while (target < 90000000) {
  439. div++;
  440. target *= 2;
  441. if (div > 7) {
  442. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  443. Fout);
  444. return -EINVAL;
  445. }
  446. }
  447. fll_div->fll_outdiv = div;
  448. pr_debug("Fvco=%dHz\n", target);
  449. /* Find an appropriate FLL_FRATIO and factor it out of the target */
  450. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  451. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  452. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  453. target /= fll_fratios[i].ratio;
  454. break;
  455. }
  456. }
  457. if (i == ARRAY_SIZE(fll_fratios)) {
  458. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  459. return -EINVAL;
  460. }
  461. /* Now, calculate N.K */
  462. Ndiv = target / Fref;
  463. fll_div->n = Ndiv;
  464. Nmod = target % Fref;
  465. pr_debug("Nmod=%d\n", Nmod);
  466. /* Calculate fractional part - scale up so we can round. */
  467. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  468. do_div(Kpart, Fref);
  469. K = Kpart & 0xFFFFFFFF;
  470. if ((K % 10) >= 5)
  471. K += 5;
  472. /* Move down to proper range now rounding is done */
  473. fll_div->k = K / 10;
  474. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  475. fll_div->n, fll_div->k,
  476. fll_div->fll_fratio, fll_div->fll_outdiv,
  477. fll_div->fll_clk_ref_div);
  478. return 0;
  479. }
  480. static int wm9081_set_fll(struct snd_soc_component *component, int fll_id,
  481. unsigned int Fref, unsigned int Fout)
  482. {
  483. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  484. u16 reg1, reg4, reg5;
  485. struct _fll_div fll_div;
  486. int ret;
  487. int clk_sys_reg;
  488. /* Any change? */
  489. if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
  490. return 0;
  491. /* Disable the FLL */
  492. if (Fout == 0) {
  493. dev_dbg(component->dev, "FLL disabled\n");
  494. wm9081->fll_fref = 0;
  495. wm9081->fll_fout = 0;
  496. return 0;
  497. }
  498. ret = fll_factors(&fll_div, Fref, Fout);
  499. if (ret != 0)
  500. return ret;
  501. reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5);
  502. reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
  503. switch (fll_id) {
  504. case WM9081_SYSCLK_FLL_MCLK:
  505. reg5 |= 0x1;
  506. break;
  507. default:
  508. dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
  509. return -EINVAL;
  510. }
  511. /* Disable CLK_SYS while we reconfigure */
  512. clk_sys_reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
  513. if (clk_sys_reg & WM9081_CLK_SYS_ENA)
  514. snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3,
  515. clk_sys_reg & ~WM9081_CLK_SYS_ENA);
  516. /* Any FLL configuration change requires that the FLL be
  517. * disabled first. */
  518. reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1);
  519. reg1 &= ~WM9081_FLL_ENA;
  520. snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
  521. /* Apply the configuration */
  522. if (fll_div.k)
  523. reg1 |= WM9081_FLL_FRAC_MASK;
  524. else
  525. reg1 &= ~WM9081_FLL_FRAC_MASK;
  526. snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
  527. snd_soc_component_write(component, WM9081_FLL_CONTROL_2,
  528. (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
  529. (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
  530. snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
  531. reg4 = snd_soc_component_read(component, WM9081_FLL_CONTROL_4);
  532. reg4 &= ~WM9081_FLL_N_MASK;
  533. reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
  534. snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4);
  535. reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
  536. reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
  537. snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);
  538. /* Set gain to the recommended value */
  539. snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4,
  540. WM9081_FLL_GAIN_MASK, 0);
  541. /* Enable the FLL */
  542. snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
  543. /* Then bring CLK_SYS up again if it was disabled */
  544. if (clk_sys_reg & WM9081_CLK_SYS_ENA)
  545. snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
  546. dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
  547. wm9081->fll_fref = Fref;
  548. wm9081->fll_fout = Fout;
  549. return 0;
  550. }
  551. static int configure_clock(struct snd_soc_component *component)
  552. {
  553. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  554. int new_sysclk, i, target;
  555. unsigned int reg;
  556. int ret = 0;
  557. int mclkdiv = 0;
  558. int fll = 0;
  559. switch (wm9081->sysclk_source) {
  560. case WM9081_SYSCLK_MCLK:
  561. if (wm9081->mclk_rate > 12225000) {
  562. mclkdiv = 1;
  563. wm9081->sysclk_rate = wm9081->mclk_rate / 2;
  564. } else {
  565. wm9081->sysclk_rate = wm9081->mclk_rate;
  566. }
  567. wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0);
  568. break;
  569. case WM9081_SYSCLK_FLL_MCLK:
  570. /* If we have a sample rate calculate a CLK_SYS that
  571. * gives us a suitable DAC configuration, plus BCLK.
  572. * Ideally we would check to see if we can clock
  573. * directly from MCLK and only use the FLL if this is
  574. * not the case, though care must be taken with free
  575. * running mode.
  576. */
  577. if (wm9081->master && wm9081->bclk) {
  578. /* Make sure we can generate CLK_SYS and BCLK
  579. * and that we've got 3MHz for optimal
  580. * performance. */
  581. for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
  582. target = wm9081->fs * clk_sys_rates[i].ratio;
  583. new_sysclk = target;
  584. if (target >= wm9081->bclk &&
  585. target > 3000000)
  586. break;
  587. }
  588. if (i == ARRAY_SIZE(clk_sys_rates))
  589. return -EINVAL;
  590. } else if (wm9081->fs) {
  591. for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
  592. new_sysclk = clk_sys_rates[i].ratio
  593. * wm9081->fs;
  594. if (new_sysclk > 3000000)
  595. break;
  596. }
  597. if (i == ARRAY_SIZE(clk_sys_rates))
  598. return -EINVAL;
  599. } else {
  600. new_sysclk = 12288000;
  601. }
  602. ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK,
  603. wm9081->mclk_rate, new_sysclk);
  604. if (ret == 0) {
  605. wm9081->sysclk_rate = new_sysclk;
  606. /* Switch SYSCLK over to FLL */
  607. fll = 1;
  608. } else {
  609. wm9081->sysclk_rate = wm9081->mclk_rate;
  610. }
  611. break;
  612. default:
  613. return -EINVAL;
  614. }
  615. reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_1);
  616. if (mclkdiv)
  617. reg |= WM9081_MCLKDIV2;
  618. else
  619. reg &= ~WM9081_MCLKDIV2;
  620. snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg);
  621. reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
  622. if (fll)
  623. reg |= WM9081_CLK_SRC_SEL;
  624. else
  625. reg &= ~WM9081_CLK_SRC_SEL;
  626. snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg);
  627. dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
  628. return ret;
  629. }
  630. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  631. struct snd_kcontrol *kcontrol, int event)
  632. {
  633. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  634. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  635. /* This should be done on init() for bypass paths */
  636. switch (wm9081->sysclk_source) {
  637. case WM9081_SYSCLK_MCLK:
  638. dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
  639. break;
  640. case WM9081_SYSCLK_FLL_MCLK:
  641. dev_dbg(component->dev, "Using %dHz MCLK with FLL\n",
  642. wm9081->mclk_rate);
  643. break;
  644. default:
  645. dev_err(component->dev, "System clock not configured\n");
  646. return -EINVAL;
  647. }
  648. switch (event) {
  649. case SND_SOC_DAPM_PRE_PMU:
  650. configure_clock(component);
  651. break;
  652. case SND_SOC_DAPM_POST_PMD:
  653. /* Disable the FLL if it's running */
  654. wm9081_set_fll(component, 0, 0, 0);
  655. break;
  656. }
  657. return 0;
  658. }
  659. static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
  660. SND_SOC_DAPM_INPUT("IN1"),
  661. SND_SOC_DAPM_INPUT("IN2"),
  662. SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
  663. SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
  664. mixer, ARRAY_SIZE(mixer)),
  665. SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
  666. SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
  667. SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
  668. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  669. SND_SOC_DAPM_OUTPUT("SPKN"),
  670. SND_SOC_DAPM_OUTPUT("SPKP"),
  671. SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
  672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  673. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
  674. SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
  675. SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
  676. };
  677. static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
  678. { "DAC", NULL, "CLK_SYS" },
  679. { "DAC", NULL, "CLK_DSP" },
  680. { "DAC", NULL, "AIF" },
  681. { "Mixer", "IN1 Switch", "IN1" },
  682. { "Mixer", "IN2 Switch", "IN2" },
  683. { "Mixer", "Playback Switch", "DAC" },
  684. { "LINEOUT PGA", NULL, "Mixer" },
  685. { "LINEOUT PGA", NULL, "TOCLK" },
  686. { "LINEOUT PGA", NULL, "CLK_SYS" },
  687. { "LINEOUT", NULL, "LINEOUT PGA" },
  688. { "Speaker PGA", NULL, "Mixer" },
  689. { "Speaker PGA", NULL, "TOCLK" },
  690. { "Speaker PGA", NULL, "CLK_SYS" },
  691. { "Speaker", NULL, "Speaker PGA" },
  692. { "Speaker", NULL, "TSENSE" },
  693. { "SPKN", NULL, "Speaker" },
  694. { "SPKP", NULL, "Speaker" },
  695. };
  696. static int wm9081_set_bias_level(struct snd_soc_component *component,
  697. enum snd_soc_bias_level level)
  698. {
  699. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  700. switch (level) {
  701. case SND_SOC_BIAS_ON:
  702. break;
  703. case SND_SOC_BIAS_PREPARE:
  704. /* VMID=2*40k */
  705. snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
  706. WM9081_VMID_SEL_MASK, 0x2);
  707. /* Normal bias current */
  708. snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
  709. WM9081_STBY_BIAS_ENA, 0);
  710. break;
  711. case SND_SOC_BIAS_STANDBY:
  712. /* Initial cold start */
  713. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  714. regcache_cache_only(wm9081->regmap, false);
  715. regcache_sync(wm9081->regmap);
  716. /* Disable LINEOUT discharge */
  717. snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
  718. WM9081_LINEOUT_DISCH, 0);
  719. /* Select startup bias source */
  720. snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
  721. WM9081_BIAS_SRC | WM9081_BIAS_ENA,
  722. WM9081_BIAS_SRC | WM9081_BIAS_ENA);
  723. /* VMID 2*4k; Soft VMID ramp enable */
  724. snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
  725. WM9081_VMID_RAMP |
  726. WM9081_VMID_SEL_MASK,
  727. WM9081_VMID_RAMP | 0x6);
  728. mdelay(100);
  729. /* Normal bias enable & soft start off */
  730. snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
  731. WM9081_VMID_RAMP, 0);
  732. /* Standard bias source */
  733. snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
  734. WM9081_BIAS_SRC, 0);
  735. }
  736. /* VMID 2*240k */
  737. snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
  738. WM9081_VMID_SEL_MASK, 0x04);
  739. /* Standby bias current on */
  740. snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
  741. WM9081_STBY_BIAS_ENA,
  742. WM9081_STBY_BIAS_ENA);
  743. break;
  744. case SND_SOC_BIAS_OFF:
  745. /* Startup bias source and disable bias */
  746. snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
  747. WM9081_BIAS_SRC | WM9081_BIAS_ENA,
  748. WM9081_BIAS_SRC);
  749. /* Disable VMID with soft ramping */
  750. snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
  751. WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
  752. WM9081_VMID_RAMP);
  753. /* Actively discharge LINEOUT */
  754. snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
  755. WM9081_LINEOUT_DISCH,
  756. WM9081_LINEOUT_DISCH);
  757. regcache_cache_only(wm9081->regmap, true);
  758. break;
  759. }
  760. return 0;
  761. }
  762. static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
  763. unsigned int fmt)
  764. {
  765. struct snd_soc_component *component = dai->component;
  766. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  767. unsigned int aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
  768. aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
  769. WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
  770. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  771. case SND_SOC_DAIFMT_CBS_CFS:
  772. wm9081->master = 0;
  773. break;
  774. case SND_SOC_DAIFMT_CBS_CFM:
  775. aif2 |= WM9081_LRCLK_DIR;
  776. wm9081->master = 1;
  777. break;
  778. case SND_SOC_DAIFMT_CBM_CFS:
  779. aif2 |= WM9081_BCLK_DIR;
  780. wm9081->master = 1;
  781. break;
  782. case SND_SOC_DAIFMT_CBM_CFM:
  783. aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
  784. wm9081->master = 1;
  785. break;
  786. default:
  787. return -EINVAL;
  788. }
  789. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  790. case SND_SOC_DAIFMT_DSP_B:
  791. aif2 |= WM9081_AIF_LRCLK_INV;
  792. fallthrough;
  793. case SND_SOC_DAIFMT_DSP_A:
  794. aif2 |= 0x3;
  795. break;
  796. case SND_SOC_DAIFMT_I2S:
  797. aif2 |= 0x2;
  798. break;
  799. case SND_SOC_DAIFMT_RIGHT_J:
  800. break;
  801. case SND_SOC_DAIFMT_LEFT_J:
  802. aif2 |= 0x1;
  803. break;
  804. default:
  805. return -EINVAL;
  806. }
  807. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  808. case SND_SOC_DAIFMT_DSP_A:
  809. case SND_SOC_DAIFMT_DSP_B:
  810. /* frame inversion not valid for DSP modes */
  811. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  812. case SND_SOC_DAIFMT_NB_NF:
  813. break;
  814. case SND_SOC_DAIFMT_IB_NF:
  815. aif2 |= WM9081_AIF_BCLK_INV;
  816. break;
  817. default:
  818. return -EINVAL;
  819. }
  820. break;
  821. case SND_SOC_DAIFMT_I2S:
  822. case SND_SOC_DAIFMT_RIGHT_J:
  823. case SND_SOC_DAIFMT_LEFT_J:
  824. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  825. case SND_SOC_DAIFMT_NB_NF:
  826. break;
  827. case SND_SOC_DAIFMT_IB_IF:
  828. aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
  829. break;
  830. case SND_SOC_DAIFMT_IB_NF:
  831. aif2 |= WM9081_AIF_BCLK_INV;
  832. break;
  833. case SND_SOC_DAIFMT_NB_IF:
  834. aif2 |= WM9081_AIF_LRCLK_INV;
  835. break;
  836. default:
  837. return -EINVAL;
  838. }
  839. break;
  840. default:
  841. return -EINVAL;
  842. }
  843. snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
  844. return 0;
  845. }
  846. static int wm9081_hw_params(struct snd_pcm_substream *substream,
  847. struct snd_pcm_hw_params *params,
  848. struct snd_soc_dai *dai)
  849. {
  850. struct snd_soc_component *component = dai->component;
  851. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  852. int ret, i, best, best_val, cur_val;
  853. unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
  854. clk_ctrl2 = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_2);
  855. clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
  856. aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
  857. aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
  858. aif2 &= ~WM9081_AIF_WL_MASK;
  859. aif3 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_3);
  860. aif3 &= ~WM9081_BCLK_DIV_MASK;
  861. aif4 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_4);
  862. aif4 &= ~WM9081_LRCLK_RATE_MASK;
  863. wm9081->fs = params_rate(params);
  864. if (wm9081->tdm_width) {
  865. /* If TDM is set up then that fixes our BCLK. */
  866. int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
  867. WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
  868. wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
  869. } else {
  870. /* Otherwise work out a BCLK from the sample size */
  871. wm9081->bclk = 2 * wm9081->fs;
  872. switch (params_width(params)) {
  873. case 16:
  874. wm9081->bclk *= 16;
  875. break;
  876. case 20:
  877. wm9081->bclk *= 20;
  878. aif2 |= 0x4;
  879. break;
  880. case 24:
  881. wm9081->bclk *= 24;
  882. aif2 |= 0x8;
  883. break;
  884. case 32:
  885. wm9081->bclk *= 32;
  886. aif2 |= 0xc;
  887. break;
  888. default:
  889. return -EINVAL;
  890. }
  891. }
  892. dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk);
  893. ret = configure_clock(component);
  894. if (ret != 0)
  895. return ret;
  896. /* Select nearest CLK_SYS_RATE */
  897. best = 0;
  898. best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
  899. - wm9081->fs);
  900. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  901. cur_val = abs((wm9081->sysclk_rate /
  902. clk_sys_rates[i].ratio) - wm9081->fs);
  903. if (cur_val < best_val) {
  904. best = i;
  905. best_val = cur_val;
  906. }
  907. }
  908. dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
  909. clk_sys_rates[best].ratio);
  910. clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
  911. << WM9081_CLK_SYS_RATE_SHIFT);
  912. /* SAMPLE_RATE */
  913. best = 0;
  914. best_val = abs(wm9081->fs - sample_rates[0].rate);
  915. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  916. /* Closest match */
  917. cur_val = abs(wm9081->fs - sample_rates[i].rate);
  918. if (cur_val < best_val) {
  919. best = i;
  920. best_val = cur_val;
  921. }
  922. }
  923. dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
  924. sample_rates[best].rate);
  925. clk_ctrl2 |= (sample_rates[best].sample_rate
  926. << WM9081_SAMPLE_RATE_SHIFT);
  927. /* BCLK_DIV */
  928. best = 0;
  929. best_val = INT_MAX;
  930. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  931. cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
  932. - wm9081->bclk;
  933. if (cur_val < 0) /* Table is sorted */
  934. break;
  935. if (cur_val < best_val) {
  936. best = i;
  937. best_val = cur_val;
  938. }
  939. }
  940. wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
  941. dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  942. bclk_divs[best].div, wm9081->bclk);
  943. aif3 |= bclk_divs[best].bclk_div;
  944. /* LRCLK is a simple fraction of BCLK */
  945. dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
  946. aif4 |= wm9081->bclk / wm9081->fs;
  947. /* Apply a ReTune Mobile configuration if it's in use */
  948. if (wm9081->pdata.num_retune_configs) {
  949. struct wm9081_pdata *pdata = &wm9081->pdata;
  950. struct wm9081_retune_mobile_setting *s;
  951. int eq1;
  952. best = 0;
  953. best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
  954. for (i = 0; i < pdata->num_retune_configs; i++) {
  955. cur_val = abs(pdata->retune_configs[i].rate -
  956. wm9081->fs);
  957. if (cur_val < best_val) {
  958. best_val = cur_val;
  959. best = i;
  960. }
  961. }
  962. s = &pdata->retune_configs[best];
  963. dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
  964. s->name, s->rate);
  965. /* If the EQ is enabled then disable it while we write out */
  966. eq1 = snd_soc_component_read(component, WM9081_EQ_1) & WM9081_EQ_ENA;
  967. if (eq1 & WM9081_EQ_ENA)
  968. snd_soc_component_write(component, WM9081_EQ_1, 0);
  969. /* Write out the other values */
  970. for (i = 1; i < ARRAY_SIZE(s->config); i++)
  971. snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]);
  972. eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
  973. snd_soc_component_write(component, WM9081_EQ_1, eq1);
  974. }
  975. snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
  976. snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
  977. snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3);
  978. snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4);
  979. return 0;
  980. }
  981. static int wm9081_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  982. {
  983. struct snd_soc_component *component = codec_dai->component;
  984. unsigned int reg;
  985. reg = snd_soc_component_read(component, WM9081_DAC_DIGITAL_2);
  986. if (mute)
  987. reg |= WM9081_DAC_MUTE;
  988. else
  989. reg &= ~WM9081_DAC_MUTE;
  990. snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg);
  991. return 0;
  992. }
  993. static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id,
  994. int source, unsigned int freq, int dir)
  995. {
  996. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  997. switch (clk_id) {
  998. case WM9081_SYSCLK_MCLK:
  999. case WM9081_SYSCLK_FLL_MCLK:
  1000. wm9081->sysclk_source = clk_id;
  1001. wm9081->mclk_rate = freq;
  1002. break;
  1003. default:
  1004. return -EINVAL;
  1005. }
  1006. return 0;
  1007. }
  1008. static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
  1009. unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
  1010. {
  1011. struct snd_soc_component *component = dai->component;
  1012. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  1013. unsigned int aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
  1014. aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
  1015. if (slots < 0 || slots > 4)
  1016. return -EINVAL;
  1017. wm9081->tdm_width = slot_width;
  1018. if (slots == 0)
  1019. slots = 1;
  1020. aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
  1021. switch (rx_mask) {
  1022. case 1:
  1023. break;
  1024. case 2:
  1025. aif1 |= 0x10;
  1026. break;
  1027. case 4:
  1028. aif1 |= 0x20;
  1029. break;
  1030. case 8:
  1031. aif1 |= 0x30;
  1032. break;
  1033. default:
  1034. return -EINVAL;
  1035. }
  1036. snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1);
  1037. return 0;
  1038. }
  1039. #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
  1040. #define WM9081_FORMATS \
  1041. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1042. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1043. static const struct snd_soc_dai_ops wm9081_dai_ops = {
  1044. .hw_params = wm9081_hw_params,
  1045. .set_fmt = wm9081_set_dai_fmt,
  1046. .mute_stream = wm9081_mute,
  1047. .set_tdm_slot = wm9081_set_tdm_slot,
  1048. .no_capture_mute = 1,
  1049. };
  1050. /* We report two channels because the CODEC processes a stereo signal, even
  1051. * though it is only capable of handling a mono output.
  1052. */
  1053. static struct snd_soc_dai_driver wm9081_dai = {
  1054. .name = "wm9081-hifi",
  1055. .playback = {
  1056. .stream_name = "AIF",
  1057. .channels_min = 1,
  1058. .channels_max = 2,
  1059. .rates = WM9081_RATES,
  1060. .formats = WM9081_FORMATS,
  1061. },
  1062. .ops = &wm9081_dai_ops,
  1063. };
  1064. static int wm9081_probe(struct snd_soc_component *component)
  1065. {
  1066. struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
  1067. /* Enable zero cross by default */
  1068. snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT,
  1069. WM9081_LINEOUTZC, WM9081_LINEOUTZC);
  1070. snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA,
  1071. WM9081_SPKPGAZC, WM9081_SPKPGAZC);
  1072. if (!wm9081->pdata.num_retune_configs) {
  1073. dev_dbg(component->dev,
  1074. "No ReTune Mobile data, using normal EQ\n");
  1075. snd_soc_add_component_controls(component, wm9081_eq_controls,
  1076. ARRAY_SIZE(wm9081_eq_controls));
  1077. }
  1078. return 0;
  1079. }
  1080. static const struct snd_soc_component_driver soc_component_dev_wm9081 = {
  1081. .probe = wm9081_probe,
  1082. .set_sysclk = wm9081_set_sysclk,
  1083. .set_bias_level = wm9081_set_bias_level,
  1084. .controls = wm9081_snd_controls,
  1085. .num_controls = ARRAY_SIZE(wm9081_snd_controls),
  1086. .dapm_widgets = wm9081_dapm_widgets,
  1087. .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
  1088. .dapm_routes = wm9081_audio_paths,
  1089. .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
  1090. .use_pmdown_time = 1,
  1091. .endianness = 1,
  1092. };
  1093. static const struct regmap_config wm9081_regmap = {
  1094. .reg_bits = 8,
  1095. .val_bits = 16,
  1096. .max_register = WM9081_MAX_REGISTER,
  1097. .reg_defaults = wm9081_reg,
  1098. .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
  1099. .volatile_reg = wm9081_volatile_register,
  1100. .readable_reg = wm9081_readable_register,
  1101. .cache_type = REGCACHE_RBTREE,
  1102. };
  1103. static int wm9081_i2c_probe(struct i2c_client *i2c)
  1104. {
  1105. struct wm9081_priv *wm9081;
  1106. unsigned int reg;
  1107. int ret;
  1108. wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
  1109. GFP_KERNEL);
  1110. if (wm9081 == NULL)
  1111. return -ENOMEM;
  1112. i2c_set_clientdata(i2c, wm9081);
  1113. wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap);
  1114. if (IS_ERR(wm9081->regmap)) {
  1115. ret = PTR_ERR(wm9081->regmap);
  1116. dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
  1117. return ret;
  1118. }
  1119. ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
  1120. if (ret != 0) {
  1121. dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
  1122. return ret;
  1123. }
  1124. if (reg != 0x9081) {
  1125. dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
  1126. return -EINVAL;
  1127. }
  1128. ret = wm9081_reset(wm9081->regmap);
  1129. if (ret < 0) {
  1130. dev_err(&i2c->dev, "Failed to issue reset\n");
  1131. return ret;
  1132. }
  1133. if (dev_get_platdata(&i2c->dev))
  1134. memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
  1135. sizeof(wm9081->pdata));
  1136. reg = 0;
  1137. if (wm9081->pdata.irq_high)
  1138. reg |= WM9081_IRQ_POL;
  1139. if (!wm9081->pdata.irq_cmos)
  1140. reg |= WM9081_IRQ_OP_CTRL;
  1141. regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
  1142. WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
  1143. regcache_cache_only(wm9081->regmap, true);
  1144. ret = devm_snd_soc_register_component(&i2c->dev,
  1145. &soc_component_dev_wm9081, &wm9081_dai, 1);
  1146. if (ret < 0)
  1147. return ret;
  1148. return 0;
  1149. }
  1150. static void wm9081_i2c_remove(struct i2c_client *client)
  1151. {}
  1152. static const struct i2c_device_id wm9081_i2c_id[] = {
  1153. { "wm9081", 0 },
  1154. { }
  1155. };
  1156. MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
  1157. static struct i2c_driver wm9081_i2c_driver = {
  1158. .driver = {
  1159. .name = "wm9081",
  1160. },
  1161. .probe_new = wm9081_i2c_probe,
  1162. .remove = wm9081_i2c_remove,
  1163. .id_table = wm9081_i2c_id,
  1164. };
  1165. module_i2c_driver(wm9081_i2c_driver);
  1166. MODULE_DESCRIPTION("ASoC WM9081 driver");
  1167. MODULE_AUTHOR("Mark Brown <[email protected]>");
  1168. MODULE_LICENSE("GPL");