wm8995.c 61 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8995.c -- WM8995 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Wolfson Microelectronics plc
  6. *
  7. * Author: Dimitris Papastamos <[email protected]>
  8. *
  9. * Based on wm8994.c and wm_hubs.c by Mark Brown
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/regmap.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include "wm8995.h"
  29. #define WM8995_NUM_SUPPLIES 8
  30. static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
  31. "DCVDD",
  32. "DBVDD1",
  33. "DBVDD2",
  34. "DBVDD3",
  35. "AVDD1",
  36. "AVDD2",
  37. "CPVDD",
  38. "MICVDD"
  39. };
  40. static const struct reg_default wm8995_reg_defaults[] = {
  41. { 0, 0x8995 },
  42. { 5, 0x0100 },
  43. { 16, 0x000b },
  44. { 17, 0x000b },
  45. { 24, 0x02c0 },
  46. { 25, 0x02c0 },
  47. { 26, 0x02c0 },
  48. { 27, 0x02c0 },
  49. { 28, 0x000f },
  50. { 32, 0x0005 },
  51. { 33, 0x0005 },
  52. { 40, 0x0003 },
  53. { 41, 0x0013 },
  54. { 48, 0x0004 },
  55. { 56, 0x09f8 },
  56. { 64, 0x1f25 },
  57. { 69, 0x0004 },
  58. { 82, 0xaaaa },
  59. { 84, 0x2a2a },
  60. { 146, 0x0060 },
  61. { 256, 0x0002 },
  62. { 257, 0x8004 },
  63. { 520, 0x0010 },
  64. { 528, 0x0083 },
  65. { 529, 0x0083 },
  66. { 548, 0x0c80 },
  67. { 580, 0x0c80 },
  68. { 768, 0x4050 },
  69. { 769, 0x4000 },
  70. { 771, 0x0040 },
  71. { 772, 0x0040 },
  72. { 773, 0x0040 },
  73. { 774, 0x0004 },
  74. { 775, 0x0100 },
  75. { 784, 0x4050 },
  76. { 785, 0x4000 },
  77. { 787, 0x0040 },
  78. { 788, 0x0040 },
  79. { 789, 0x0040 },
  80. { 1024, 0x00c0 },
  81. { 1025, 0x00c0 },
  82. { 1026, 0x00c0 },
  83. { 1027, 0x00c0 },
  84. { 1028, 0x00c0 },
  85. { 1029, 0x00c0 },
  86. { 1030, 0x00c0 },
  87. { 1031, 0x00c0 },
  88. { 1056, 0x0200 },
  89. { 1057, 0x0010 },
  90. { 1058, 0x0200 },
  91. { 1059, 0x0010 },
  92. { 1088, 0x0098 },
  93. { 1089, 0x0845 },
  94. { 1104, 0x0098 },
  95. { 1105, 0x0845 },
  96. { 1152, 0x6318 },
  97. { 1153, 0x6300 },
  98. { 1154, 0x0fca },
  99. { 1155, 0x0400 },
  100. { 1156, 0x00d8 },
  101. { 1157, 0x1eb5 },
  102. { 1158, 0xf145 },
  103. { 1159, 0x0b75 },
  104. { 1160, 0x01c5 },
  105. { 1161, 0x1c58 },
  106. { 1162, 0xf373 },
  107. { 1163, 0x0a54 },
  108. { 1164, 0x0558 },
  109. { 1165, 0x168e },
  110. { 1166, 0xf829 },
  111. { 1167, 0x07ad },
  112. { 1168, 0x1103 },
  113. { 1169, 0x0564 },
  114. { 1170, 0x0559 },
  115. { 1171, 0x4000 },
  116. { 1184, 0x6318 },
  117. { 1185, 0x6300 },
  118. { 1186, 0x0fca },
  119. { 1187, 0x0400 },
  120. { 1188, 0x00d8 },
  121. { 1189, 0x1eb5 },
  122. { 1190, 0xf145 },
  123. { 1191, 0x0b75 },
  124. { 1192, 0x01c5 },
  125. { 1193, 0x1c58 },
  126. { 1194, 0xf373 },
  127. { 1195, 0x0a54 },
  128. { 1196, 0x0558 },
  129. { 1197, 0x168e },
  130. { 1198, 0xf829 },
  131. { 1199, 0x07ad },
  132. { 1200, 0x1103 },
  133. { 1201, 0x0564 },
  134. { 1202, 0x0559 },
  135. { 1203, 0x4000 },
  136. { 1280, 0x00c0 },
  137. { 1281, 0x00c0 },
  138. { 1282, 0x00c0 },
  139. { 1283, 0x00c0 },
  140. { 1312, 0x0200 },
  141. { 1313, 0x0010 },
  142. { 1344, 0x0098 },
  143. { 1345, 0x0845 },
  144. { 1408, 0x6318 },
  145. { 1409, 0x6300 },
  146. { 1410, 0x0fca },
  147. { 1411, 0x0400 },
  148. { 1412, 0x00d8 },
  149. { 1413, 0x1eb5 },
  150. { 1414, 0xf145 },
  151. { 1415, 0x0b75 },
  152. { 1416, 0x01c5 },
  153. { 1417, 0x1c58 },
  154. { 1418, 0xf373 },
  155. { 1419, 0x0a54 },
  156. { 1420, 0x0558 },
  157. { 1421, 0x168e },
  158. { 1422, 0xf829 },
  159. { 1423, 0x07ad },
  160. { 1424, 0x1103 },
  161. { 1425, 0x0564 },
  162. { 1426, 0x0559 },
  163. { 1427, 0x4000 },
  164. { 1568, 0x0002 },
  165. { 1792, 0xa100 },
  166. { 1793, 0xa101 },
  167. { 1794, 0xa101 },
  168. { 1795, 0xa101 },
  169. { 1796, 0xa101 },
  170. { 1797, 0xa101 },
  171. { 1798, 0xa101 },
  172. { 1799, 0xa101 },
  173. { 1800, 0xa101 },
  174. { 1801, 0xa101 },
  175. { 1802, 0xa101 },
  176. { 1803, 0xa101 },
  177. { 1804, 0xa101 },
  178. { 1805, 0xa101 },
  179. { 1825, 0x0055 },
  180. { 1848, 0x3fff },
  181. { 1849, 0x1fff },
  182. { 2049, 0x0001 },
  183. { 2050, 0x0069 },
  184. { 2056, 0x0002 },
  185. { 2057, 0x0003 },
  186. { 2058, 0x0069 },
  187. { 12288, 0x0001 },
  188. { 12289, 0x0001 },
  189. { 12291, 0x0006 },
  190. { 12292, 0x0040 },
  191. { 12293, 0x0001 },
  192. { 12294, 0x000f },
  193. { 12295, 0x0006 },
  194. { 12296, 0x0001 },
  195. { 12297, 0x0003 },
  196. { 12298, 0x0104 },
  197. { 12300, 0x0060 },
  198. { 12301, 0x0011 },
  199. { 12302, 0x0401 },
  200. { 12304, 0x0050 },
  201. { 12305, 0x0003 },
  202. { 12306, 0x0100 },
  203. { 12308, 0x0051 },
  204. { 12309, 0x0003 },
  205. { 12310, 0x0104 },
  206. { 12311, 0x000a },
  207. { 12312, 0x0060 },
  208. { 12313, 0x003b },
  209. { 12314, 0x0502 },
  210. { 12315, 0x0100 },
  211. { 12316, 0x2fff },
  212. { 12320, 0x2fff },
  213. { 12324, 0x2fff },
  214. { 12328, 0x2fff },
  215. { 12332, 0x2fff },
  216. { 12336, 0x2fff },
  217. { 12340, 0x2fff },
  218. { 12344, 0x2fff },
  219. { 12348, 0x2fff },
  220. { 12352, 0x0001 },
  221. { 12353, 0x0001 },
  222. { 12355, 0x0006 },
  223. { 12356, 0x0040 },
  224. { 12357, 0x0001 },
  225. { 12358, 0x000f },
  226. { 12359, 0x0006 },
  227. { 12360, 0x0001 },
  228. { 12361, 0x0003 },
  229. { 12362, 0x0104 },
  230. { 12364, 0x0060 },
  231. { 12365, 0x0011 },
  232. { 12366, 0x0401 },
  233. { 12368, 0x0050 },
  234. { 12369, 0x0003 },
  235. { 12370, 0x0100 },
  236. { 12372, 0x0060 },
  237. { 12373, 0x003b },
  238. { 12374, 0x0502 },
  239. { 12375, 0x0100 },
  240. { 12376, 0x2fff },
  241. { 12380, 0x2fff },
  242. { 12384, 0x2fff },
  243. { 12388, 0x2fff },
  244. { 12392, 0x2fff },
  245. { 12396, 0x2fff },
  246. { 12400, 0x2fff },
  247. { 12404, 0x2fff },
  248. { 12408, 0x2fff },
  249. { 12412, 0x2fff },
  250. { 12416, 0x0001 },
  251. { 12417, 0x0001 },
  252. { 12419, 0x0006 },
  253. { 12420, 0x0040 },
  254. { 12421, 0x0001 },
  255. { 12422, 0x000f },
  256. { 12423, 0x0006 },
  257. { 12424, 0x0001 },
  258. { 12425, 0x0003 },
  259. { 12426, 0x0106 },
  260. { 12428, 0x0061 },
  261. { 12429, 0x0011 },
  262. { 12430, 0x0401 },
  263. { 12432, 0x0050 },
  264. { 12433, 0x0003 },
  265. { 12434, 0x0102 },
  266. { 12436, 0x0051 },
  267. { 12437, 0x0003 },
  268. { 12438, 0x0106 },
  269. { 12439, 0x000a },
  270. { 12440, 0x0061 },
  271. { 12441, 0x003b },
  272. { 12442, 0x0502 },
  273. { 12443, 0x0100 },
  274. { 12444, 0x2fff },
  275. { 12448, 0x2fff },
  276. { 12452, 0x2fff },
  277. { 12456, 0x2fff },
  278. { 12460, 0x2fff },
  279. { 12464, 0x2fff },
  280. { 12468, 0x2fff },
  281. { 12472, 0x2fff },
  282. { 12476, 0x2fff },
  283. { 12480, 0x0001 },
  284. { 12481, 0x0001 },
  285. { 12483, 0x0006 },
  286. { 12484, 0x0040 },
  287. { 12485, 0x0001 },
  288. { 12486, 0x000f },
  289. { 12487, 0x0006 },
  290. { 12488, 0x0001 },
  291. { 12489, 0x0003 },
  292. { 12490, 0x0106 },
  293. { 12492, 0x0061 },
  294. { 12493, 0x0011 },
  295. { 12494, 0x0401 },
  296. { 12496, 0x0050 },
  297. { 12497, 0x0003 },
  298. { 12498, 0x0102 },
  299. { 12500, 0x0061 },
  300. { 12501, 0x003b },
  301. { 12502, 0x0502 },
  302. { 12503, 0x0100 },
  303. { 12504, 0x2fff },
  304. { 12508, 0x2fff },
  305. { 12512, 0x2fff },
  306. { 12516, 0x2fff },
  307. { 12520, 0x2fff },
  308. { 12524, 0x2fff },
  309. { 12528, 0x2fff },
  310. { 12532, 0x2fff },
  311. { 12536, 0x2fff },
  312. { 12540, 0x2fff },
  313. { 12544, 0x0060 },
  314. { 12546, 0x0601 },
  315. { 12548, 0x0050 },
  316. { 12550, 0x0100 },
  317. { 12552, 0x0001 },
  318. { 12554, 0x0104 },
  319. { 12555, 0x0100 },
  320. { 12556, 0x2fff },
  321. { 12560, 0x2fff },
  322. { 12564, 0x2fff },
  323. { 12568, 0x2fff },
  324. { 12572, 0x2fff },
  325. { 12576, 0x2fff },
  326. { 12580, 0x2fff },
  327. { 12584, 0x2fff },
  328. { 12588, 0x2fff },
  329. { 12592, 0x2fff },
  330. { 12596, 0x2fff },
  331. { 12600, 0x2fff },
  332. { 12604, 0x2fff },
  333. { 12608, 0x0061 },
  334. { 12610, 0x0601 },
  335. { 12612, 0x0050 },
  336. { 12614, 0x0102 },
  337. { 12616, 0x0001 },
  338. { 12618, 0x0106 },
  339. { 12619, 0x0100 },
  340. { 12620, 0x2fff },
  341. { 12624, 0x2fff },
  342. { 12628, 0x2fff },
  343. { 12632, 0x2fff },
  344. { 12636, 0x2fff },
  345. { 12640, 0x2fff },
  346. { 12644, 0x2fff },
  347. { 12648, 0x2fff },
  348. { 12652, 0x2fff },
  349. { 12656, 0x2fff },
  350. { 12660, 0x2fff },
  351. { 12664, 0x2fff },
  352. { 12668, 0x2fff },
  353. { 12672, 0x0060 },
  354. { 12674, 0x0601 },
  355. { 12676, 0x0061 },
  356. { 12678, 0x0601 },
  357. { 12680, 0x0050 },
  358. { 12682, 0x0300 },
  359. { 12684, 0x0001 },
  360. { 12686, 0x0304 },
  361. { 12688, 0x0040 },
  362. { 12690, 0x000f },
  363. { 12692, 0x0001 },
  364. { 12695, 0x0100 },
  365. };
  366. struct fll_config {
  367. int src;
  368. int in;
  369. int out;
  370. };
  371. struct wm8995_priv {
  372. struct regmap *regmap;
  373. int sysclk[2];
  374. int mclk[2];
  375. int aifclk[2];
  376. struct fll_config fll[2], fll_suspend[2];
  377. struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
  378. struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
  379. struct snd_soc_component *component;
  380. };
  381. /*
  382. * We can't use the same notifier block for more than one supply and
  383. * there's no way I can see to get from a callback to the caller
  384. * except container_of().
  385. */
  386. #define WM8995_REGULATOR_EVENT(n) \
  387. static int wm8995_regulator_event_##n(struct notifier_block *nb, \
  388. unsigned long event, void *data) \
  389. { \
  390. struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
  391. disable_nb[n]); \
  392. if (event & REGULATOR_EVENT_DISABLE) { \
  393. regcache_mark_dirty(wm8995->regmap); \
  394. } \
  395. return 0; \
  396. }
  397. WM8995_REGULATOR_EVENT(0)
  398. WM8995_REGULATOR_EVENT(1)
  399. WM8995_REGULATOR_EVENT(2)
  400. WM8995_REGULATOR_EVENT(3)
  401. WM8995_REGULATOR_EVENT(4)
  402. WM8995_REGULATOR_EVENT(5)
  403. WM8995_REGULATOR_EVENT(6)
  404. WM8995_REGULATOR_EVENT(7)
  405. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  406. static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
  407. static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
  408. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
  409. static const char *in1l_text[] = {
  410. "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
  411. };
  412. static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
  413. 2, in1l_text);
  414. static const char *in1r_text[] = {
  415. "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
  416. };
  417. static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
  418. 0, in1r_text);
  419. static const char *dmic_src_text[] = {
  420. "DMICDAT1", "DMICDAT2", "DMICDAT3"
  421. };
  422. static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
  423. 8, dmic_src_text);
  424. static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
  425. 6, dmic_src_text);
  426. static const struct snd_kcontrol_new wm8995_snd_controls[] = {
  427. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
  428. WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  429. SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
  430. WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
  431. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
  432. WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  433. SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
  434. WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
  435. SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
  436. WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  437. SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
  438. WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  439. SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
  440. WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  441. SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
  442. WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
  443. SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
  444. 4, 3, 0, in1l_boost_tlv),
  445. SOC_ENUM("IN1L Mode", in1l_enum),
  446. SOC_ENUM("IN1R Mode", in1r_enum),
  447. SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
  448. SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
  449. SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
  450. 24, 0, sidetone_tlv),
  451. SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
  452. 24, 0, sidetone_tlv),
  453. SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
  454. WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  455. SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
  456. WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
  457. SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
  458. WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
  459. };
  460. static void wm8995_update_class_w(struct snd_soc_component *component)
  461. {
  462. int enable = 1;
  463. int source = 0; /* GCC flow analysis can't track enable */
  464. int reg, reg_r;
  465. /* We also need the same setting for L/R and only one path */
  466. reg = snd_soc_component_read(component, WM8995_DAC1_LEFT_MIXER_ROUTING);
  467. switch (reg) {
  468. case WM8995_AIF2DACL_TO_DAC1L:
  469. dev_dbg(component->dev, "Class W source AIF2DAC\n");
  470. source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
  471. break;
  472. case WM8995_AIF1DAC2L_TO_DAC1L:
  473. dev_dbg(component->dev, "Class W source AIF1DAC2\n");
  474. source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
  475. break;
  476. case WM8995_AIF1DAC1L_TO_DAC1L:
  477. dev_dbg(component->dev, "Class W source AIF1DAC1\n");
  478. source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
  479. break;
  480. default:
  481. dev_dbg(component->dev, "DAC mixer setting: %x\n", reg);
  482. enable = 0;
  483. break;
  484. }
  485. reg_r = snd_soc_component_read(component, WM8995_DAC1_RIGHT_MIXER_ROUTING);
  486. if (reg_r != reg) {
  487. dev_dbg(component->dev, "Left and right DAC mixers different\n");
  488. enable = 0;
  489. }
  490. if (enable) {
  491. dev_dbg(component->dev, "Class W enabled\n");
  492. snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
  493. WM8995_CP_DYN_PWR_MASK |
  494. WM8995_CP_DYN_SRC_SEL_MASK,
  495. source | WM8995_CP_DYN_PWR);
  496. } else {
  497. dev_dbg(component->dev, "Class W disabled\n");
  498. snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
  499. WM8995_CP_DYN_PWR_MASK, 0);
  500. }
  501. }
  502. static int check_clk_sys(struct snd_soc_dapm_widget *source,
  503. struct snd_soc_dapm_widget *sink)
  504. {
  505. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  506. unsigned int reg;
  507. const char *clk;
  508. reg = snd_soc_component_read(component, WM8995_CLOCKING_1);
  509. /* Check what we're currently using for CLK_SYS */
  510. if (reg & WM8995_SYSCLK_SRC)
  511. clk = "AIF2CLK";
  512. else
  513. clk = "AIF1CLK";
  514. return !strcmp(source->name, clk);
  515. }
  516. static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
  517. struct snd_ctl_elem_value *ucontrol)
  518. {
  519. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  520. int ret;
  521. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  522. wm8995_update_class_w(component);
  523. return ret;
  524. }
  525. static int hp_supply_event(struct snd_soc_dapm_widget *w,
  526. struct snd_kcontrol *kcontrol, int event)
  527. {
  528. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  529. switch (event) {
  530. case SND_SOC_DAPM_PRE_PMU:
  531. /* Enable the headphone amp */
  532. snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
  533. WM8995_HPOUT1L_ENA_MASK |
  534. WM8995_HPOUT1R_ENA_MASK,
  535. WM8995_HPOUT1L_ENA |
  536. WM8995_HPOUT1R_ENA);
  537. /* Enable the second stage */
  538. snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
  539. WM8995_HPOUT1L_DLY_MASK |
  540. WM8995_HPOUT1R_DLY_MASK,
  541. WM8995_HPOUT1L_DLY |
  542. WM8995_HPOUT1R_DLY);
  543. break;
  544. case SND_SOC_DAPM_PRE_PMD:
  545. snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
  546. WM8995_CP_ENA_MASK, 0);
  547. break;
  548. }
  549. return 0;
  550. }
  551. static void dc_servo_cmd(struct snd_soc_component *component,
  552. unsigned int reg, unsigned int val, unsigned int mask)
  553. {
  554. int timeout = 10;
  555. dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
  556. __func__, reg, val, mask);
  557. snd_soc_component_write(component, reg, val);
  558. while (timeout--) {
  559. msleep(10);
  560. val = snd_soc_component_read(component, WM8995_DC_SERVO_READBACK_0);
  561. if ((val & mask) == mask)
  562. return;
  563. }
  564. dev_err(component->dev, "Timed out waiting for DC Servo\n");
  565. }
  566. static int hp_event(struct snd_soc_dapm_widget *w,
  567. struct snd_kcontrol *kcontrol, int event)
  568. {
  569. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  570. unsigned int reg;
  571. reg = snd_soc_component_read(component, WM8995_ANALOGUE_HP_1);
  572. switch (event) {
  573. case SND_SOC_DAPM_POST_PMU:
  574. snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
  575. WM8995_CP_ENA_MASK, WM8995_CP_ENA);
  576. msleep(5);
  577. snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
  578. WM8995_HPOUT1L_ENA_MASK |
  579. WM8995_HPOUT1R_ENA_MASK,
  580. WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
  581. udelay(20);
  582. reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
  583. snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
  584. snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
  585. WM8995_DCS_ENA_CHAN_1);
  586. dc_servo_cmd(component, WM8995_DC_SERVO_2,
  587. WM8995_DCS_TRIG_STARTUP_0 |
  588. WM8995_DCS_TRIG_STARTUP_1,
  589. WM8995_DCS_TRIG_DAC_WR_0 |
  590. WM8995_DCS_TRIG_DAC_WR_1);
  591. reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
  592. WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
  593. snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
  594. break;
  595. case SND_SOC_DAPM_PRE_PMD:
  596. snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
  597. WM8995_HPOUT1L_OUTP_MASK |
  598. WM8995_HPOUT1R_OUTP_MASK |
  599. WM8995_HPOUT1L_RMV_SHORT_MASK |
  600. WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
  601. snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
  602. WM8995_HPOUT1L_DLY_MASK |
  603. WM8995_HPOUT1R_DLY_MASK, 0);
  604. snd_soc_component_write(component, WM8995_DC_SERVO_1, 0);
  605. snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
  606. WM8995_HPOUT1L_ENA_MASK |
  607. WM8995_HPOUT1R_ENA_MASK,
  608. 0);
  609. break;
  610. }
  611. return 0;
  612. }
  613. static int configure_aif_clock(struct snd_soc_component *component, int aif)
  614. {
  615. struct wm8995_priv *wm8995;
  616. int rate;
  617. int reg1 = 0;
  618. int offset;
  619. wm8995 = snd_soc_component_get_drvdata(component);
  620. if (aif)
  621. offset = 4;
  622. else
  623. offset = 0;
  624. switch (wm8995->sysclk[aif]) {
  625. case WM8995_SYSCLK_MCLK1:
  626. rate = wm8995->mclk[0];
  627. break;
  628. case WM8995_SYSCLK_MCLK2:
  629. reg1 |= 0x8;
  630. rate = wm8995->mclk[1];
  631. break;
  632. case WM8995_SYSCLK_FLL1:
  633. reg1 |= 0x10;
  634. rate = wm8995->fll[0].out;
  635. break;
  636. case WM8995_SYSCLK_FLL2:
  637. reg1 |= 0x18;
  638. rate = wm8995->fll[1].out;
  639. break;
  640. default:
  641. return -EINVAL;
  642. }
  643. if (rate >= 13500000) {
  644. rate /= 2;
  645. reg1 |= WM8995_AIF1CLK_DIV;
  646. dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
  647. aif + 1, rate);
  648. }
  649. wm8995->aifclk[aif] = rate;
  650. snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset,
  651. WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
  652. reg1);
  653. return 0;
  654. }
  655. static int configure_clock(struct snd_soc_component *component)
  656. {
  657. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  658. struct wm8995_priv *wm8995;
  659. int change, new;
  660. wm8995 = snd_soc_component_get_drvdata(component);
  661. /* Bring up the AIF clocks first */
  662. configure_aif_clock(component, 0);
  663. configure_aif_clock(component, 1);
  664. /*
  665. * Then switch CLK_SYS over to the higher of them; a change
  666. * can only happen as a result of a clocking change which can
  667. * only be made outside of DAPM so we can safely redo the
  668. * clocking.
  669. */
  670. /* If they're equal it doesn't matter which is used */
  671. if (wm8995->aifclk[0] == wm8995->aifclk[1])
  672. return 0;
  673. if (wm8995->aifclk[0] < wm8995->aifclk[1])
  674. new = WM8995_SYSCLK_SRC;
  675. else
  676. new = 0;
  677. change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1,
  678. WM8995_SYSCLK_SRC_MASK, new);
  679. if (!change)
  680. return 0;
  681. snd_soc_dapm_sync(dapm);
  682. return 0;
  683. }
  684. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  685. struct snd_kcontrol *kcontrol, int event)
  686. {
  687. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  688. switch (event) {
  689. case SND_SOC_DAPM_PRE_PMU:
  690. return configure_clock(component);
  691. case SND_SOC_DAPM_POST_PMD:
  692. configure_clock(component);
  693. break;
  694. }
  695. return 0;
  696. }
  697. static const char *sidetone_text[] = {
  698. "ADC/DMIC1", "DMIC2",
  699. };
  700. static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text);
  701. static const struct snd_kcontrol_new sidetone1_mux =
  702. SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
  703. static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text);
  704. static const struct snd_kcontrol_new sidetone2_mux =
  705. SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
  706. static const struct snd_kcontrol_new aif1adc1l_mix[] = {
  707. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
  708. 1, 1, 0),
  709. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
  710. 0, 1, 0),
  711. };
  712. static const struct snd_kcontrol_new aif1adc1r_mix[] = {
  713. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  714. 1, 1, 0),
  715. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  716. 0, 1, 0),
  717. };
  718. static const struct snd_kcontrol_new aif1adc2l_mix[] = {
  719. SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
  720. 1, 1, 0),
  721. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
  722. 0, 1, 0),
  723. };
  724. static const struct snd_kcontrol_new aif1adc2r_mix[] = {
  725. SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  726. 1, 1, 0),
  727. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  728. 0, 1, 0),
  729. };
  730. static const struct snd_kcontrol_new dac1l_mix[] = {
  731. WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
  732. 5, 1, 0),
  733. WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
  734. 4, 1, 0),
  735. WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
  736. 2, 1, 0),
  737. WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
  738. 1, 1, 0),
  739. WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
  740. 0, 1, 0),
  741. };
  742. static const struct snd_kcontrol_new dac1r_mix[] = {
  743. WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
  744. 5, 1, 0),
  745. WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
  746. 4, 1, 0),
  747. WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
  748. 2, 1, 0),
  749. WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
  750. 1, 1, 0),
  751. WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
  752. 0, 1, 0),
  753. };
  754. static const struct snd_kcontrol_new aif2dac2l_mix[] = {
  755. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
  756. 5, 1, 0),
  757. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
  758. 4, 1, 0),
  759. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
  760. 2, 1, 0),
  761. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
  762. 1, 1, 0),
  763. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
  764. 0, 1, 0),
  765. };
  766. static const struct snd_kcontrol_new aif2dac2r_mix[] = {
  767. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
  768. 5, 1, 0),
  769. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
  770. 4, 1, 0),
  771. SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
  772. 2, 1, 0),
  773. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
  774. 1, 1, 0),
  775. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
  776. 0, 1, 0),
  777. };
  778. static const struct snd_kcontrol_new in1l_pga =
  779. SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
  780. static const struct snd_kcontrol_new in1r_pga =
  781. SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
  782. static const char *adc_mux_text[] = {
  783. "ADC",
  784. "DMIC",
  785. };
  786. static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
  787. static const struct snd_kcontrol_new adcl_mux =
  788. SOC_DAPM_ENUM("ADCL Mux", adc_enum);
  789. static const struct snd_kcontrol_new adcr_mux =
  790. SOC_DAPM_ENUM("ADCR Mux", adc_enum);
  791. static const char *spk_src_text[] = {
  792. "DAC1L", "DAC1R", "DAC2L", "DAC2R"
  793. };
  794. static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
  795. 0, spk_src_text);
  796. static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
  797. 0, spk_src_text);
  798. static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
  799. 0, spk_src_text);
  800. static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
  801. 0, spk_src_text);
  802. static const struct snd_kcontrol_new spk1l_mux =
  803. SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
  804. static const struct snd_kcontrol_new spk1r_mux =
  805. SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
  806. static const struct snd_kcontrol_new spk2l_mux =
  807. SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
  808. static const struct snd_kcontrol_new spk2r_mux =
  809. SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
  810. static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
  811. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  812. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  813. SND_SOC_DAPM_INPUT("IN1L"),
  814. SND_SOC_DAPM_INPUT("IN1R"),
  815. SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
  816. &in1l_pga, 1),
  817. SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
  818. &in1r_pga, 1),
  819. SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
  820. NULL, 0),
  821. SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
  822. NULL, 0),
  823. SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
  824. SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
  825. SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
  826. SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
  827. SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
  828. SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
  829. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  830. SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
  831. WM8995_POWER_MANAGEMENT_3, 9, 0),
  832. SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
  833. WM8995_POWER_MANAGEMENT_3, 8, 0),
  834. SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
  835. SND_SOC_NOPM, 0, 0),
  836. SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
  837. 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
  838. SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
  839. 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
  840. SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
  841. SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
  842. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
  843. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
  844. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
  845. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
  846. SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
  847. SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
  848. SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
  849. aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
  850. SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
  851. aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
  852. SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
  853. aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
  854. SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
  855. aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
  856. SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
  857. 9, 0),
  858. SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
  859. 8, 0),
  860. SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
  861. 0, 0),
  862. SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
  863. 11, 0),
  864. SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
  865. 10, 0),
  866. SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  867. aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
  868. SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  869. aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
  870. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
  871. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
  872. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
  873. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
  874. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
  875. ARRAY_SIZE(dac1l_mix)),
  876. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
  877. ARRAY_SIZE(dac1r_mix)),
  878. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
  879. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
  880. SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  881. hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  882. SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
  883. hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  884. SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
  885. 4, 0, &spk1l_mux),
  886. SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
  887. 4, 0, &spk1r_mux),
  888. SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
  889. 4, 0, &spk2l_mux),
  890. SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
  891. 4, 0, &spk2r_mux),
  892. SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
  893. SND_SOC_DAPM_OUTPUT("HP1L"),
  894. SND_SOC_DAPM_OUTPUT("HP1R"),
  895. SND_SOC_DAPM_OUTPUT("SPK1L"),
  896. SND_SOC_DAPM_OUTPUT("SPK1R"),
  897. SND_SOC_DAPM_OUTPUT("SPK2L"),
  898. SND_SOC_DAPM_OUTPUT("SPK2R")
  899. };
  900. static const struct snd_soc_dapm_route wm8995_intercon[] = {
  901. { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
  902. { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
  903. { "DSP1CLK", NULL, "CLK_SYS" },
  904. { "DSP2CLK", NULL, "CLK_SYS" },
  905. { "SYSDSPCLK", NULL, "CLK_SYS" },
  906. { "AIF1ADC1L", NULL, "AIF1CLK" },
  907. { "AIF1ADC1L", NULL, "DSP1CLK" },
  908. { "AIF1ADC1R", NULL, "AIF1CLK" },
  909. { "AIF1ADC1R", NULL, "DSP1CLK" },
  910. { "AIF1ADC1R", NULL, "SYSDSPCLK" },
  911. { "AIF1ADC2L", NULL, "AIF1CLK" },
  912. { "AIF1ADC2L", NULL, "DSP1CLK" },
  913. { "AIF1ADC2R", NULL, "AIF1CLK" },
  914. { "AIF1ADC2R", NULL, "DSP1CLK" },
  915. { "AIF1ADC2R", NULL, "SYSDSPCLK" },
  916. { "DMIC1L", NULL, "DMIC1DAT" },
  917. { "DMIC1L", NULL, "CLK_SYS" },
  918. { "DMIC1R", NULL, "DMIC1DAT" },
  919. { "DMIC1R", NULL, "CLK_SYS" },
  920. { "DMIC2L", NULL, "DMIC2DAT" },
  921. { "DMIC2L", NULL, "CLK_SYS" },
  922. { "DMIC2R", NULL, "DMIC2DAT" },
  923. { "DMIC2R", NULL, "CLK_SYS" },
  924. { "ADCL", NULL, "AIF1CLK" },
  925. { "ADCL", NULL, "DSP1CLK" },
  926. { "ADCL", NULL, "SYSDSPCLK" },
  927. { "ADCR", NULL, "AIF1CLK" },
  928. { "ADCR", NULL, "DSP1CLK" },
  929. { "ADCR", NULL, "SYSDSPCLK" },
  930. { "IN1L PGA", "IN1L Switch", "IN1L" },
  931. { "IN1R PGA", "IN1R Switch", "IN1R" },
  932. { "IN1L PGA", NULL, "LDO2" },
  933. { "IN1R PGA", NULL, "LDO2" },
  934. { "ADCL", NULL, "IN1L PGA" },
  935. { "ADCR", NULL, "IN1R PGA" },
  936. { "ADCL Mux", "ADC", "ADCL" },
  937. { "ADCL Mux", "DMIC", "DMIC1L" },
  938. { "ADCR Mux", "ADC", "ADCR" },
  939. { "ADCR Mux", "DMIC", "DMIC1R" },
  940. /* AIF1 outputs */
  941. { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
  942. { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
  943. { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
  944. { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
  945. { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
  946. { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
  947. { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
  948. { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
  949. /* Sidetone */
  950. { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
  951. { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
  952. { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
  953. { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
  954. { "AIF1DAC1L", NULL, "AIF1CLK" },
  955. { "AIF1DAC1L", NULL, "DSP1CLK" },
  956. { "AIF1DAC1R", NULL, "AIF1CLK" },
  957. { "AIF1DAC1R", NULL, "DSP1CLK" },
  958. { "AIF1DAC1R", NULL, "SYSDSPCLK" },
  959. { "AIF1DAC2L", NULL, "AIF1CLK" },
  960. { "AIF1DAC2L", NULL, "DSP1CLK" },
  961. { "AIF1DAC2R", NULL, "AIF1CLK" },
  962. { "AIF1DAC2R", NULL, "DSP1CLK" },
  963. { "AIF1DAC2R", NULL, "SYSDSPCLK" },
  964. { "DAC1L", NULL, "AIF1CLK" },
  965. { "DAC1L", NULL, "DSP1CLK" },
  966. { "DAC1L", NULL, "SYSDSPCLK" },
  967. { "DAC1R", NULL, "AIF1CLK" },
  968. { "DAC1R", NULL, "DSP1CLK" },
  969. { "DAC1R", NULL, "SYSDSPCLK" },
  970. { "AIF1DAC1L", NULL, "AIF1DACDAT" },
  971. { "AIF1DAC1R", NULL, "AIF1DACDAT" },
  972. { "AIF1DAC2L", NULL, "AIF1DACDAT" },
  973. { "AIF1DAC2R", NULL, "AIF1DACDAT" },
  974. /* DAC1 inputs */
  975. { "DAC1L", NULL, "DAC1L Mixer" },
  976. { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  977. { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  978. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  979. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  980. { "DAC1R", NULL, "DAC1R Mixer" },
  981. { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  982. { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  983. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  984. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  985. /* DAC2/AIF2 outputs */
  986. { "DAC2L", NULL, "AIF2DAC2L Mixer" },
  987. { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  988. { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  989. { "DAC2R", NULL, "AIF2DAC2R Mixer" },
  990. { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  991. { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  992. /* Output stages */
  993. { "Headphone PGA", NULL, "DAC1L" },
  994. { "Headphone PGA", NULL, "DAC1R" },
  995. { "Headphone PGA", NULL, "DAC2L" },
  996. { "Headphone PGA", NULL, "DAC2R" },
  997. { "Headphone PGA", NULL, "Headphone Supply" },
  998. { "Headphone PGA", NULL, "CLK_SYS" },
  999. { "Headphone PGA", NULL, "LDO2" },
  1000. { "HP1L", NULL, "Headphone PGA" },
  1001. { "HP1R", NULL, "Headphone PGA" },
  1002. { "SPK1L Driver", "DAC1L", "DAC1L" },
  1003. { "SPK1L Driver", "DAC1R", "DAC1R" },
  1004. { "SPK1L Driver", "DAC2L", "DAC2L" },
  1005. { "SPK1L Driver", "DAC2R", "DAC2R" },
  1006. { "SPK1L Driver", NULL, "CLK_SYS" },
  1007. { "SPK1R Driver", "DAC1L", "DAC1L" },
  1008. { "SPK1R Driver", "DAC1R", "DAC1R" },
  1009. { "SPK1R Driver", "DAC2L", "DAC2L" },
  1010. { "SPK1R Driver", "DAC2R", "DAC2R" },
  1011. { "SPK1R Driver", NULL, "CLK_SYS" },
  1012. { "SPK2L Driver", "DAC1L", "DAC1L" },
  1013. { "SPK2L Driver", "DAC1R", "DAC1R" },
  1014. { "SPK2L Driver", "DAC2L", "DAC2L" },
  1015. { "SPK2L Driver", "DAC2R", "DAC2R" },
  1016. { "SPK2L Driver", NULL, "CLK_SYS" },
  1017. { "SPK2R Driver", "DAC1L", "DAC1L" },
  1018. { "SPK2R Driver", "DAC1R", "DAC1R" },
  1019. { "SPK2R Driver", "DAC2L", "DAC2L" },
  1020. { "SPK2R Driver", "DAC2R", "DAC2R" },
  1021. { "SPK2R Driver", NULL, "CLK_SYS" },
  1022. { "SPK1L", NULL, "SPK1L Driver" },
  1023. { "SPK1R", NULL, "SPK1R Driver" },
  1024. { "SPK2L", NULL, "SPK2L Driver" },
  1025. { "SPK2R", NULL, "SPK2R Driver" }
  1026. };
  1027. static bool wm8995_readable(struct device *dev, unsigned int reg)
  1028. {
  1029. switch (reg) {
  1030. case WM8995_SOFTWARE_RESET:
  1031. case WM8995_POWER_MANAGEMENT_1:
  1032. case WM8995_POWER_MANAGEMENT_2:
  1033. case WM8995_POWER_MANAGEMENT_3:
  1034. case WM8995_POWER_MANAGEMENT_4:
  1035. case WM8995_POWER_MANAGEMENT_5:
  1036. case WM8995_LEFT_LINE_INPUT_1_VOLUME:
  1037. case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
  1038. case WM8995_LEFT_LINE_INPUT_CONTROL:
  1039. case WM8995_DAC1_LEFT_VOLUME:
  1040. case WM8995_DAC1_RIGHT_VOLUME:
  1041. case WM8995_DAC2_LEFT_VOLUME:
  1042. case WM8995_DAC2_RIGHT_VOLUME:
  1043. case WM8995_OUTPUT_VOLUME_ZC_1:
  1044. case WM8995_MICBIAS_1:
  1045. case WM8995_MICBIAS_2:
  1046. case WM8995_LDO_1:
  1047. case WM8995_LDO_2:
  1048. case WM8995_ACCESSORY_DETECT_MODE1:
  1049. case WM8995_ACCESSORY_DETECT_MODE2:
  1050. case WM8995_HEADPHONE_DETECT1:
  1051. case WM8995_HEADPHONE_DETECT2:
  1052. case WM8995_MIC_DETECT_1:
  1053. case WM8995_MIC_DETECT_2:
  1054. case WM8995_CHARGE_PUMP_1:
  1055. case WM8995_CLASS_W_1:
  1056. case WM8995_DC_SERVO_1:
  1057. case WM8995_DC_SERVO_2:
  1058. case WM8995_DC_SERVO_3:
  1059. case WM8995_DC_SERVO_5:
  1060. case WM8995_DC_SERVO_6:
  1061. case WM8995_DC_SERVO_7:
  1062. case WM8995_DC_SERVO_READBACK_0:
  1063. case WM8995_ANALOGUE_HP_1:
  1064. case WM8995_ANALOGUE_HP_2:
  1065. case WM8995_CHIP_REVISION:
  1066. case WM8995_CONTROL_INTERFACE_1:
  1067. case WM8995_CONTROL_INTERFACE_2:
  1068. case WM8995_WRITE_SEQUENCER_CTRL_1:
  1069. case WM8995_WRITE_SEQUENCER_CTRL_2:
  1070. case WM8995_AIF1_CLOCKING_1:
  1071. case WM8995_AIF1_CLOCKING_2:
  1072. case WM8995_AIF2_CLOCKING_1:
  1073. case WM8995_AIF2_CLOCKING_2:
  1074. case WM8995_CLOCKING_1:
  1075. case WM8995_CLOCKING_2:
  1076. case WM8995_AIF1_RATE:
  1077. case WM8995_AIF2_RATE:
  1078. case WM8995_RATE_STATUS:
  1079. case WM8995_FLL1_CONTROL_1:
  1080. case WM8995_FLL1_CONTROL_2:
  1081. case WM8995_FLL1_CONTROL_3:
  1082. case WM8995_FLL1_CONTROL_4:
  1083. case WM8995_FLL1_CONTROL_5:
  1084. case WM8995_FLL2_CONTROL_1:
  1085. case WM8995_FLL2_CONTROL_2:
  1086. case WM8995_FLL2_CONTROL_3:
  1087. case WM8995_FLL2_CONTROL_4:
  1088. case WM8995_FLL2_CONTROL_5:
  1089. case WM8995_AIF1_CONTROL_1:
  1090. case WM8995_AIF1_CONTROL_2:
  1091. case WM8995_AIF1_MASTER_SLAVE:
  1092. case WM8995_AIF1_BCLK:
  1093. case WM8995_AIF1ADC_LRCLK:
  1094. case WM8995_AIF1DAC_LRCLK:
  1095. case WM8995_AIF1DAC_DATA:
  1096. case WM8995_AIF1ADC_DATA:
  1097. case WM8995_AIF2_CONTROL_1:
  1098. case WM8995_AIF2_CONTROL_2:
  1099. case WM8995_AIF2_MASTER_SLAVE:
  1100. case WM8995_AIF2_BCLK:
  1101. case WM8995_AIF2ADC_LRCLK:
  1102. case WM8995_AIF2DAC_LRCLK:
  1103. case WM8995_AIF2DAC_DATA:
  1104. case WM8995_AIF2ADC_DATA:
  1105. case WM8995_AIF1_ADC1_LEFT_VOLUME:
  1106. case WM8995_AIF1_ADC1_RIGHT_VOLUME:
  1107. case WM8995_AIF1_DAC1_LEFT_VOLUME:
  1108. case WM8995_AIF1_DAC1_RIGHT_VOLUME:
  1109. case WM8995_AIF1_ADC2_LEFT_VOLUME:
  1110. case WM8995_AIF1_ADC2_RIGHT_VOLUME:
  1111. case WM8995_AIF1_DAC2_LEFT_VOLUME:
  1112. case WM8995_AIF1_DAC2_RIGHT_VOLUME:
  1113. case WM8995_AIF1_ADC1_FILTERS:
  1114. case WM8995_AIF1_ADC2_FILTERS:
  1115. case WM8995_AIF1_DAC1_FILTERS_1:
  1116. case WM8995_AIF1_DAC1_FILTERS_2:
  1117. case WM8995_AIF1_DAC2_FILTERS_1:
  1118. case WM8995_AIF1_DAC2_FILTERS_2:
  1119. case WM8995_AIF1_DRC1_1:
  1120. case WM8995_AIF1_DRC1_2:
  1121. case WM8995_AIF1_DRC1_3:
  1122. case WM8995_AIF1_DRC1_4:
  1123. case WM8995_AIF1_DRC1_5:
  1124. case WM8995_AIF1_DRC2_1:
  1125. case WM8995_AIF1_DRC2_2:
  1126. case WM8995_AIF1_DRC2_3:
  1127. case WM8995_AIF1_DRC2_4:
  1128. case WM8995_AIF1_DRC2_5:
  1129. case WM8995_AIF1_DAC1_EQ_GAINS_1:
  1130. case WM8995_AIF1_DAC1_EQ_GAINS_2:
  1131. case WM8995_AIF1_DAC1_EQ_BAND_1_A:
  1132. case WM8995_AIF1_DAC1_EQ_BAND_1_B:
  1133. case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
  1134. case WM8995_AIF1_DAC1_EQ_BAND_2_A:
  1135. case WM8995_AIF1_DAC1_EQ_BAND_2_B:
  1136. case WM8995_AIF1_DAC1_EQ_BAND_2_C:
  1137. case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
  1138. case WM8995_AIF1_DAC1_EQ_BAND_3_A:
  1139. case WM8995_AIF1_DAC1_EQ_BAND_3_B:
  1140. case WM8995_AIF1_DAC1_EQ_BAND_3_C:
  1141. case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
  1142. case WM8995_AIF1_DAC1_EQ_BAND_4_A:
  1143. case WM8995_AIF1_DAC1_EQ_BAND_4_B:
  1144. case WM8995_AIF1_DAC1_EQ_BAND_4_C:
  1145. case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
  1146. case WM8995_AIF1_DAC1_EQ_BAND_5_A:
  1147. case WM8995_AIF1_DAC1_EQ_BAND_5_B:
  1148. case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
  1149. case WM8995_AIF1_DAC2_EQ_GAINS_1:
  1150. case WM8995_AIF1_DAC2_EQ_GAINS_2:
  1151. case WM8995_AIF1_DAC2_EQ_BAND_1_A:
  1152. case WM8995_AIF1_DAC2_EQ_BAND_1_B:
  1153. case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
  1154. case WM8995_AIF1_DAC2_EQ_BAND_2_A:
  1155. case WM8995_AIF1_DAC2_EQ_BAND_2_B:
  1156. case WM8995_AIF1_DAC2_EQ_BAND_2_C:
  1157. case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
  1158. case WM8995_AIF1_DAC2_EQ_BAND_3_A:
  1159. case WM8995_AIF1_DAC2_EQ_BAND_3_B:
  1160. case WM8995_AIF1_DAC2_EQ_BAND_3_C:
  1161. case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
  1162. case WM8995_AIF1_DAC2_EQ_BAND_4_A:
  1163. case WM8995_AIF1_DAC2_EQ_BAND_4_B:
  1164. case WM8995_AIF1_DAC2_EQ_BAND_4_C:
  1165. case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
  1166. case WM8995_AIF1_DAC2_EQ_BAND_5_A:
  1167. case WM8995_AIF1_DAC2_EQ_BAND_5_B:
  1168. case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
  1169. case WM8995_AIF2_ADC_LEFT_VOLUME:
  1170. case WM8995_AIF2_ADC_RIGHT_VOLUME:
  1171. case WM8995_AIF2_DAC_LEFT_VOLUME:
  1172. case WM8995_AIF2_DAC_RIGHT_VOLUME:
  1173. case WM8995_AIF2_ADC_FILTERS:
  1174. case WM8995_AIF2_DAC_FILTERS_1:
  1175. case WM8995_AIF2_DAC_FILTERS_2:
  1176. case WM8995_AIF2_DRC_1:
  1177. case WM8995_AIF2_DRC_2:
  1178. case WM8995_AIF2_DRC_3:
  1179. case WM8995_AIF2_DRC_4:
  1180. case WM8995_AIF2_DRC_5:
  1181. case WM8995_AIF2_EQ_GAINS_1:
  1182. case WM8995_AIF2_EQ_GAINS_2:
  1183. case WM8995_AIF2_EQ_BAND_1_A:
  1184. case WM8995_AIF2_EQ_BAND_1_B:
  1185. case WM8995_AIF2_EQ_BAND_1_PG:
  1186. case WM8995_AIF2_EQ_BAND_2_A:
  1187. case WM8995_AIF2_EQ_BAND_2_B:
  1188. case WM8995_AIF2_EQ_BAND_2_C:
  1189. case WM8995_AIF2_EQ_BAND_2_PG:
  1190. case WM8995_AIF2_EQ_BAND_3_A:
  1191. case WM8995_AIF2_EQ_BAND_3_B:
  1192. case WM8995_AIF2_EQ_BAND_3_C:
  1193. case WM8995_AIF2_EQ_BAND_3_PG:
  1194. case WM8995_AIF2_EQ_BAND_4_A:
  1195. case WM8995_AIF2_EQ_BAND_4_B:
  1196. case WM8995_AIF2_EQ_BAND_4_C:
  1197. case WM8995_AIF2_EQ_BAND_4_PG:
  1198. case WM8995_AIF2_EQ_BAND_5_A:
  1199. case WM8995_AIF2_EQ_BAND_5_B:
  1200. case WM8995_AIF2_EQ_BAND_5_PG:
  1201. case WM8995_DAC1_MIXER_VOLUMES:
  1202. case WM8995_DAC1_LEFT_MIXER_ROUTING:
  1203. case WM8995_DAC1_RIGHT_MIXER_ROUTING:
  1204. case WM8995_DAC2_MIXER_VOLUMES:
  1205. case WM8995_DAC2_LEFT_MIXER_ROUTING:
  1206. case WM8995_DAC2_RIGHT_MIXER_ROUTING:
  1207. case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
  1208. case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
  1209. case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
  1210. case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
  1211. case WM8995_DAC_SOFTMUTE:
  1212. case WM8995_OVERSAMPLING:
  1213. case WM8995_SIDETONE:
  1214. case WM8995_GPIO_1:
  1215. case WM8995_GPIO_2:
  1216. case WM8995_GPIO_3:
  1217. case WM8995_GPIO_4:
  1218. case WM8995_GPIO_5:
  1219. case WM8995_GPIO_6:
  1220. case WM8995_GPIO_7:
  1221. case WM8995_GPIO_8:
  1222. case WM8995_GPIO_9:
  1223. case WM8995_GPIO_10:
  1224. case WM8995_GPIO_11:
  1225. case WM8995_GPIO_12:
  1226. case WM8995_GPIO_13:
  1227. case WM8995_GPIO_14:
  1228. case WM8995_PULL_CONTROL_1:
  1229. case WM8995_PULL_CONTROL_2:
  1230. case WM8995_INTERRUPT_STATUS_1:
  1231. case WM8995_INTERRUPT_STATUS_2:
  1232. case WM8995_INTERRUPT_RAW_STATUS_2:
  1233. case WM8995_INTERRUPT_STATUS_1_MASK:
  1234. case WM8995_INTERRUPT_STATUS_2_MASK:
  1235. case WM8995_INTERRUPT_CONTROL:
  1236. case WM8995_LEFT_PDM_SPEAKER_1:
  1237. case WM8995_RIGHT_PDM_SPEAKER_1:
  1238. case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
  1239. case WM8995_LEFT_PDM_SPEAKER_2:
  1240. case WM8995_RIGHT_PDM_SPEAKER_2:
  1241. case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
  1242. return true;
  1243. default:
  1244. return false;
  1245. }
  1246. }
  1247. static bool wm8995_volatile(struct device *dev, unsigned int reg)
  1248. {
  1249. switch (reg) {
  1250. case WM8995_SOFTWARE_RESET:
  1251. case WM8995_DC_SERVO_READBACK_0:
  1252. case WM8995_INTERRUPT_STATUS_1:
  1253. case WM8995_INTERRUPT_STATUS_2:
  1254. case WM8995_INTERRUPT_CONTROL:
  1255. case WM8995_ACCESSORY_DETECT_MODE1:
  1256. case WM8995_ACCESSORY_DETECT_MODE2:
  1257. case WM8995_HEADPHONE_DETECT1:
  1258. case WM8995_HEADPHONE_DETECT2:
  1259. case WM8995_RATE_STATUS:
  1260. return true;
  1261. default:
  1262. return false;
  1263. }
  1264. }
  1265. static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute, int direction)
  1266. {
  1267. struct snd_soc_component *component = dai->component;
  1268. int mute_reg;
  1269. switch (dai->id) {
  1270. case 0:
  1271. mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
  1272. break;
  1273. case 1:
  1274. mute_reg = WM8995_AIF2_DAC_FILTERS_1;
  1275. break;
  1276. default:
  1277. return -EINVAL;
  1278. }
  1279. snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
  1280. !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
  1281. return 0;
  1282. }
  1283. static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1284. {
  1285. struct snd_soc_component *component;
  1286. int master;
  1287. int aif;
  1288. component = dai->component;
  1289. master = 0;
  1290. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1291. case SND_SOC_DAIFMT_CBS_CFS:
  1292. break;
  1293. case SND_SOC_DAIFMT_CBM_CFM:
  1294. master = WM8995_AIF1_MSTR;
  1295. break;
  1296. default:
  1297. dev_err(dai->dev, "Unknown master/slave configuration\n");
  1298. return -EINVAL;
  1299. }
  1300. aif = 0;
  1301. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1302. case SND_SOC_DAIFMT_DSP_B:
  1303. aif |= WM8995_AIF1_LRCLK_INV;
  1304. fallthrough;
  1305. case SND_SOC_DAIFMT_DSP_A:
  1306. aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
  1307. break;
  1308. case SND_SOC_DAIFMT_I2S:
  1309. aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
  1310. break;
  1311. case SND_SOC_DAIFMT_RIGHT_J:
  1312. break;
  1313. case SND_SOC_DAIFMT_LEFT_J:
  1314. aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
  1315. break;
  1316. default:
  1317. dev_err(dai->dev, "Unknown dai format\n");
  1318. return -EINVAL;
  1319. }
  1320. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1321. case SND_SOC_DAIFMT_DSP_A:
  1322. case SND_SOC_DAIFMT_DSP_B:
  1323. /* frame inversion not valid for DSP modes */
  1324. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1325. case SND_SOC_DAIFMT_NB_NF:
  1326. break;
  1327. case SND_SOC_DAIFMT_IB_NF:
  1328. aif |= WM8995_AIF1_BCLK_INV;
  1329. break;
  1330. default:
  1331. return -EINVAL;
  1332. }
  1333. break;
  1334. case SND_SOC_DAIFMT_I2S:
  1335. case SND_SOC_DAIFMT_RIGHT_J:
  1336. case SND_SOC_DAIFMT_LEFT_J:
  1337. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1338. case SND_SOC_DAIFMT_NB_NF:
  1339. break;
  1340. case SND_SOC_DAIFMT_IB_IF:
  1341. aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
  1342. break;
  1343. case SND_SOC_DAIFMT_IB_NF:
  1344. aif |= WM8995_AIF1_BCLK_INV;
  1345. break;
  1346. case SND_SOC_DAIFMT_NB_IF:
  1347. aif |= WM8995_AIF1_LRCLK_INV;
  1348. break;
  1349. default:
  1350. return -EINVAL;
  1351. }
  1352. break;
  1353. default:
  1354. return -EINVAL;
  1355. }
  1356. snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1,
  1357. WM8995_AIF1_BCLK_INV_MASK |
  1358. WM8995_AIF1_LRCLK_INV_MASK |
  1359. WM8995_AIF1_FMT_MASK, aif);
  1360. snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE,
  1361. WM8995_AIF1_MSTR_MASK, master);
  1362. return 0;
  1363. }
  1364. static const int srs[] = {
  1365. 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
  1366. 48000, 88200, 96000
  1367. };
  1368. static const int fs_ratios[] = {
  1369. -1 /* reserved */,
  1370. 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
  1371. };
  1372. static const int bclk_divs[] = {
  1373. 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
  1374. };
  1375. static int wm8995_hw_params(struct snd_pcm_substream *substream,
  1376. struct snd_pcm_hw_params *params,
  1377. struct snd_soc_dai *dai)
  1378. {
  1379. struct snd_soc_component *component;
  1380. struct wm8995_priv *wm8995;
  1381. int aif1_reg;
  1382. int bclk_reg;
  1383. int lrclk_reg;
  1384. int rate_reg;
  1385. int bclk_rate;
  1386. int aif1;
  1387. int lrclk, bclk;
  1388. int i, rate_val, best, best_val, cur_val;
  1389. component = dai->component;
  1390. wm8995 = snd_soc_component_get_drvdata(component);
  1391. switch (dai->id) {
  1392. case 0:
  1393. aif1_reg = WM8995_AIF1_CONTROL_1;
  1394. bclk_reg = WM8995_AIF1_BCLK;
  1395. rate_reg = WM8995_AIF1_RATE;
  1396. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
  1397. wm8995->lrclk_shared[0] */) {
  1398. lrclk_reg = WM8995_AIF1DAC_LRCLK;
  1399. } else {
  1400. lrclk_reg = WM8995_AIF1ADC_LRCLK;
  1401. dev_dbg(component->dev, "AIF1 using split LRCLK\n");
  1402. }
  1403. break;
  1404. case 1:
  1405. aif1_reg = WM8995_AIF2_CONTROL_1;
  1406. bclk_reg = WM8995_AIF2_BCLK;
  1407. rate_reg = WM8995_AIF2_RATE;
  1408. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
  1409. wm8995->lrclk_shared[1] */) {
  1410. lrclk_reg = WM8995_AIF2DAC_LRCLK;
  1411. } else {
  1412. lrclk_reg = WM8995_AIF2ADC_LRCLK;
  1413. dev_dbg(component->dev, "AIF2 using split LRCLK\n");
  1414. }
  1415. break;
  1416. default:
  1417. return -EINVAL;
  1418. }
  1419. bclk_rate = snd_soc_params_to_bclk(params);
  1420. if (bclk_rate < 0)
  1421. return bclk_rate;
  1422. aif1 = 0;
  1423. switch (params_width(params)) {
  1424. case 16:
  1425. break;
  1426. case 20:
  1427. aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
  1428. break;
  1429. case 24:
  1430. aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
  1431. break;
  1432. case 32:
  1433. aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
  1434. break;
  1435. default:
  1436. dev_err(dai->dev, "Unsupported word length %u\n",
  1437. params_width(params));
  1438. return -EINVAL;
  1439. }
  1440. /* try to find a suitable sample rate */
  1441. for (i = 0; i < ARRAY_SIZE(srs); ++i)
  1442. if (srs[i] == params_rate(params))
  1443. break;
  1444. if (i == ARRAY_SIZE(srs)) {
  1445. dev_err(dai->dev, "Sample rate %d is not supported\n",
  1446. params_rate(params));
  1447. return -EINVAL;
  1448. }
  1449. rate_val = i << WM8995_AIF1_SR_SHIFT;
  1450. dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
  1451. dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
  1452. dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
  1453. /* AIFCLK/fs ratio; look for a close match in either direction */
  1454. best = 1;
  1455. best_val = abs((fs_ratios[1] * params_rate(params))
  1456. - wm8995->aifclk[dai->id]);
  1457. for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
  1458. cur_val = abs((fs_ratios[i] * params_rate(params))
  1459. - wm8995->aifclk[dai->id]);
  1460. if (cur_val >= best_val)
  1461. continue;
  1462. best = i;
  1463. best_val = cur_val;
  1464. }
  1465. rate_val |= best;
  1466. dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
  1467. dai->id + 1, fs_ratios[best]);
  1468. /*
  1469. * We may not get quite the right frequency if using
  1470. * approximate clocks so look for the closest match that is
  1471. * higher than the target (we need to ensure that there enough
  1472. * BCLKs to clock out the samples).
  1473. */
  1474. best = 0;
  1475. bclk = 0;
  1476. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1477. cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
  1478. if (cur_val < 0) /* BCLK table is sorted */
  1479. break;
  1480. best = i;
  1481. }
  1482. bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
  1483. bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
  1484. dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  1485. bclk_divs[best], bclk_rate);
  1486. lrclk = bclk_rate / params_rate(params);
  1487. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  1488. lrclk, bclk_rate / lrclk);
  1489. snd_soc_component_update_bits(component, aif1_reg,
  1490. WM8995_AIF1_WL_MASK, aif1);
  1491. snd_soc_component_update_bits(component, bclk_reg,
  1492. WM8995_AIF1_BCLK_DIV_MASK, bclk);
  1493. snd_soc_component_update_bits(component, lrclk_reg,
  1494. WM8995_AIF1DAC_RATE_MASK, lrclk);
  1495. snd_soc_component_update_bits(component, rate_reg,
  1496. WM8995_AIF1_SR_MASK |
  1497. WM8995_AIF1CLK_RATE_MASK, rate_val);
  1498. return 0;
  1499. }
  1500. static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
  1501. {
  1502. struct snd_soc_component *component = codec_dai->component;
  1503. int reg, val, mask;
  1504. switch (codec_dai->id) {
  1505. case 0:
  1506. reg = WM8995_AIF1_MASTER_SLAVE;
  1507. mask = WM8995_AIF1_TRI;
  1508. break;
  1509. case 1:
  1510. reg = WM8995_AIF2_MASTER_SLAVE;
  1511. mask = WM8995_AIF2_TRI;
  1512. break;
  1513. case 2:
  1514. reg = WM8995_POWER_MANAGEMENT_5;
  1515. mask = WM8995_AIF3_TRI;
  1516. break;
  1517. default:
  1518. return -EINVAL;
  1519. }
  1520. if (tristate)
  1521. val = mask;
  1522. else
  1523. val = 0;
  1524. return snd_soc_component_update_bits(component, reg, mask, val);
  1525. }
  1526. /* The size in bits of the FLL divide multiplied by 10
  1527. * to allow rounding later */
  1528. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1529. struct fll_div {
  1530. u16 outdiv;
  1531. u16 n;
  1532. u16 k;
  1533. u16 clk_ref_div;
  1534. u16 fll_fratio;
  1535. };
  1536. static int wm8995_get_fll_config(struct fll_div *fll,
  1537. int freq_in, int freq_out)
  1538. {
  1539. u64 Kpart;
  1540. unsigned int K, Ndiv, Nmod;
  1541. pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
  1542. /* Scale the input frequency down to <= 13.5MHz */
  1543. fll->clk_ref_div = 0;
  1544. while (freq_in > 13500000) {
  1545. fll->clk_ref_div++;
  1546. freq_in /= 2;
  1547. if (fll->clk_ref_div > 3)
  1548. return -EINVAL;
  1549. }
  1550. pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
  1551. /* Scale the output to give 90MHz<=Fvco<=100MHz */
  1552. fll->outdiv = 3;
  1553. while (freq_out * (fll->outdiv + 1) < 90000000) {
  1554. fll->outdiv++;
  1555. if (fll->outdiv > 63)
  1556. return -EINVAL;
  1557. }
  1558. freq_out *= fll->outdiv + 1;
  1559. pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
  1560. if (freq_in > 1000000) {
  1561. fll->fll_fratio = 0;
  1562. } else if (freq_in > 256000) {
  1563. fll->fll_fratio = 1;
  1564. freq_in *= 2;
  1565. } else if (freq_in > 128000) {
  1566. fll->fll_fratio = 2;
  1567. freq_in *= 4;
  1568. } else if (freq_in > 64000) {
  1569. fll->fll_fratio = 3;
  1570. freq_in *= 8;
  1571. } else {
  1572. fll->fll_fratio = 4;
  1573. freq_in *= 16;
  1574. }
  1575. pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
  1576. /* Now, calculate N.K */
  1577. Ndiv = freq_out / freq_in;
  1578. fll->n = Ndiv;
  1579. Nmod = freq_out % freq_in;
  1580. pr_debug("Nmod=%d\n", Nmod);
  1581. /* Calculate fractional part - scale up so we can round. */
  1582. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1583. do_div(Kpart, freq_in);
  1584. K = Kpart & 0xFFFFFFFF;
  1585. if ((K % 10) >= 5)
  1586. K += 5;
  1587. /* Move down to proper range now rounding is done */
  1588. fll->k = K / 10;
  1589. pr_debug("N=%x K=%x\n", fll->n, fll->k);
  1590. return 0;
  1591. }
  1592. static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
  1593. int src, unsigned int freq_in,
  1594. unsigned int freq_out)
  1595. {
  1596. struct snd_soc_component *component;
  1597. struct wm8995_priv *wm8995;
  1598. int reg_offset, ret;
  1599. struct fll_div fll;
  1600. u16 reg, aif1, aif2;
  1601. component = dai->component;
  1602. wm8995 = snd_soc_component_get_drvdata(component);
  1603. aif1 = snd_soc_component_read(component, WM8995_AIF1_CLOCKING_1)
  1604. & WM8995_AIF1CLK_ENA;
  1605. aif2 = snd_soc_component_read(component, WM8995_AIF2_CLOCKING_1)
  1606. & WM8995_AIF2CLK_ENA;
  1607. switch (id) {
  1608. case WM8995_FLL1:
  1609. reg_offset = 0;
  1610. id = 0;
  1611. break;
  1612. case WM8995_FLL2:
  1613. reg_offset = 0x20;
  1614. id = 1;
  1615. break;
  1616. default:
  1617. return -EINVAL;
  1618. }
  1619. switch (src) {
  1620. case 0:
  1621. /* Allow no source specification when stopping */
  1622. if (freq_out)
  1623. return -EINVAL;
  1624. break;
  1625. case WM8995_FLL_SRC_MCLK1:
  1626. case WM8995_FLL_SRC_MCLK2:
  1627. case WM8995_FLL_SRC_LRCLK:
  1628. case WM8995_FLL_SRC_BCLK:
  1629. break;
  1630. default:
  1631. return -EINVAL;
  1632. }
  1633. /* Are we changing anything? */
  1634. if (wm8995->fll[id].src == src &&
  1635. wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
  1636. return 0;
  1637. /* If we're stopping the FLL redo the old config - no
  1638. * registers will actually be written but we avoid GCC flow
  1639. * analysis bugs spewing warnings.
  1640. */
  1641. if (freq_out)
  1642. ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
  1643. else
  1644. ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
  1645. wm8995->fll[id].out);
  1646. if (ret < 0)
  1647. return ret;
  1648. /* Gate the AIF clocks while we reclock */
  1649. snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
  1650. WM8995_AIF1CLK_ENA_MASK, 0);
  1651. snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
  1652. WM8995_AIF2CLK_ENA_MASK, 0);
  1653. /* We always need to disable the FLL while reconfiguring */
  1654. snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
  1655. WM8995_FLL1_ENA_MASK, 0);
  1656. reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
  1657. (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
  1658. snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
  1659. WM8995_FLL1_OUTDIV_MASK |
  1660. WM8995_FLL1_FRATIO_MASK, reg);
  1661. snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
  1662. snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
  1663. WM8995_FLL1_N_MASK,
  1664. fll.n << WM8995_FLL1_N_SHIFT);
  1665. snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
  1666. WM8995_FLL1_REFCLK_DIV_MASK |
  1667. WM8995_FLL1_REFCLK_SRC_MASK,
  1668. (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
  1669. (src - 1));
  1670. if (freq_out)
  1671. snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
  1672. WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
  1673. wm8995->fll[id].in = freq_in;
  1674. wm8995->fll[id].out = freq_out;
  1675. wm8995->fll[id].src = src;
  1676. /* Enable any gated AIF clocks */
  1677. snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
  1678. WM8995_AIF1CLK_ENA_MASK, aif1);
  1679. snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
  1680. WM8995_AIF2CLK_ENA_MASK, aif2);
  1681. configure_clock(component);
  1682. return 0;
  1683. }
  1684. static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
  1685. int clk_id, unsigned int freq, int dir)
  1686. {
  1687. struct snd_soc_component *component;
  1688. struct wm8995_priv *wm8995;
  1689. component = dai->component;
  1690. wm8995 = snd_soc_component_get_drvdata(component);
  1691. switch (dai->id) {
  1692. case 0:
  1693. case 1:
  1694. break;
  1695. default:
  1696. /* AIF3 shares clocking with AIF1/2 */
  1697. return -EINVAL;
  1698. }
  1699. switch (clk_id) {
  1700. case WM8995_SYSCLK_MCLK1:
  1701. wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
  1702. wm8995->mclk[0] = freq;
  1703. dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
  1704. dai->id + 1, freq);
  1705. break;
  1706. case WM8995_SYSCLK_MCLK2:
  1707. wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
  1708. wm8995->mclk[1] = freq;
  1709. dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
  1710. dai->id + 1, freq);
  1711. break;
  1712. case WM8995_SYSCLK_FLL1:
  1713. wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
  1714. dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
  1715. break;
  1716. case WM8995_SYSCLK_FLL2:
  1717. wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
  1718. dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
  1719. break;
  1720. case WM8995_SYSCLK_OPCLK:
  1721. default:
  1722. dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
  1723. return -EINVAL;
  1724. }
  1725. configure_clock(component);
  1726. return 0;
  1727. }
  1728. static int wm8995_set_bias_level(struct snd_soc_component *component,
  1729. enum snd_soc_bias_level level)
  1730. {
  1731. struct wm8995_priv *wm8995;
  1732. int ret;
  1733. wm8995 = snd_soc_component_get_drvdata(component);
  1734. switch (level) {
  1735. case SND_SOC_BIAS_ON:
  1736. case SND_SOC_BIAS_PREPARE:
  1737. break;
  1738. case SND_SOC_BIAS_STANDBY:
  1739. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1740. ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
  1741. wm8995->supplies);
  1742. if (ret)
  1743. return ret;
  1744. ret = regcache_sync(wm8995->regmap);
  1745. if (ret) {
  1746. dev_err(component->dev,
  1747. "Failed to sync cache: %d\n", ret);
  1748. return ret;
  1749. }
  1750. snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
  1751. WM8995_BG_ENA_MASK, WM8995_BG_ENA);
  1752. }
  1753. break;
  1754. case SND_SOC_BIAS_OFF:
  1755. snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
  1756. WM8995_BG_ENA_MASK, 0);
  1757. regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
  1758. wm8995->supplies);
  1759. break;
  1760. }
  1761. return 0;
  1762. }
  1763. static int wm8995_probe(struct snd_soc_component *component)
  1764. {
  1765. struct wm8995_priv *wm8995;
  1766. int i;
  1767. int ret;
  1768. wm8995 = snd_soc_component_get_drvdata(component);
  1769. wm8995->component = component;
  1770. for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
  1771. wm8995->supplies[i].supply = wm8995_supply_names[i];
  1772. ret = devm_regulator_bulk_get(component->dev,
  1773. ARRAY_SIZE(wm8995->supplies),
  1774. wm8995->supplies);
  1775. if (ret) {
  1776. dev_err(component->dev, "Failed to request supplies: %d\n", ret);
  1777. return ret;
  1778. }
  1779. wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
  1780. wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
  1781. wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
  1782. wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
  1783. wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
  1784. wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
  1785. wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
  1786. wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
  1787. /* This should really be moved into the regulator core */
  1788. for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
  1789. ret = devm_regulator_register_notifier(
  1790. wm8995->supplies[i].consumer,
  1791. &wm8995->disable_nb[i]);
  1792. if (ret) {
  1793. dev_err(component->dev,
  1794. "Failed to register regulator notifier: %d\n",
  1795. ret);
  1796. }
  1797. }
  1798. ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
  1799. wm8995->supplies);
  1800. if (ret) {
  1801. dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
  1802. return ret;
  1803. }
  1804. ret = snd_soc_component_read(component, WM8995_SOFTWARE_RESET);
  1805. if (ret < 0) {
  1806. dev_err(component->dev, "Failed to read device ID: %d\n", ret);
  1807. goto err_reg_enable;
  1808. }
  1809. if (ret != 0x8995) {
  1810. dev_err(component->dev, "Invalid device ID: %#x\n", ret);
  1811. ret = -EINVAL;
  1812. goto err_reg_enable;
  1813. }
  1814. ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0);
  1815. if (ret < 0) {
  1816. dev_err(component->dev, "Failed to issue reset: %d\n", ret);
  1817. goto err_reg_enable;
  1818. }
  1819. /* Latch volume updates (right only; we always do left then right). */
  1820. snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME,
  1821. WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
  1822. snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME,
  1823. WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
  1824. snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME,
  1825. WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
  1826. snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME,
  1827. WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
  1828. snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME,
  1829. WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
  1830. snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME,
  1831. WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
  1832. snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME,
  1833. WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
  1834. snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME,
  1835. WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
  1836. snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
  1837. WM8995_IN1_VU_MASK, WM8995_IN1_VU);
  1838. wm8995_update_class_w(component);
  1839. return 0;
  1840. err_reg_enable:
  1841. regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
  1842. return ret;
  1843. }
  1844. #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1845. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1846. static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
  1847. .set_sysclk = wm8995_set_dai_sysclk,
  1848. .set_fmt = wm8995_set_dai_fmt,
  1849. .hw_params = wm8995_hw_params,
  1850. .mute_stream = wm8995_aif_mute,
  1851. .set_pll = wm8995_set_fll,
  1852. .set_tristate = wm8995_set_tristate,
  1853. .no_capture_mute = 1,
  1854. };
  1855. static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
  1856. .set_sysclk = wm8995_set_dai_sysclk,
  1857. .set_fmt = wm8995_set_dai_fmt,
  1858. .hw_params = wm8995_hw_params,
  1859. .mute_stream = wm8995_aif_mute,
  1860. .set_pll = wm8995_set_fll,
  1861. .set_tristate = wm8995_set_tristate,
  1862. .no_capture_mute = 1,
  1863. };
  1864. static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
  1865. .set_tristate = wm8995_set_tristate,
  1866. };
  1867. static struct snd_soc_dai_driver wm8995_dai[] = {
  1868. {
  1869. .name = "wm8995-aif1",
  1870. .playback = {
  1871. .stream_name = "AIF1 Playback",
  1872. .channels_min = 2,
  1873. .channels_max = 2,
  1874. .rates = SNDRV_PCM_RATE_8000_96000,
  1875. .formats = WM8995_FORMATS
  1876. },
  1877. .capture = {
  1878. .stream_name = "AIF1 Capture",
  1879. .channels_min = 2,
  1880. .channels_max = 2,
  1881. .rates = SNDRV_PCM_RATE_8000_48000,
  1882. .formats = WM8995_FORMATS
  1883. },
  1884. .ops = &wm8995_aif1_dai_ops
  1885. },
  1886. {
  1887. .name = "wm8995-aif2",
  1888. .playback = {
  1889. .stream_name = "AIF2 Playback",
  1890. .channels_min = 2,
  1891. .channels_max = 2,
  1892. .rates = SNDRV_PCM_RATE_8000_96000,
  1893. .formats = WM8995_FORMATS
  1894. },
  1895. .capture = {
  1896. .stream_name = "AIF2 Capture",
  1897. .channels_min = 2,
  1898. .channels_max = 2,
  1899. .rates = SNDRV_PCM_RATE_8000_48000,
  1900. .formats = WM8995_FORMATS
  1901. },
  1902. .ops = &wm8995_aif2_dai_ops
  1903. },
  1904. {
  1905. .name = "wm8995-aif3",
  1906. .playback = {
  1907. .stream_name = "AIF3 Playback",
  1908. .channels_min = 2,
  1909. .channels_max = 2,
  1910. .rates = SNDRV_PCM_RATE_8000_96000,
  1911. .formats = WM8995_FORMATS
  1912. },
  1913. .capture = {
  1914. .stream_name = "AIF3 Capture",
  1915. .channels_min = 2,
  1916. .channels_max = 2,
  1917. .rates = SNDRV_PCM_RATE_8000_48000,
  1918. .formats = WM8995_FORMATS
  1919. },
  1920. .ops = &wm8995_aif3_dai_ops
  1921. }
  1922. };
  1923. static const struct snd_soc_component_driver soc_component_dev_wm8995 = {
  1924. .probe = wm8995_probe,
  1925. .set_bias_level = wm8995_set_bias_level,
  1926. .controls = wm8995_snd_controls,
  1927. .num_controls = ARRAY_SIZE(wm8995_snd_controls),
  1928. .dapm_widgets = wm8995_dapm_widgets,
  1929. .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets),
  1930. .dapm_routes = wm8995_intercon,
  1931. .num_dapm_routes = ARRAY_SIZE(wm8995_intercon),
  1932. .use_pmdown_time = 1,
  1933. .endianness = 1,
  1934. };
  1935. static const struct regmap_config wm8995_regmap = {
  1936. .reg_bits = 16,
  1937. .val_bits = 16,
  1938. .max_register = WM8995_MAX_REGISTER,
  1939. .reg_defaults = wm8995_reg_defaults,
  1940. .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
  1941. .volatile_reg = wm8995_volatile,
  1942. .readable_reg = wm8995_readable,
  1943. .cache_type = REGCACHE_RBTREE,
  1944. };
  1945. #if defined(CONFIG_SPI_MASTER)
  1946. static int wm8995_spi_probe(struct spi_device *spi)
  1947. {
  1948. struct wm8995_priv *wm8995;
  1949. int ret;
  1950. wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
  1951. if (!wm8995)
  1952. return -ENOMEM;
  1953. spi_set_drvdata(spi, wm8995);
  1954. wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
  1955. if (IS_ERR(wm8995->regmap)) {
  1956. ret = PTR_ERR(wm8995->regmap);
  1957. dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
  1958. return ret;
  1959. }
  1960. ret = devm_snd_soc_register_component(&spi->dev,
  1961. &soc_component_dev_wm8995, wm8995_dai,
  1962. ARRAY_SIZE(wm8995_dai));
  1963. return ret;
  1964. }
  1965. static struct spi_driver wm8995_spi_driver = {
  1966. .driver = {
  1967. .name = "wm8995",
  1968. },
  1969. .probe = wm8995_spi_probe,
  1970. };
  1971. #endif
  1972. #if IS_ENABLED(CONFIG_I2C)
  1973. static int wm8995_i2c_probe(struct i2c_client *i2c)
  1974. {
  1975. struct wm8995_priv *wm8995;
  1976. int ret;
  1977. wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
  1978. if (!wm8995)
  1979. return -ENOMEM;
  1980. i2c_set_clientdata(i2c, wm8995);
  1981. wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
  1982. if (IS_ERR(wm8995->regmap)) {
  1983. ret = PTR_ERR(wm8995->regmap);
  1984. dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
  1985. return ret;
  1986. }
  1987. ret = devm_snd_soc_register_component(&i2c->dev,
  1988. &soc_component_dev_wm8995, wm8995_dai,
  1989. ARRAY_SIZE(wm8995_dai));
  1990. if (ret < 0)
  1991. dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
  1992. return ret;
  1993. }
  1994. static const struct i2c_device_id wm8995_i2c_id[] = {
  1995. {"wm8995", 0},
  1996. {}
  1997. };
  1998. MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
  1999. static struct i2c_driver wm8995_i2c_driver = {
  2000. .driver = {
  2001. .name = "wm8995",
  2002. },
  2003. .probe_new = wm8995_i2c_probe,
  2004. .id_table = wm8995_i2c_id
  2005. };
  2006. #endif
  2007. static int __init wm8995_modinit(void)
  2008. {
  2009. int ret = 0;
  2010. #if IS_ENABLED(CONFIG_I2C)
  2011. ret = i2c_add_driver(&wm8995_i2c_driver);
  2012. if (ret) {
  2013. printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
  2014. ret);
  2015. }
  2016. #endif
  2017. #if defined(CONFIG_SPI_MASTER)
  2018. ret = spi_register_driver(&wm8995_spi_driver);
  2019. if (ret) {
  2020. printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
  2021. ret);
  2022. }
  2023. #endif
  2024. return ret;
  2025. }
  2026. module_init(wm8995_modinit);
  2027. static void __exit wm8995_exit(void)
  2028. {
  2029. #if IS_ENABLED(CONFIG_I2C)
  2030. i2c_del_driver(&wm8995_i2c_driver);
  2031. #endif
  2032. #if defined(CONFIG_SPI_MASTER)
  2033. spi_unregister_driver(&wm8995_spi_driver);
  2034. #endif
  2035. }
  2036. module_exit(wm8995_exit);
  2037. MODULE_DESCRIPTION("ASoC WM8995 driver");
  2038. MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
  2039. MODULE_LICENSE("GPL");