wm8962.c 123 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8962.c -- WM8962 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010-2 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/gcd.h>
  16. #include <linux/gpio/driver.h>
  17. #include <linux/i2c.h>
  18. #include <linux/input.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/mutex.h>
  25. #include <sound/core.h>
  26. #include <sound/jack.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/soc.h>
  30. #include <sound/initval.h>
  31. #include <sound/tlv.h>
  32. #include <sound/wm8962.h>
  33. #include <trace/events/asoc.h>
  34. #include "wm8962.h"
  35. #define WM8962_NUM_SUPPLIES 8
  36. static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  37. "DCVDD",
  38. "DBVDD",
  39. "AVDD",
  40. "CPVDD",
  41. "MICVDD",
  42. "PLLVDD",
  43. "SPKVDD1",
  44. "SPKVDD2",
  45. };
  46. /* codec private data */
  47. struct wm8962_priv {
  48. struct wm8962_pdata pdata;
  49. struct regmap *regmap;
  50. struct snd_soc_component *component;
  51. int sysclk;
  52. int sysclk_rate;
  53. int bclk; /* Desired BCLK */
  54. int lrclk;
  55. struct completion fll_lock;
  56. int fll_src;
  57. int fll_fref;
  58. int fll_fout;
  59. struct mutex dsp2_ena_lock;
  60. u16 dsp2_ena;
  61. struct delayed_work mic_work;
  62. struct snd_soc_jack *jack;
  63. struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  64. struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  65. struct input_dev *beep;
  66. struct work_struct beep_work;
  67. int beep_rate;
  68. #ifdef CONFIG_GPIOLIB
  69. struct gpio_chip gpio_chip;
  70. #endif
  71. int irq;
  72. };
  73. /* We can't use the same notifier block for more than one supply and
  74. * there's no way I can see to get from a callback to the caller
  75. * except container_of().
  76. */
  77. #define WM8962_REGULATOR_EVENT(n) \
  78. static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  79. unsigned long event, void *data) \
  80. { \
  81. struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  82. disable_nb[n]); \
  83. if (event & REGULATOR_EVENT_DISABLE) { \
  84. regcache_mark_dirty(wm8962->regmap); \
  85. } \
  86. return 0; \
  87. }
  88. WM8962_REGULATOR_EVENT(0)
  89. WM8962_REGULATOR_EVENT(1)
  90. WM8962_REGULATOR_EVENT(2)
  91. WM8962_REGULATOR_EVENT(3)
  92. WM8962_REGULATOR_EVENT(4)
  93. WM8962_REGULATOR_EVENT(5)
  94. WM8962_REGULATOR_EVENT(6)
  95. WM8962_REGULATOR_EVENT(7)
  96. static const struct reg_default wm8962_reg[] = {
  97. { 0, 0x009F }, /* R0 - Left Input volume */
  98. { 1, 0x049F }, /* R1 - Right Input volume */
  99. { 2, 0x0000 }, /* R2 - HPOUTL volume */
  100. { 3, 0x0000 }, /* R3 - HPOUTR volume */
  101. { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
  102. { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
  103. { 7, 0x000A }, /* R7 - Audio Interface 0 */
  104. { 8, 0x01E4 }, /* R8 - Clocking2 */
  105. { 9, 0x0300 }, /* R9 - Audio Interface 1 */
  106. { 10, 0x00C0 }, /* R10 - Left DAC volume */
  107. { 11, 0x00C0 }, /* R11 - Right DAC volume */
  108. { 14, 0x0040 }, /* R14 - Audio Interface 2 */
  109. { 15, 0x6243 }, /* R15 - Software Reset */
  110. { 17, 0x007B }, /* R17 - ALC1 */
  111. { 18, 0x0000 }, /* R18 - ALC2 */
  112. { 19, 0x1C32 }, /* R19 - ALC3 */
  113. { 20, 0x3200 }, /* R20 - Noise Gate */
  114. { 21, 0x00C0 }, /* R21 - Left ADC volume */
  115. { 22, 0x00C0 }, /* R22 - Right ADC volume */
  116. { 23, 0x0160 }, /* R23 - Additional control(1) */
  117. { 24, 0x0000 }, /* R24 - Additional control(2) */
  118. { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
  119. { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
  120. { 27, 0x0010 }, /* R27 - Additional Control (3) */
  121. { 28, 0x0000 }, /* R28 - Anti-pop */
  122. { 30, 0x005E }, /* R30 - Clocking 3 */
  123. { 31, 0x0000 }, /* R31 - Input mixer control (1) */
  124. { 32, 0x0145 }, /* R32 - Left input mixer volume */
  125. { 33, 0x0145 }, /* R33 - Right input mixer volume */
  126. { 34, 0x0009 }, /* R34 - Input mixer control (2) */
  127. { 35, 0x0003 }, /* R35 - Input bias control */
  128. { 37, 0x0008 }, /* R37 - Left input PGA control */
  129. { 38, 0x0008 }, /* R38 - Right input PGA control */
  130. { 40, 0x0000 }, /* R40 - SPKOUTL volume */
  131. { 41, 0x0000 }, /* R41 - SPKOUTR volume */
  132. { 49, 0x0010 }, /* R49 - Class D Control 1 */
  133. { 51, 0x0003 }, /* R51 - Class D Control 2 */
  134. { 56, 0x0506 }, /* R56 - Clocking 4 */
  135. { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
  136. { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
  137. { 60, 0x0300 }, /* R60 - DC Servo 0 */
  138. { 61, 0x0300 }, /* R61 - DC Servo 1 */
  139. { 64, 0x0810 }, /* R64 - DC Servo 4 */
  140. { 68, 0x001B }, /* R68 - Analogue PGA Bias */
  141. { 69, 0x0000 }, /* R69 - Analogue HP 0 */
  142. { 71, 0x01FB }, /* R71 - Analogue HP 2 */
  143. { 72, 0x0000 }, /* R72 - Charge Pump 1 */
  144. { 82, 0x0004 }, /* R82 - Charge Pump B */
  145. { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
  146. { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
  147. { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
  148. { 94, 0x0000 }, /* R94 - Control Interface */
  149. { 99, 0x0000 }, /* R99 - Mixer Enables */
  150. { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
  151. { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
  152. { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
  153. { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
  154. { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
  155. { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
  156. { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
  157. { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
  158. { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
  159. { 110, 0x0002 }, /* R110 - Beep Generator (1) */
  160. { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
  161. { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
  162. { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
  163. { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
  164. { 125, 0x004B }, /* R125 - Analogue Clocking2 */
  165. { 126, 0x000D }, /* R126 - Analogue Clocking3 */
  166. { 127, 0x0000 }, /* R127 - PLL Software Reset */
  167. { 131, 0x0000 }, /* R131 - PLL 4 */
  168. { 136, 0x0067 }, /* R136 - PLL 9 */
  169. { 137, 0x001C }, /* R137 - PLL 10 */
  170. { 138, 0x0071 }, /* R138 - PLL 11 */
  171. { 139, 0x00C7 }, /* R139 - PLL 12 */
  172. { 140, 0x0067 }, /* R140 - PLL 13 */
  173. { 141, 0x0048 }, /* R141 - PLL 14 */
  174. { 142, 0x0022 }, /* R142 - PLL 15 */
  175. { 143, 0x0097 }, /* R143 - PLL 16 */
  176. { 155, 0x000C }, /* R155 - FLL Control (1) */
  177. { 156, 0x0039 }, /* R156 - FLL Control (2) */
  178. { 157, 0x0180 }, /* R157 - FLL Control (3) */
  179. { 159, 0x0032 }, /* R159 - FLL Control (5) */
  180. { 160, 0x0018 }, /* R160 - FLL Control (6) */
  181. { 161, 0x007D }, /* R161 - FLL Control (7) */
  182. { 162, 0x0008 }, /* R162 - FLL Control (8) */
  183. { 252, 0x0005 }, /* R252 - General test 1 */
  184. { 256, 0x0000 }, /* R256 - DF1 */
  185. { 257, 0x0000 }, /* R257 - DF2 */
  186. { 258, 0x0000 }, /* R258 - DF3 */
  187. { 259, 0x0000 }, /* R259 - DF4 */
  188. { 260, 0x0000 }, /* R260 - DF5 */
  189. { 261, 0x0000 }, /* R261 - DF6 */
  190. { 262, 0x0000 }, /* R262 - DF7 */
  191. { 264, 0x0000 }, /* R264 - LHPF1 */
  192. { 265, 0x0000 }, /* R265 - LHPF2 */
  193. { 268, 0x0000 }, /* R268 - THREED1 */
  194. { 269, 0x0000 }, /* R269 - THREED2 */
  195. { 270, 0x0000 }, /* R270 - THREED3 */
  196. { 271, 0x0000 }, /* R271 - THREED4 */
  197. { 276, 0x000C }, /* R276 - DRC 1 */
  198. { 277, 0x0925 }, /* R277 - DRC 2 */
  199. { 278, 0x0000 }, /* R278 - DRC 3 */
  200. { 279, 0x0000 }, /* R279 - DRC 4 */
  201. { 280, 0x0000 }, /* R280 - DRC 5 */
  202. { 285, 0x0000 }, /* R285 - Tloopback */
  203. { 335, 0x0004 }, /* R335 - EQ1 */
  204. { 336, 0x6318 }, /* R336 - EQ2 */
  205. { 337, 0x6300 }, /* R337 - EQ3 */
  206. { 338, 0x0FCA }, /* R338 - EQ4 */
  207. { 339, 0x0400 }, /* R339 - EQ5 */
  208. { 340, 0x00D8 }, /* R340 - EQ6 */
  209. { 341, 0x1EB5 }, /* R341 - EQ7 */
  210. { 342, 0xF145 }, /* R342 - EQ8 */
  211. { 343, 0x0B75 }, /* R343 - EQ9 */
  212. { 344, 0x01C5 }, /* R344 - EQ10 */
  213. { 345, 0x1C58 }, /* R345 - EQ11 */
  214. { 346, 0xF373 }, /* R346 - EQ12 */
  215. { 347, 0x0A54 }, /* R347 - EQ13 */
  216. { 348, 0x0558 }, /* R348 - EQ14 */
  217. { 349, 0x168E }, /* R349 - EQ15 */
  218. { 350, 0xF829 }, /* R350 - EQ16 */
  219. { 351, 0x07AD }, /* R351 - EQ17 */
  220. { 352, 0x1103 }, /* R352 - EQ18 */
  221. { 353, 0x0564 }, /* R353 - EQ19 */
  222. { 354, 0x0559 }, /* R354 - EQ20 */
  223. { 355, 0x4000 }, /* R355 - EQ21 */
  224. { 356, 0x6318 }, /* R356 - EQ22 */
  225. { 357, 0x6300 }, /* R357 - EQ23 */
  226. { 358, 0x0FCA }, /* R358 - EQ24 */
  227. { 359, 0x0400 }, /* R359 - EQ25 */
  228. { 360, 0x00D8 }, /* R360 - EQ26 */
  229. { 361, 0x1EB5 }, /* R361 - EQ27 */
  230. { 362, 0xF145 }, /* R362 - EQ28 */
  231. { 363, 0x0B75 }, /* R363 - EQ29 */
  232. { 364, 0x01C5 }, /* R364 - EQ30 */
  233. { 365, 0x1C58 }, /* R365 - EQ31 */
  234. { 366, 0xF373 }, /* R366 - EQ32 */
  235. { 367, 0x0A54 }, /* R367 - EQ33 */
  236. { 368, 0x0558 }, /* R368 - EQ34 */
  237. { 369, 0x168E }, /* R369 - EQ35 */
  238. { 370, 0xF829 }, /* R370 - EQ36 */
  239. { 371, 0x07AD }, /* R371 - EQ37 */
  240. { 372, 0x1103 }, /* R372 - EQ38 */
  241. { 373, 0x0564 }, /* R373 - EQ39 */
  242. { 374, 0x0559 }, /* R374 - EQ40 */
  243. { 375, 0x4000 }, /* R375 - EQ41 */
  244. { 513, 0x0000 }, /* R513 - GPIO 2 */
  245. { 514, 0x0000 }, /* R514 - GPIO 3 */
  246. { 516, 0x8100 }, /* R516 - GPIO 5 */
  247. { 517, 0x8100 }, /* R517 - GPIO 6 */
  248. { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
  249. { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
  250. { 576, 0x0000 }, /* R576 - Interrupt Control */
  251. { 584, 0x002D }, /* R584 - IRQ Debounce */
  252. { 586, 0x0000 }, /* R586 - MICINT Source Pol */
  253. { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
  254. { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
  255. { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
  256. { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
  257. { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
  258. { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
  259. { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
  260. { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
  261. { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
  262. { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
  263. { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
  264. { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
  265. { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
  266. { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
  267. { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
  268. { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
  269. { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
  270. { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
  271. { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
  272. { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
  273. { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
  274. { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
  275. { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
  276. { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
  277. { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
  278. { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
  279. { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
  280. { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
  281. { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
  282. { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
  283. { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
  284. { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
  285. { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
  286. { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
  287. { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
  288. { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
  289. { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
  290. { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
  291. { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
  292. { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
  293. { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
  294. { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
  295. { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
  296. { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
  297. { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
  298. { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
  299. { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
  300. { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
  301. { 17408, 0x0083 }, /* R17408 - HPF_C_1 */
  302. { 17409, 0x98AD }, /* R17409 - HPF_C_0 */
  303. { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
  304. { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
  305. { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
  306. { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
  307. { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
  308. { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
  309. { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
  310. { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
  311. { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
  312. { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
  313. { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
  314. { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
  315. { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
  316. { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
  317. { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
  318. { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
  319. { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
  320. { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
  321. { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
  322. { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
  323. { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
  324. { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
  325. { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
  326. { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
  327. { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
  328. { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
  329. { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
  330. { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
  331. { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
  332. { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
  333. { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
  334. { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
  335. { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
  336. { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
  337. { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
  338. { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
  339. { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
  340. { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
  341. { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
  342. { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
  343. { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
  344. { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
  345. { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
  346. { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
  347. { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
  348. { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
  349. { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
  350. { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
  351. { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
  352. { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
  353. { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
  354. { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
  355. { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
  356. { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
  357. { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
  358. { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
  359. { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
  360. { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
  361. { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
  362. { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
  363. { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
  364. { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
  365. { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
  366. { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
  367. { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
  368. { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
  369. { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
  370. { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
  371. { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
  372. { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
  373. { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
  374. { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
  375. { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
  376. { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
  377. { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
  378. { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
  379. { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
  380. { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
  381. { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
  382. { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
  383. { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
  384. { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
  385. { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
  386. { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
  387. { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
  388. { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
  389. { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
  390. { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
  391. { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
  392. { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
  393. { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
  394. { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
  395. { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
  396. { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
  397. { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
  398. { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
  399. { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
  400. { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
  401. { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
  402. { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
  403. { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
  404. { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
  405. { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
  406. { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
  407. { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
  408. { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
  409. { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
  410. { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
  411. { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
  412. { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
  413. { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
  414. { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
  415. { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
  416. { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
  417. { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
  418. { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
  419. { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
  420. { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
  421. { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
  422. { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
  423. { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
  424. { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
  425. { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
  426. { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
  427. { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
  428. { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
  429. { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
  430. { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
  431. { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
  432. { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
  433. { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
  434. { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
  435. { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
  436. { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
  437. { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
  438. { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
  439. { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
  440. { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
  441. { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
  442. { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
  443. { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
  444. { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
  445. { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
  446. { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
  447. { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
  448. { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
  449. { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
  450. { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
  451. { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
  452. { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
  453. { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
  454. { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
  455. { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
  456. { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
  457. { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
  458. { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
  459. { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
  460. { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
  461. { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
  462. { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
  463. { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
  464. { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
  465. { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
  466. { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
  467. { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
  468. { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
  469. { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
  470. { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
  471. { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
  472. { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
  473. { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
  474. { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
  475. { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
  476. { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
  477. { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
  478. { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
  479. { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
  480. { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
  481. { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
  482. { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
  483. { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
  484. { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
  485. { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
  486. { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
  487. { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
  488. { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
  489. { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
  490. { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
  491. { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
  492. { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
  493. { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
  494. { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
  495. { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
  496. { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
  497. { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
  498. { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
  499. { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
  500. { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
  501. { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
  502. { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
  503. { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
  504. { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
  505. { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
  506. { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
  507. { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
  508. { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
  509. { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
  510. { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
  511. { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
  512. { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
  513. { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
  514. { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
  515. { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
  516. { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
  517. { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
  518. { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
  519. { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
  520. { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
  521. { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
  522. { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
  523. { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
  524. { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
  525. { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
  526. { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
  527. { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
  528. { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
  529. { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
  530. { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
  531. { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
  532. { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
  533. { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
  534. { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
  535. { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
  536. { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
  537. { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
  538. { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
  539. { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
  540. { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
  541. { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
  542. { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
  543. { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
  544. { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
  545. { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
  546. { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
  547. { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
  548. { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
  549. { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
  550. { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
  551. { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
  552. { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
  553. { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
  554. { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
  555. { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
  556. { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
  557. { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
  558. { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
  559. { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
  560. { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
  561. { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
  562. { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
  563. { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
  564. { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
  565. { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
  566. { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
  567. { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
  568. { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
  569. { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
  570. { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
  571. { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
  572. { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
  573. { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
  574. { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
  575. { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
  576. { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
  577. { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
  578. { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
  579. { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
  580. { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
  581. { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
  582. { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
  583. { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
  584. { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
  585. { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
  586. { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
  587. { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
  588. { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
  589. { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
  590. { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
  591. { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
  592. { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
  593. { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
  594. { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
  595. { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
  596. { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
  597. { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
  598. { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
  599. { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
  600. { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
  601. { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
  602. { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
  603. { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
  604. { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
  605. { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
  606. { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
  607. { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
  608. { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
  609. { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
  610. { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
  611. { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
  612. { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
  613. { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
  614. { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
  615. { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
  616. { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
  617. { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
  618. { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
  619. { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
  620. { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
  621. { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
  622. { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
  623. { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
  624. { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
  625. { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
  626. { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
  627. { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
  628. { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
  629. { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
  630. { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
  631. { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
  632. { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
  633. { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
  634. { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
  635. { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
  636. { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
  637. { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
  638. { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
  639. { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
  640. { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
  641. { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
  642. { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
  643. { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
  644. { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
  645. { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
  646. { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
  647. { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
  648. { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
  649. { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
  650. { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
  651. { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
  652. { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
  653. { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
  654. { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
  655. { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
  656. { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
  657. { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
  658. { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
  659. { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
  660. { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
  661. { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
  662. { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
  663. { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
  664. { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
  665. { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
  666. { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
  667. { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
  668. { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
  669. { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
  670. { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
  671. { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
  672. { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
  673. { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
  674. { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
  675. { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
  676. { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
  677. { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
  678. { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
  679. { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
  680. { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
  681. { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
  682. { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
  683. { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
  684. { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
  685. { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
  686. { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
  687. { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
  688. { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
  689. { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
  690. { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
  691. { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
  692. { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
  693. { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
  694. { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
  695. { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
  696. { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
  697. { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
  698. { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
  699. { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
  700. { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
  701. { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
  702. { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
  703. { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
  704. { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
  705. { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
  706. { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
  707. { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
  708. { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
  709. { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
  710. { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
  711. { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
  712. { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
  713. { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
  714. { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
  715. };
  716. static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
  717. {
  718. switch (reg) {
  719. case WM8962_CLOCKING1:
  720. case WM8962_SOFTWARE_RESET:
  721. case WM8962_THERMAL_SHUTDOWN_STATUS:
  722. case WM8962_ADDITIONAL_CONTROL_4:
  723. case WM8962_DC_SERVO_6:
  724. case WM8962_INTERRUPT_STATUS_1:
  725. case WM8962_INTERRUPT_STATUS_2:
  726. case WM8962_DSP2_EXECCONTROL:
  727. return true;
  728. default:
  729. return false;
  730. }
  731. }
  732. static bool wm8962_readable_register(struct device *dev, unsigned int reg)
  733. {
  734. switch (reg) {
  735. case WM8962_LEFT_INPUT_VOLUME:
  736. case WM8962_RIGHT_INPUT_VOLUME:
  737. case WM8962_HPOUTL_VOLUME:
  738. case WM8962_HPOUTR_VOLUME:
  739. case WM8962_CLOCKING1:
  740. case WM8962_ADC_DAC_CONTROL_1:
  741. case WM8962_ADC_DAC_CONTROL_2:
  742. case WM8962_AUDIO_INTERFACE_0:
  743. case WM8962_CLOCKING2:
  744. case WM8962_AUDIO_INTERFACE_1:
  745. case WM8962_LEFT_DAC_VOLUME:
  746. case WM8962_RIGHT_DAC_VOLUME:
  747. case WM8962_AUDIO_INTERFACE_2:
  748. case WM8962_SOFTWARE_RESET:
  749. case WM8962_ALC1:
  750. case WM8962_ALC2:
  751. case WM8962_ALC3:
  752. case WM8962_NOISE_GATE:
  753. case WM8962_LEFT_ADC_VOLUME:
  754. case WM8962_RIGHT_ADC_VOLUME:
  755. case WM8962_ADDITIONAL_CONTROL_1:
  756. case WM8962_ADDITIONAL_CONTROL_2:
  757. case WM8962_PWR_MGMT_1:
  758. case WM8962_PWR_MGMT_2:
  759. case WM8962_ADDITIONAL_CONTROL_3:
  760. case WM8962_ANTI_POP:
  761. case WM8962_CLOCKING_3:
  762. case WM8962_INPUT_MIXER_CONTROL_1:
  763. case WM8962_LEFT_INPUT_MIXER_VOLUME:
  764. case WM8962_RIGHT_INPUT_MIXER_VOLUME:
  765. case WM8962_INPUT_MIXER_CONTROL_2:
  766. case WM8962_INPUT_BIAS_CONTROL:
  767. case WM8962_LEFT_INPUT_PGA_CONTROL:
  768. case WM8962_RIGHT_INPUT_PGA_CONTROL:
  769. case WM8962_SPKOUTL_VOLUME:
  770. case WM8962_SPKOUTR_VOLUME:
  771. case WM8962_THERMAL_SHUTDOWN_STATUS:
  772. case WM8962_ADDITIONAL_CONTROL_4:
  773. case WM8962_CLASS_D_CONTROL_1:
  774. case WM8962_CLASS_D_CONTROL_2:
  775. case WM8962_CLOCKING_4:
  776. case WM8962_DAC_DSP_MIXING_1:
  777. case WM8962_DAC_DSP_MIXING_2:
  778. case WM8962_DC_SERVO_0:
  779. case WM8962_DC_SERVO_1:
  780. case WM8962_DC_SERVO_4:
  781. case WM8962_DC_SERVO_6:
  782. case WM8962_ANALOGUE_PGA_BIAS:
  783. case WM8962_ANALOGUE_HP_0:
  784. case WM8962_ANALOGUE_HP_2:
  785. case WM8962_CHARGE_PUMP_1:
  786. case WM8962_CHARGE_PUMP_B:
  787. case WM8962_WRITE_SEQUENCER_CONTROL_1:
  788. case WM8962_WRITE_SEQUENCER_CONTROL_2:
  789. case WM8962_WRITE_SEQUENCER_CONTROL_3:
  790. case WM8962_CONTROL_INTERFACE:
  791. case WM8962_MIXER_ENABLES:
  792. case WM8962_HEADPHONE_MIXER_1:
  793. case WM8962_HEADPHONE_MIXER_2:
  794. case WM8962_HEADPHONE_MIXER_3:
  795. case WM8962_HEADPHONE_MIXER_4:
  796. case WM8962_SPEAKER_MIXER_1:
  797. case WM8962_SPEAKER_MIXER_2:
  798. case WM8962_SPEAKER_MIXER_3:
  799. case WM8962_SPEAKER_MIXER_4:
  800. case WM8962_SPEAKER_MIXER_5:
  801. case WM8962_BEEP_GENERATOR_1:
  802. case WM8962_OSCILLATOR_TRIM_3:
  803. case WM8962_OSCILLATOR_TRIM_4:
  804. case WM8962_OSCILLATOR_TRIM_7:
  805. case WM8962_ANALOGUE_CLOCKING1:
  806. case WM8962_ANALOGUE_CLOCKING2:
  807. case WM8962_ANALOGUE_CLOCKING3:
  808. case WM8962_PLL_SOFTWARE_RESET:
  809. case WM8962_PLL2:
  810. case WM8962_PLL_4:
  811. case WM8962_PLL_9:
  812. case WM8962_PLL_10:
  813. case WM8962_PLL_11:
  814. case WM8962_PLL_12:
  815. case WM8962_PLL_13:
  816. case WM8962_PLL_14:
  817. case WM8962_PLL_15:
  818. case WM8962_PLL_16:
  819. case WM8962_FLL_CONTROL_1:
  820. case WM8962_FLL_CONTROL_2:
  821. case WM8962_FLL_CONTROL_3:
  822. case WM8962_FLL_CONTROL_5:
  823. case WM8962_FLL_CONTROL_6:
  824. case WM8962_FLL_CONTROL_7:
  825. case WM8962_FLL_CONTROL_8:
  826. case WM8962_GENERAL_TEST_1:
  827. case WM8962_DF1:
  828. case WM8962_DF2:
  829. case WM8962_DF3:
  830. case WM8962_DF4:
  831. case WM8962_DF5:
  832. case WM8962_DF6:
  833. case WM8962_DF7:
  834. case WM8962_LHPF1:
  835. case WM8962_LHPF2:
  836. case WM8962_THREED1:
  837. case WM8962_THREED2:
  838. case WM8962_THREED3:
  839. case WM8962_THREED4:
  840. case WM8962_DRC_1:
  841. case WM8962_DRC_2:
  842. case WM8962_DRC_3:
  843. case WM8962_DRC_4:
  844. case WM8962_DRC_5:
  845. case WM8962_TLOOPBACK:
  846. case WM8962_EQ1:
  847. case WM8962_EQ2:
  848. case WM8962_EQ3:
  849. case WM8962_EQ4:
  850. case WM8962_EQ5:
  851. case WM8962_EQ6:
  852. case WM8962_EQ7:
  853. case WM8962_EQ8:
  854. case WM8962_EQ9:
  855. case WM8962_EQ10:
  856. case WM8962_EQ11:
  857. case WM8962_EQ12:
  858. case WM8962_EQ13:
  859. case WM8962_EQ14:
  860. case WM8962_EQ15:
  861. case WM8962_EQ16:
  862. case WM8962_EQ17:
  863. case WM8962_EQ18:
  864. case WM8962_EQ19:
  865. case WM8962_EQ20:
  866. case WM8962_EQ21:
  867. case WM8962_EQ22:
  868. case WM8962_EQ23:
  869. case WM8962_EQ24:
  870. case WM8962_EQ25:
  871. case WM8962_EQ26:
  872. case WM8962_EQ27:
  873. case WM8962_EQ28:
  874. case WM8962_EQ29:
  875. case WM8962_EQ30:
  876. case WM8962_EQ31:
  877. case WM8962_EQ32:
  878. case WM8962_EQ33:
  879. case WM8962_EQ34:
  880. case WM8962_EQ35:
  881. case WM8962_EQ36:
  882. case WM8962_EQ37:
  883. case WM8962_EQ38:
  884. case WM8962_EQ39:
  885. case WM8962_EQ40:
  886. case WM8962_EQ41:
  887. case WM8962_GPIO_2:
  888. case WM8962_GPIO_3:
  889. case WM8962_GPIO_5:
  890. case WM8962_GPIO_6:
  891. case WM8962_INTERRUPT_STATUS_1:
  892. case WM8962_INTERRUPT_STATUS_2:
  893. case WM8962_INTERRUPT_STATUS_1_MASK:
  894. case WM8962_INTERRUPT_STATUS_2_MASK:
  895. case WM8962_INTERRUPT_CONTROL:
  896. case WM8962_IRQ_DEBOUNCE:
  897. case WM8962_MICINT_SOURCE_POL:
  898. case WM8962_DSP2_POWER_MANAGEMENT:
  899. case WM8962_DSP2_EXECCONTROL:
  900. case WM8962_DSP2_INSTRUCTION_RAM_0:
  901. case WM8962_DSP2_ADDRESS_RAM_2:
  902. case WM8962_DSP2_ADDRESS_RAM_1:
  903. case WM8962_DSP2_ADDRESS_RAM_0:
  904. case WM8962_DSP2_DATA1_RAM_1:
  905. case WM8962_DSP2_DATA1_RAM_0:
  906. case WM8962_DSP2_DATA2_RAM_1:
  907. case WM8962_DSP2_DATA2_RAM_0:
  908. case WM8962_DSP2_DATA3_RAM_1:
  909. case WM8962_DSP2_DATA3_RAM_0:
  910. case WM8962_DSP2_COEFF_RAM_0:
  911. case WM8962_RETUNEADC_SHARED_COEFF_1:
  912. case WM8962_RETUNEADC_SHARED_COEFF_0:
  913. case WM8962_RETUNEDAC_SHARED_COEFF_1:
  914. case WM8962_RETUNEDAC_SHARED_COEFF_0:
  915. case WM8962_SOUNDSTAGE_ENABLES_1:
  916. case WM8962_SOUNDSTAGE_ENABLES_0:
  917. case WM8962_HDBASS_AI_1:
  918. case WM8962_HDBASS_AI_0:
  919. case WM8962_HDBASS_AR_1:
  920. case WM8962_HDBASS_AR_0:
  921. case WM8962_HDBASS_B_1:
  922. case WM8962_HDBASS_B_0:
  923. case WM8962_HDBASS_K_1:
  924. case WM8962_HDBASS_K_0:
  925. case WM8962_HDBASS_N1_1:
  926. case WM8962_HDBASS_N1_0:
  927. case WM8962_HDBASS_N2_1:
  928. case WM8962_HDBASS_N2_0:
  929. case WM8962_HDBASS_N3_1:
  930. case WM8962_HDBASS_N3_0:
  931. case WM8962_HDBASS_N4_1:
  932. case WM8962_HDBASS_N4_0:
  933. case WM8962_HDBASS_N5_1:
  934. case WM8962_HDBASS_N5_0:
  935. case WM8962_HDBASS_X1_1:
  936. case WM8962_HDBASS_X1_0:
  937. case WM8962_HDBASS_X2_1:
  938. case WM8962_HDBASS_X2_0:
  939. case WM8962_HDBASS_X3_1:
  940. case WM8962_HDBASS_X3_0:
  941. case WM8962_HDBASS_ATK_1:
  942. case WM8962_HDBASS_ATK_0:
  943. case WM8962_HDBASS_DCY_1:
  944. case WM8962_HDBASS_DCY_0:
  945. case WM8962_HDBASS_PG_1:
  946. case WM8962_HDBASS_PG_0:
  947. case WM8962_HPF_C_1:
  948. case WM8962_HPF_C_0:
  949. case WM8962_ADCL_RETUNE_C1_1:
  950. case WM8962_ADCL_RETUNE_C1_0:
  951. case WM8962_ADCL_RETUNE_C2_1:
  952. case WM8962_ADCL_RETUNE_C2_0:
  953. case WM8962_ADCL_RETUNE_C3_1:
  954. case WM8962_ADCL_RETUNE_C3_0:
  955. case WM8962_ADCL_RETUNE_C4_1:
  956. case WM8962_ADCL_RETUNE_C4_0:
  957. case WM8962_ADCL_RETUNE_C5_1:
  958. case WM8962_ADCL_RETUNE_C5_0:
  959. case WM8962_ADCL_RETUNE_C6_1:
  960. case WM8962_ADCL_RETUNE_C6_0:
  961. case WM8962_ADCL_RETUNE_C7_1:
  962. case WM8962_ADCL_RETUNE_C7_0:
  963. case WM8962_ADCL_RETUNE_C8_1:
  964. case WM8962_ADCL_RETUNE_C8_0:
  965. case WM8962_ADCL_RETUNE_C9_1:
  966. case WM8962_ADCL_RETUNE_C9_0:
  967. case WM8962_ADCL_RETUNE_C10_1:
  968. case WM8962_ADCL_RETUNE_C10_0:
  969. case WM8962_ADCL_RETUNE_C11_1:
  970. case WM8962_ADCL_RETUNE_C11_0:
  971. case WM8962_ADCL_RETUNE_C12_1:
  972. case WM8962_ADCL_RETUNE_C12_0:
  973. case WM8962_ADCL_RETUNE_C13_1:
  974. case WM8962_ADCL_RETUNE_C13_0:
  975. case WM8962_ADCL_RETUNE_C14_1:
  976. case WM8962_ADCL_RETUNE_C14_0:
  977. case WM8962_ADCL_RETUNE_C15_1:
  978. case WM8962_ADCL_RETUNE_C15_0:
  979. case WM8962_ADCL_RETUNE_C16_1:
  980. case WM8962_ADCL_RETUNE_C16_0:
  981. case WM8962_ADCL_RETUNE_C17_1:
  982. case WM8962_ADCL_RETUNE_C17_0:
  983. case WM8962_ADCL_RETUNE_C18_1:
  984. case WM8962_ADCL_RETUNE_C18_0:
  985. case WM8962_ADCL_RETUNE_C19_1:
  986. case WM8962_ADCL_RETUNE_C19_0:
  987. case WM8962_ADCL_RETUNE_C20_1:
  988. case WM8962_ADCL_RETUNE_C20_0:
  989. case WM8962_ADCL_RETUNE_C21_1:
  990. case WM8962_ADCL_RETUNE_C21_0:
  991. case WM8962_ADCL_RETUNE_C22_1:
  992. case WM8962_ADCL_RETUNE_C22_0:
  993. case WM8962_ADCL_RETUNE_C23_1:
  994. case WM8962_ADCL_RETUNE_C23_0:
  995. case WM8962_ADCL_RETUNE_C24_1:
  996. case WM8962_ADCL_RETUNE_C24_0:
  997. case WM8962_ADCL_RETUNE_C25_1:
  998. case WM8962_ADCL_RETUNE_C25_0:
  999. case WM8962_ADCL_RETUNE_C26_1:
  1000. case WM8962_ADCL_RETUNE_C26_0:
  1001. case WM8962_ADCL_RETUNE_C27_1:
  1002. case WM8962_ADCL_RETUNE_C27_0:
  1003. case WM8962_ADCL_RETUNE_C28_1:
  1004. case WM8962_ADCL_RETUNE_C28_0:
  1005. case WM8962_ADCL_RETUNE_C29_1:
  1006. case WM8962_ADCL_RETUNE_C29_0:
  1007. case WM8962_ADCL_RETUNE_C30_1:
  1008. case WM8962_ADCL_RETUNE_C30_0:
  1009. case WM8962_ADCL_RETUNE_C31_1:
  1010. case WM8962_ADCL_RETUNE_C31_0:
  1011. case WM8962_ADCL_RETUNE_C32_1:
  1012. case WM8962_ADCL_RETUNE_C32_0:
  1013. case WM8962_RETUNEADC_PG2_1:
  1014. case WM8962_RETUNEADC_PG2_0:
  1015. case WM8962_RETUNEADC_PG_1:
  1016. case WM8962_RETUNEADC_PG_0:
  1017. case WM8962_ADCR_RETUNE_C1_1:
  1018. case WM8962_ADCR_RETUNE_C1_0:
  1019. case WM8962_ADCR_RETUNE_C2_1:
  1020. case WM8962_ADCR_RETUNE_C2_0:
  1021. case WM8962_ADCR_RETUNE_C3_1:
  1022. case WM8962_ADCR_RETUNE_C3_0:
  1023. case WM8962_ADCR_RETUNE_C4_1:
  1024. case WM8962_ADCR_RETUNE_C4_0:
  1025. case WM8962_ADCR_RETUNE_C5_1:
  1026. case WM8962_ADCR_RETUNE_C5_0:
  1027. case WM8962_ADCR_RETUNE_C6_1:
  1028. case WM8962_ADCR_RETUNE_C6_0:
  1029. case WM8962_ADCR_RETUNE_C7_1:
  1030. case WM8962_ADCR_RETUNE_C7_0:
  1031. case WM8962_ADCR_RETUNE_C8_1:
  1032. case WM8962_ADCR_RETUNE_C8_0:
  1033. case WM8962_ADCR_RETUNE_C9_1:
  1034. case WM8962_ADCR_RETUNE_C9_0:
  1035. case WM8962_ADCR_RETUNE_C10_1:
  1036. case WM8962_ADCR_RETUNE_C10_0:
  1037. case WM8962_ADCR_RETUNE_C11_1:
  1038. case WM8962_ADCR_RETUNE_C11_0:
  1039. case WM8962_ADCR_RETUNE_C12_1:
  1040. case WM8962_ADCR_RETUNE_C12_0:
  1041. case WM8962_ADCR_RETUNE_C13_1:
  1042. case WM8962_ADCR_RETUNE_C13_0:
  1043. case WM8962_ADCR_RETUNE_C14_1:
  1044. case WM8962_ADCR_RETUNE_C14_0:
  1045. case WM8962_ADCR_RETUNE_C15_1:
  1046. case WM8962_ADCR_RETUNE_C15_0:
  1047. case WM8962_ADCR_RETUNE_C16_1:
  1048. case WM8962_ADCR_RETUNE_C16_0:
  1049. case WM8962_ADCR_RETUNE_C17_1:
  1050. case WM8962_ADCR_RETUNE_C17_0:
  1051. case WM8962_ADCR_RETUNE_C18_1:
  1052. case WM8962_ADCR_RETUNE_C18_0:
  1053. case WM8962_ADCR_RETUNE_C19_1:
  1054. case WM8962_ADCR_RETUNE_C19_0:
  1055. case WM8962_ADCR_RETUNE_C20_1:
  1056. case WM8962_ADCR_RETUNE_C20_0:
  1057. case WM8962_ADCR_RETUNE_C21_1:
  1058. case WM8962_ADCR_RETUNE_C21_0:
  1059. case WM8962_ADCR_RETUNE_C22_1:
  1060. case WM8962_ADCR_RETUNE_C22_0:
  1061. case WM8962_ADCR_RETUNE_C23_1:
  1062. case WM8962_ADCR_RETUNE_C23_0:
  1063. case WM8962_ADCR_RETUNE_C24_1:
  1064. case WM8962_ADCR_RETUNE_C24_0:
  1065. case WM8962_ADCR_RETUNE_C25_1:
  1066. case WM8962_ADCR_RETUNE_C25_0:
  1067. case WM8962_ADCR_RETUNE_C26_1:
  1068. case WM8962_ADCR_RETUNE_C26_0:
  1069. case WM8962_ADCR_RETUNE_C27_1:
  1070. case WM8962_ADCR_RETUNE_C27_0:
  1071. case WM8962_ADCR_RETUNE_C28_1:
  1072. case WM8962_ADCR_RETUNE_C28_0:
  1073. case WM8962_ADCR_RETUNE_C29_1:
  1074. case WM8962_ADCR_RETUNE_C29_0:
  1075. case WM8962_ADCR_RETUNE_C30_1:
  1076. case WM8962_ADCR_RETUNE_C30_0:
  1077. case WM8962_ADCR_RETUNE_C31_1:
  1078. case WM8962_ADCR_RETUNE_C31_0:
  1079. case WM8962_ADCR_RETUNE_C32_1:
  1080. case WM8962_ADCR_RETUNE_C32_0:
  1081. case WM8962_DACL_RETUNE_C1_1:
  1082. case WM8962_DACL_RETUNE_C1_0:
  1083. case WM8962_DACL_RETUNE_C2_1:
  1084. case WM8962_DACL_RETUNE_C2_0:
  1085. case WM8962_DACL_RETUNE_C3_1:
  1086. case WM8962_DACL_RETUNE_C3_0:
  1087. case WM8962_DACL_RETUNE_C4_1:
  1088. case WM8962_DACL_RETUNE_C4_0:
  1089. case WM8962_DACL_RETUNE_C5_1:
  1090. case WM8962_DACL_RETUNE_C5_0:
  1091. case WM8962_DACL_RETUNE_C6_1:
  1092. case WM8962_DACL_RETUNE_C6_0:
  1093. case WM8962_DACL_RETUNE_C7_1:
  1094. case WM8962_DACL_RETUNE_C7_0:
  1095. case WM8962_DACL_RETUNE_C8_1:
  1096. case WM8962_DACL_RETUNE_C8_0:
  1097. case WM8962_DACL_RETUNE_C9_1:
  1098. case WM8962_DACL_RETUNE_C9_0:
  1099. case WM8962_DACL_RETUNE_C10_1:
  1100. case WM8962_DACL_RETUNE_C10_0:
  1101. case WM8962_DACL_RETUNE_C11_1:
  1102. case WM8962_DACL_RETUNE_C11_0:
  1103. case WM8962_DACL_RETUNE_C12_1:
  1104. case WM8962_DACL_RETUNE_C12_0:
  1105. case WM8962_DACL_RETUNE_C13_1:
  1106. case WM8962_DACL_RETUNE_C13_0:
  1107. case WM8962_DACL_RETUNE_C14_1:
  1108. case WM8962_DACL_RETUNE_C14_0:
  1109. case WM8962_DACL_RETUNE_C15_1:
  1110. case WM8962_DACL_RETUNE_C15_0:
  1111. case WM8962_DACL_RETUNE_C16_1:
  1112. case WM8962_DACL_RETUNE_C16_0:
  1113. case WM8962_DACL_RETUNE_C17_1:
  1114. case WM8962_DACL_RETUNE_C17_0:
  1115. case WM8962_DACL_RETUNE_C18_1:
  1116. case WM8962_DACL_RETUNE_C18_0:
  1117. case WM8962_DACL_RETUNE_C19_1:
  1118. case WM8962_DACL_RETUNE_C19_0:
  1119. case WM8962_DACL_RETUNE_C20_1:
  1120. case WM8962_DACL_RETUNE_C20_0:
  1121. case WM8962_DACL_RETUNE_C21_1:
  1122. case WM8962_DACL_RETUNE_C21_0:
  1123. case WM8962_DACL_RETUNE_C22_1:
  1124. case WM8962_DACL_RETUNE_C22_0:
  1125. case WM8962_DACL_RETUNE_C23_1:
  1126. case WM8962_DACL_RETUNE_C23_0:
  1127. case WM8962_DACL_RETUNE_C24_1:
  1128. case WM8962_DACL_RETUNE_C24_0:
  1129. case WM8962_DACL_RETUNE_C25_1:
  1130. case WM8962_DACL_RETUNE_C25_0:
  1131. case WM8962_DACL_RETUNE_C26_1:
  1132. case WM8962_DACL_RETUNE_C26_0:
  1133. case WM8962_DACL_RETUNE_C27_1:
  1134. case WM8962_DACL_RETUNE_C27_0:
  1135. case WM8962_DACL_RETUNE_C28_1:
  1136. case WM8962_DACL_RETUNE_C28_0:
  1137. case WM8962_DACL_RETUNE_C29_1:
  1138. case WM8962_DACL_RETUNE_C29_0:
  1139. case WM8962_DACL_RETUNE_C30_1:
  1140. case WM8962_DACL_RETUNE_C30_0:
  1141. case WM8962_DACL_RETUNE_C31_1:
  1142. case WM8962_DACL_RETUNE_C31_0:
  1143. case WM8962_DACL_RETUNE_C32_1:
  1144. case WM8962_DACL_RETUNE_C32_0:
  1145. case WM8962_RETUNEDAC_PG2_1:
  1146. case WM8962_RETUNEDAC_PG2_0:
  1147. case WM8962_RETUNEDAC_PG_1:
  1148. case WM8962_RETUNEDAC_PG_0:
  1149. case WM8962_DACR_RETUNE_C1_1:
  1150. case WM8962_DACR_RETUNE_C1_0:
  1151. case WM8962_DACR_RETUNE_C2_1:
  1152. case WM8962_DACR_RETUNE_C2_0:
  1153. case WM8962_DACR_RETUNE_C3_1:
  1154. case WM8962_DACR_RETUNE_C3_0:
  1155. case WM8962_DACR_RETUNE_C4_1:
  1156. case WM8962_DACR_RETUNE_C4_0:
  1157. case WM8962_DACR_RETUNE_C5_1:
  1158. case WM8962_DACR_RETUNE_C5_0:
  1159. case WM8962_DACR_RETUNE_C6_1:
  1160. case WM8962_DACR_RETUNE_C6_0:
  1161. case WM8962_DACR_RETUNE_C7_1:
  1162. case WM8962_DACR_RETUNE_C7_0:
  1163. case WM8962_DACR_RETUNE_C8_1:
  1164. case WM8962_DACR_RETUNE_C8_0:
  1165. case WM8962_DACR_RETUNE_C9_1:
  1166. case WM8962_DACR_RETUNE_C9_0:
  1167. case WM8962_DACR_RETUNE_C10_1:
  1168. case WM8962_DACR_RETUNE_C10_0:
  1169. case WM8962_DACR_RETUNE_C11_1:
  1170. case WM8962_DACR_RETUNE_C11_0:
  1171. case WM8962_DACR_RETUNE_C12_1:
  1172. case WM8962_DACR_RETUNE_C12_0:
  1173. case WM8962_DACR_RETUNE_C13_1:
  1174. case WM8962_DACR_RETUNE_C13_0:
  1175. case WM8962_DACR_RETUNE_C14_1:
  1176. case WM8962_DACR_RETUNE_C14_0:
  1177. case WM8962_DACR_RETUNE_C15_1:
  1178. case WM8962_DACR_RETUNE_C15_0:
  1179. case WM8962_DACR_RETUNE_C16_1:
  1180. case WM8962_DACR_RETUNE_C16_0:
  1181. case WM8962_DACR_RETUNE_C17_1:
  1182. case WM8962_DACR_RETUNE_C17_0:
  1183. case WM8962_DACR_RETUNE_C18_1:
  1184. case WM8962_DACR_RETUNE_C18_0:
  1185. case WM8962_DACR_RETUNE_C19_1:
  1186. case WM8962_DACR_RETUNE_C19_0:
  1187. case WM8962_DACR_RETUNE_C20_1:
  1188. case WM8962_DACR_RETUNE_C20_0:
  1189. case WM8962_DACR_RETUNE_C21_1:
  1190. case WM8962_DACR_RETUNE_C21_0:
  1191. case WM8962_DACR_RETUNE_C22_1:
  1192. case WM8962_DACR_RETUNE_C22_0:
  1193. case WM8962_DACR_RETUNE_C23_1:
  1194. case WM8962_DACR_RETUNE_C23_0:
  1195. case WM8962_DACR_RETUNE_C24_1:
  1196. case WM8962_DACR_RETUNE_C24_0:
  1197. case WM8962_DACR_RETUNE_C25_1:
  1198. case WM8962_DACR_RETUNE_C25_0:
  1199. case WM8962_DACR_RETUNE_C26_1:
  1200. case WM8962_DACR_RETUNE_C26_0:
  1201. case WM8962_DACR_RETUNE_C27_1:
  1202. case WM8962_DACR_RETUNE_C27_0:
  1203. case WM8962_DACR_RETUNE_C28_1:
  1204. case WM8962_DACR_RETUNE_C28_0:
  1205. case WM8962_DACR_RETUNE_C29_1:
  1206. case WM8962_DACR_RETUNE_C29_0:
  1207. case WM8962_DACR_RETUNE_C30_1:
  1208. case WM8962_DACR_RETUNE_C30_0:
  1209. case WM8962_DACR_RETUNE_C31_1:
  1210. case WM8962_DACR_RETUNE_C31_0:
  1211. case WM8962_DACR_RETUNE_C32_1:
  1212. case WM8962_DACR_RETUNE_C32_0:
  1213. case WM8962_VSS_XHD2_1:
  1214. case WM8962_VSS_XHD2_0:
  1215. case WM8962_VSS_XHD3_1:
  1216. case WM8962_VSS_XHD3_0:
  1217. case WM8962_VSS_XHN1_1:
  1218. case WM8962_VSS_XHN1_0:
  1219. case WM8962_VSS_XHN2_1:
  1220. case WM8962_VSS_XHN2_0:
  1221. case WM8962_VSS_XHN3_1:
  1222. case WM8962_VSS_XHN3_0:
  1223. case WM8962_VSS_XLA_1:
  1224. case WM8962_VSS_XLA_0:
  1225. case WM8962_VSS_XLB_1:
  1226. case WM8962_VSS_XLB_0:
  1227. case WM8962_VSS_XLG_1:
  1228. case WM8962_VSS_XLG_0:
  1229. case WM8962_VSS_PG2_1:
  1230. case WM8962_VSS_PG2_0:
  1231. case WM8962_VSS_PG_1:
  1232. case WM8962_VSS_PG_0:
  1233. case WM8962_VSS_XTD1_1:
  1234. case WM8962_VSS_XTD1_0:
  1235. case WM8962_VSS_XTD2_1:
  1236. case WM8962_VSS_XTD2_0:
  1237. case WM8962_VSS_XTD3_1:
  1238. case WM8962_VSS_XTD3_0:
  1239. case WM8962_VSS_XTD4_1:
  1240. case WM8962_VSS_XTD4_0:
  1241. case WM8962_VSS_XTD5_1:
  1242. case WM8962_VSS_XTD5_0:
  1243. case WM8962_VSS_XTD6_1:
  1244. case WM8962_VSS_XTD6_0:
  1245. case WM8962_VSS_XTD7_1:
  1246. case WM8962_VSS_XTD7_0:
  1247. case WM8962_VSS_XTD8_1:
  1248. case WM8962_VSS_XTD8_0:
  1249. case WM8962_VSS_XTD9_1:
  1250. case WM8962_VSS_XTD9_0:
  1251. case WM8962_VSS_XTD10_1:
  1252. case WM8962_VSS_XTD10_0:
  1253. case WM8962_VSS_XTD11_1:
  1254. case WM8962_VSS_XTD11_0:
  1255. case WM8962_VSS_XTD12_1:
  1256. case WM8962_VSS_XTD12_0:
  1257. case WM8962_VSS_XTD13_1:
  1258. case WM8962_VSS_XTD13_0:
  1259. case WM8962_VSS_XTD14_1:
  1260. case WM8962_VSS_XTD14_0:
  1261. case WM8962_VSS_XTD15_1:
  1262. case WM8962_VSS_XTD15_0:
  1263. case WM8962_VSS_XTD16_1:
  1264. case WM8962_VSS_XTD16_0:
  1265. case WM8962_VSS_XTD17_1:
  1266. case WM8962_VSS_XTD17_0:
  1267. case WM8962_VSS_XTD18_1:
  1268. case WM8962_VSS_XTD18_0:
  1269. case WM8962_VSS_XTD19_1:
  1270. case WM8962_VSS_XTD19_0:
  1271. case WM8962_VSS_XTD20_1:
  1272. case WM8962_VSS_XTD20_0:
  1273. case WM8962_VSS_XTD21_1:
  1274. case WM8962_VSS_XTD21_0:
  1275. case WM8962_VSS_XTD22_1:
  1276. case WM8962_VSS_XTD22_0:
  1277. case WM8962_VSS_XTD23_1:
  1278. case WM8962_VSS_XTD23_0:
  1279. case WM8962_VSS_XTD24_1:
  1280. case WM8962_VSS_XTD24_0:
  1281. case WM8962_VSS_XTD25_1:
  1282. case WM8962_VSS_XTD25_0:
  1283. case WM8962_VSS_XTD26_1:
  1284. case WM8962_VSS_XTD26_0:
  1285. case WM8962_VSS_XTD27_1:
  1286. case WM8962_VSS_XTD27_0:
  1287. case WM8962_VSS_XTD28_1:
  1288. case WM8962_VSS_XTD28_0:
  1289. case WM8962_VSS_XTD29_1:
  1290. case WM8962_VSS_XTD29_0:
  1291. case WM8962_VSS_XTD30_1:
  1292. case WM8962_VSS_XTD30_0:
  1293. case WM8962_VSS_XTD31_1:
  1294. case WM8962_VSS_XTD31_0:
  1295. case WM8962_VSS_XTD32_1:
  1296. case WM8962_VSS_XTD32_0:
  1297. case WM8962_VSS_XTS1_1:
  1298. case WM8962_VSS_XTS1_0:
  1299. case WM8962_VSS_XTS2_1:
  1300. case WM8962_VSS_XTS2_0:
  1301. case WM8962_VSS_XTS3_1:
  1302. case WM8962_VSS_XTS3_0:
  1303. case WM8962_VSS_XTS4_1:
  1304. case WM8962_VSS_XTS4_0:
  1305. case WM8962_VSS_XTS5_1:
  1306. case WM8962_VSS_XTS5_0:
  1307. case WM8962_VSS_XTS6_1:
  1308. case WM8962_VSS_XTS6_0:
  1309. case WM8962_VSS_XTS7_1:
  1310. case WM8962_VSS_XTS7_0:
  1311. case WM8962_VSS_XTS8_1:
  1312. case WM8962_VSS_XTS8_0:
  1313. case WM8962_VSS_XTS9_1:
  1314. case WM8962_VSS_XTS9_0:
  1315. case WM8962_VSS_XTS10_1:
  1316. case WM8962_VSS_XTS10_0:
  1317. case WM8962_VSS_XTS11_1:
  1318. case WM8962_VSS_XTS11_0:
  1319. case WM8962_VSS_XTS12_1:
  1320. case WM8962_VSS_XTS12_0:
  1321. case WM8962_VSS_XTS13_1:
  1322. case WM8962_VSS_XTS13_0:
  1323. case WM8962_VSS_XTS14_1:
  1324. case WM8962_VSS_XTS14_0:
  1325. case WM8962_VSS_XTS15_1:
  1326. case WM8962_VSS_XTS15_0:
  1327. case WM8962_VSS_XTS16_1:
  1328. case WM8962_VSS_XTS16_0:
  1329. case WM8962_VSS_XTS17_1:
  1330. case WM8962_VSS_XTS17_0:
  1331. case WM8962_VSS_XTS18_1:
  1332. case WM8962_VSS_XTS18_0:
  1333. case WM8962_VSS_XTS19_1:
  1334. case WM8962_VSS_XTS19_0:
  1335. case WM8962_VSS_XTS20_1:
  1336. case WM8962_VSS_XTS20_0:
  1337. case WM8962_VSS_XTS21_1:
  1338. case WM8962_VSS_XTS21_0:
  1339. case WM8962_VSS_XTS22_1:
  1340. case WM8962_VSS_XTS22_0:
  1341. case WM8962_VSS_XTS23_1:
  1342. case WM8962_VSS_XTS23_0:
  1343. case WM8962_VSS_XTS24_1:
  1344. case WM8962_VSS_XTS24_0:
  1345. case WM8962_VSS_XTS25_1:
  1346. case WM8962_VSS_XTS25_0:
  1347. case WM8962_VSS_XTS26_1:
  1348. case WM8962_VSS_XTS26_0:
  1349. case WM8962_VSS_XTS27_1:
  1350. case WM8962_VSS_XTS27_0:
  1351. case WM8962_VSS_XTS28_1:
  1352. case WM8962_VSS_XTS28_0:
  1353. case WM8962_VSS_XTS29_1:
  1354. case WM8962_VSS_XTS29_0:
  1355. case WM8962_VSS_XTS30_1:
  1356. case WM8962_VSS_XTS30_0:
  1357. case WM8962_VSS_XTS31_1:
  1358. case WM8962_VSS_XTS31_0:
  1359. case WM8962_VSS_XTS32_1:
  1360. case WM8962_VSS_XTS32_0:
  1361. return true;
  1362. default:
  1363. return false;
  1364. }
  1365. }
  1366. static int wm8962_reset(struct wm8962_priv *wm8962)
  1367. {
  1368. int ret;
  1369. ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
  1370. if (ret != 0)
  1371. return ret;
  1372. return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
  1373. }
  1374. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
  1375. static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
  1376. static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
  1377. 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
  1378. 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
  1379. 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
  1380. 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
  1381. 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
  1382. );
  1383. static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
  1384. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  1385. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  1386. static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
  1387. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  1388. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  1389. static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
  1390. static const DECLARE_TLV_DB_RANGE(classd_tlv,
  1391. 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
  1392. 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
  1393. );
  1394. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  1395. static int wm8962_dsp2_write_config(struct snd_soc_component *component)
  1396. {
  1397. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  1398. return regcache_sync_region(wm8962->regmap,
  1399. WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
  1400. }
  1401. static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
  1402. {
  1403. u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
  1404. u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
  1405. u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
  1406. /* Mute the ADCs and DACs */
  1407. snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
  1408. snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
  1409. snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
  1410. WM8962_DAC_MUTE, WM8962_DAC_MUTE);
  1411. snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
  1412. /* Restore the ADCs and DACs */
  1413. snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
  1414. snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
  1415. snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
  1416. WM8962_DAC_MUTE, dac);
  1417. return 0;
  1418. }
  1419. static int wm8962_dsp2_start(struct snd_soc_component *component)
  1420. {
  1421. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  1422. wm8962_dsp2_write_config(component);
  1423. snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
  1424. wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
  1425. return 0;
  1426. }
  1427. static int wm8962_dsp2_stop(struct snd_soc_component *component)
  1428. {
  1429. wm8962_dsp2_set_enable(component, 0);
  1430. snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
  1431. return 0;
  1432. }
  1433. #define WM8962_DSP2_ENABLE(xname, xshift) \
  1434. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1435. .info = wm8962_dsp2_ena_info, \
  1436. .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
  1437. .private_value = xshift }
  1438. static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
  1439. struct snd_ctl_elem_info *uinfo)
  1440. {
  1441. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1442. uinfo->count = 1;
  1443. uinfo->value.integer.min = 0;
  1444. uinfo->value.integer.max = 1;
  1445. return 0;
  1446. }
  1447. static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
  1448. struct snd_ctl_elem_value *ucontrol)
  1449. {
  1450. int shift = kcontrol->private_value;
  1451. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1452. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  1453. ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
  1454. return 0;
  1455. }
  1456. static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
  1457. struct snd_ctl_elem_value *ucontrol)
  1458. {
  1459. int shift = kcontrol->private_value;
  1460. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1461. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  1462. int old = wm8962->dsp2_ena;
  1463. int ret = 0;
  1464. int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
  1465. WM8962_DSP2_ENA;
  1466. mutex_lock(&wm8962->dsp2_ena_lock);
  1467. if (ucontrol->value.integer.value[0])
  1468. wm8962->dsp2_ena |= 1 << shift;
  1469. else
  1470. wm8962->dsp2_ena &= ~(1 << shift);
  1471. if (wm8962->dsp2_ena == old)
  1472. goto out;
  1473. ret = 1;
  1474. if (dsp2_running) {
  1475. if (wm8962->dsp2_ena)
  1476. wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
  1477. else
  1478. wm8962_dsp2_stop(component);
  1479. }
  1480. out:
  1481. mutex_unlock(&wm8962->dsp2_ena_lock);
  1482. return ret;
  1483. }
  1484. /* The VU bits for the headphones are in a different register to the mute
  1485. * bits and only take effect on the PGA if it is actually powered.
  1486. */
  1487. static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
  1488. struct snd_ctl_elem_value *ucontrol)
  1489. {
  1490. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1491. int ret;
  1492. /* Apply the update (if any) */
  1493. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  1494. if (ret == 0)
  1495. return 0;
  1496. /* If the left PGA is enabled hit that VU bit... */
  1497. ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
  1498. if (ret & WM8962_HPOUTL_PGA_ENA) {
  1499. snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
  1500. snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
  1501. return 1;
  1502. }
  1503. /* ...otherwise the right. The VU is stereo. */
  1504. if (ret & WM8962_HPOUTR_PGA_ENA)
  1505. snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
  1506. snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
  1507. return 1;
  1508. }
  1509. /* The VU bits for the speakers are in a different register to the mute
  1510. * bits and only take effect on the PGA if it is actually powered.
  1511. */
  1512. static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
  1513. struct snd_ctl_elem_value *ucontrol)
  1514. {
  1515. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  1516. int ret;
  1517. /* Apply the update (if any) */
  1518. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  1519. if (ret == 0)
  1520. return 0;
  1521. /* If the left PGA is enabled hit that VU bit... */
  1522. ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
  1523. if (ret & WM8962_SPKOUTL_PGA_ENA) {
  1524. snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
  1525. snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
  1526. return 1;
  1527. }
  1528. /* ...otherwise the right. The VU is stereo. */
  1529. if (ret & WM8962_SPKOUTR_PGA_ENA)
  1530. snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
  1531. snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
  1532. return 1;
  1533. }
  1534. static const char *cap_hpf_mode_text[] = {
  1535. "Hi-fi", "Application"
  1536. };
  1537. static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
  1538. WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
  1539. static const char *cap_lhpf_mode_text[] = {
  1540. "LPF", "HPF"
  1541. };
  1542. static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
  1543. WM8962_LHPF1, 1, cap_lhpf_mode_text);
  1544. static const struct snd_kcontrol_new wm8962_snd_controls[] = {
  1545. SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
  1546. SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
  1547. mixin_tlv),
  1548. SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
  1549. mixinpga_tlv),
  1550. SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
  1551. mixin_tlv),
  1552. SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
  1553. mixin_tlv),
  1554. SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
  1555. mixinpga_tlv),
  1556. SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
  1557. mixin_tlv),
  1558. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
  1559. WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
  1560. SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
  1561. WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
  1562. SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
  1563. WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
  1564. SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
  1565. WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
  1566. SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
  1567. SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
  1568. SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
  1569. SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
  1570. SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
  1571. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
  1572. WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
  1573. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
  1574. WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
  1575. SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
  1576. SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
  1577. SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
  1578. SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
  1579. SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
  1580. SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
  1581. 5, 1, 0),
  1582. SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
  1583. SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
  1584. WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
  1585. SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
  1586. snd_soc_get_volsw, wm8962_put_hp_sw),
  1587. SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
  1588. 7, 1, 0),
  1589. SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
  1590. hp_tlv),
  1591. SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
  1592. WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
  1593. SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
  1594. 3, 7, 0, bypass_tlv),
  1595. SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
  1596. 0, 7, 0, bypass_tlv),
  1597. SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
  1598. 7, 1, 1, inmix_tlv),
  1599. SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
  1600. 6, 1, 1, inmix_tlv),
  1601. SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
  1602. 3, 7, 0, bypass_tlv),
  1603. SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
  1604. 0, 7, 0, bypass_tlv),
  1605. SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
  1606. 7, 1, 1, inmix_tlv),
  1607. SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
  1608. 6, 1, 1, inmix_tlv),
  1609. SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
  1610. classd_tlv),
  1611. SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
  1612. SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
  1613. WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
  1614. SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
  1615. WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
  1616. SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
  1617. WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
  1618. SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
  1619. WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
  1620. SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
  1621. WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
  1622. SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
  1623. SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
  1624. SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
  1625. SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
  1626. SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
  1627. SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
  1628. SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
  1629. SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
  1630. WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
  1631. SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
  1632. WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
  1633. WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
  1634. SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
  1635. WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
  1636. SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
  1637. SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
  1638. WM8962_ALCR_ENA_SHIFT, 1, 0),
  1639. SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
  1640. WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
  1641. };
  1642. static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
  1643. SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
  1644. SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
  1645. snd_soc_get_volsw, wm8962_put_spk_sw),
  1646. SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
  1647. SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
  1648. SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  1649. 3, 7, 0, bypass_tlv),
  1650. SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  1651. 0, 7, 0, bypass_tlv),
  1652. SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  1653. 7, 1, 1, inmix_tlv),
  1654. SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  1655. 6, 1, 1, inmix_tlv),
  1656. SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  1657. 7, 1, 0, inmix_tlv),
  1658. SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  1659. 6, 1, 0, inmix_tlv),
  1660. };
  1661. static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
  1662. SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
  1663. WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
  1664. SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
  1665. snd_soc_get_volsw, wm8962_put_spk_sw),
  1666. SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
  1667. 7, 1, 0),
  1668. SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
  1669. WM8962_SPEAKER_MIXER_4, 8, 1, 1),
  1670. SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  1671. 3, 7, 0, bypass_tlv),
  1672. SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  1673. 0, 7, 0, bypass_tlv),
  1674. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  1675. 7, 1, 1, inmix_tlv),
  1676. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  1677. 6, 1, 1, inmix_tlv),
  1678. SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  1679. 7, 1, 0, inmix_tlv),
  1680. SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  1681. 6, 1, 0, inmix_tlv),
  1682. SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
  1683. 3, 7, 0, bypass_tlv),
  1684. SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
  1685. 0, 7, 0, bypass_tlv),
  1686. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
  1687. 7, 1, 1, inmix_tlv),
  1688. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
  1689. 6, 1, 1, inmix_tlv),
  1690. SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  1691. 5, 1, 0, inmix_tlv),
  1692. SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  1693. 4, 1, 0, inmix_tlv),
  1694. };
  1695. static int tp_event(struct snd_soc_dapm_widget *w,
  1696. struct snd_kcontrol *kcontrol, int event)
  1697. {
  1698. int ret, reg, val, mask;
  1699. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1700. ret = pm_runtime_resume_and_get(component->dev);
  1701. if (ret < 0) {
  1702. dev_err(component->dev, "Failed to resume device: %d\n", ret);
  1703. return ret;
  1704. }
  1705. reg = WM8962_ADDITIONAL_CONTROL_4;
  1706. if (!strcmp(w->name, "TEMP_HP")) {
  1707. mask = WM8962_TEMP_ENA_HP_MASK;
  1708. val = WM8962_TEMP_ENA_HP;
  1709. } else if (!strcmp(w->name, "TEMP_SPK")) {
  1710. mask = WM8962_TEMP_ENA_SPK_MASK;
  1711. val = WM8962_TEMP_ENA_SPK;
  1712. } else {
  1713. pm_runtime_put(component->dev);
  1714. return -EINVAL;
  1715. }
  1716. switch (event) {
  1717. case SND_SOC_DAPM_POST_PMD:
  1718. val = 0;
  1719. fallthrough;
  1720. case SND_SOC_DAPM_POST_PMU:
  1721. ret = snd_soc_component_update_bits(component, reg, mask, val);
  1722. break;
  1723. default:
  1724. WARN(1, "Invalid event %d\n", event);
  1725. pm_runtime_put(component->dev);
  1726. return -EINVAL;
  1727. }
  1728. pm_runtime_put(component->dev);
  1729. return 0;
  1730. }
  1731. static int cp_event(struct snd_soc_dapm_widget *w,
  1732. struct snd_kcontrol *kcontrol, int event)
  1733. {
  1734. switch (event) {
  1735. case SND_SOC_DAPM_POST_PMU:
  1736. msleep(5);
  1737. break;
  1738. default:
  1739. WARN(1, "Invalid event %d\n", event);
  1740. return -EINVAL;
  1741. }
  1742. return 0;
  1743. }
  1744. static int hp_event(struct snd_soc_dapm_widget *w,
  1745. struct snd_kcontrol *kcontrol, int event)
  1746. {
  1747. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1748. int timeout;
  1749. int reg;
  1750. int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
  1751. WM8962_DCS_STARTUP_DONE_HP1R);
  1752. switch (event) {
  1753. case SND_SOC_DAPM_POST_PMU:
  1754. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1755. WM8962_HP1L_ENA | WM8962_HP1R_ENA,
  1756. WM8962_HP1L_ENA | WM8962_HP1R_ENA);
  1757. udelay(20);
  1758. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1759. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
  1760. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
  1761. /* Start the DC servo */
  1762. snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
  1763. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  1764. WM8962_HP1L_DCS_STARTUP |
  1765. WM8962_HP1R_DCS_STARTUP,
  1766. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  1767. WM8962_HP1L_DCS_STARTUP |
  1768. WM8962_HP1R_DCS_STARTUP);
  1769. /* Wait for it to complete, should be well under 100ms */
  1770. timeout = 0;
  1771. do {
  1772. msleep(1);
  1773. reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
  1774. if (reg < 0) {
  1775. dev_err(component->dev,
  1776. "Failed to read DCS status: %d\n",
  1777. reg);
  1778. continue;
  1779. }
  1780. dev_dbg(component->dev, "DCS status: %x\n", reg);
  1781. } while (++timeout < 200 && (reg & expected) != expected);
  1782. if ((reg & expected) != expected)
  1783. dev_err(component->dev, "DC servo timed out\n");
  1784. else
  1785. dev_dbg(component->dev, "DC servo complete after %dms\n",
  1786. timeout);
  1787. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1788. WM8962_HP1L_ENA_OUTP |
  1789. WM8962_HP1R_ENA_OUTP,
  1790. WM8962_HP1L_ENA_OUTP |
  1791. WM8962_HP1R_ENA_OUTP);
  1792. udelay(20);
  1793. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1794. WM8962_HP1L_RMV_SHORT |
  1795. WM8962_HP1R_RMV_SHORT,
  1796. WM8962_HP1L_RMV_SHORT |
  1797. WM8962_HP1R_RMV_SHORT);
  1798. break;
  1799. case SND_SOC_DAPM_PRE_PMD:
  1800. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1801. WM8962_HP1L_RMV_SHORT |
  1802. WM8962_HP1R_RMV_SHORT, 0);
  1803. udelay(20);
  1804. snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
  1805. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  1806. WM8962_HP1L_DCS_STARTUP |
  1807. WM8962_HP1R_DCS_STARTUP,
  1808. 0);
  1809. snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
  1810. WM8962_HP1L_ENA | WM8962_HP1R_ENA |
  1811. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
  1812. WM8962_HP1L_ENA_OUTP |
  1813. WM8962_HP1R_ENA_OUTP, 0);
  1814. break;
  1815. default:
  1816. WARN(1, "Invalid event %d\n", event);
  1817. return -EINVAL;
  1818. }
  1819. return 0;
  1820. }
  1821. /* VU bits for the output PGAs only take effect while the PGA is powered */
  1822. static int out_pga_event(struct snd_soc_dapm_widget *w,
  1823. struct snd_kcontrol *kcontrol, int event)
  1824. {
  1825. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1826. int reg;
  1827. switch (w->shift) {
  1828. case WM8962_HPOUTR_PGA_ENA_SHIFT:
  1829. reg = WM8962_HPOUTR_VOLUME;
  1830. break;
  1831. case WM8962_HPOUTL_PGA_ENA_SHIFT:
  1832. reg = WM8962_HPOUTL_VOLUME;
  1833. break;
  1834. case WM8962_SPKOUTR_PGA_ENA_SHIFT:
  1835. reg = WM8962_SPKOUTR_VOLUME;
  1836. break;
  1837. case WM8962_SPKOUTL_PGA_ENA_SHIFT:
  1838. reg = WM8962_SPKOUTL_VOLUME;
  1839. break;
  1840. default:
  1841. WARN(1, "Invalid shift %d\n", w->shift);
  1842. return -EINVAL;
  1843. }
  1844. switch (event) {
  1845. case SND_SOC_DAPM_POST_PMU:
  1846. return snd_soc_component_write(component, reg,
  1847. snd_soc_component_read(component, reg));
  1848. default:
  1849. WARN(1, "Invalid event %d\n", event);
  1850. return -EINVAL;
  1851. }
  1852. }
  1853. static int dsp2_event(struct snd_soc_dapm_widget *w,
  1854. struct snd_kcontrol *kcontrol, int event)
  1855. {
  1856. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1857. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  1858. switch (event) {
  1859. case SND_SOC_DAPM_POST_PMU:
  1860. if (wm8962->dsp2_ena)
  1861. wm8962_dsp2_start(component);
  1862. break;
  1863. case SND_SOC_DAPM_PRE_PMD:
  1864. if (wm8962->dsp2_ena)
  1865. wm8962_dsp2_stop(component);
  1866. break;
  1867. default:
  1868. WARN(1, "Invalid event %d\n", event);
  1869. return -EINVAL;
  1870. }
  1871. return 0;
  1872. }
  1873. static const char *st_text[] = { "None", "Left", "Right" };
  1874. static SOC_ENUM_SINGLE_DECL(str_enum,
  1875. WM8962_DAC_DSP_MIXING_1, 2, st_text);
  1876. static const struct snd_kcontrol_new str_mux =
  1877. SOC_DAPM_ENUM("Right Sidetone", str_enum);
  1878. static SOC_ENUM_SINGLE_DECL(stl_enum,
  1879. WM8962_DAC_DSP_MIXING_2, 2, st_text);
  1880. static const struct snd_kcontrol_new stl_mux =
  1881. SOC_DAPM_ENUM("Left Sidetone", stl_enum);
  1882. static const char *outmux_text[] = { "DAC", "Mixer" };
  1883. static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
  1884. WM8962_SPEAKER_MIXER_2, 7, outmux_text);
  1885. static const struct snd_kcontrol_new spkoutr_mux =
  1886. SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
  1887. static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
  1888. WM8962_SPEAKER_MIXER_1, 7, outmux_text);
  1889. static const struct snd_kcontrol_new spkoutl_mux =
  1890. SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
  1891. static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
  1892. WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
  1893. static const struct snd_kcontrol_new hpoutr_mux =
  1894. SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
  1895. static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
  1896. WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
  1897. static const struct snd_kcontrol_new hpoutl_mux =
  1898. SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
  1899. static const char * const input_mode_text[] = { "Analog", "Digital" };
  1900. static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text);
  1901. static const struct snd_kcontrol_new input_mode_mux =
  1902. SOC_DAPM_ENUM("Input Mode", input_mode_enum);
  1903. static const struct snd_kcontrol_new inpgal[] = {
  1904. SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
  1905. SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
  1906. SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
  1907. SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
  1908. };
  1909. static const struct snd_kcontrol_new inpgar[] = {
  1910. SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
  1911. SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
  1912. SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
  1913. SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
  1914. };
  1915. static const struct snd_kcontrol_new mixinl[] = {
  1916. SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
  1917. SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
  1918. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
  1919. };
  1920. static const struct snd_kcontrol_new mixinr[] = {
  1921. SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
  1922. SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
  1923. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
  1924. };
  1925. static const struct snd_kcontrol_new hpmixl[] = {
  1926. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
  1927. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
  1928. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
  1929. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
  1930. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
  1931. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
  1932. };
  1933. static const struct snd_kcontrol_new hpmixr[] = {
  1934. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
  1935. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
  1936. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
  1937. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
  1938. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
  1939. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
  1940. };
  1941. static const struct snd_kcontrol_new spkmixl[] = {
  1942. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
  1943. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
  1944. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
  1945. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
  1946. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
  1947. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
  1948. };
  1949. static const struct snd_kcontrol_new spkmixr[] = {
  1950. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
  1951. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
  1952. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
  1953. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
  1954. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
  1955. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
  1956. };
  1957. static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
  1958. SND_SOC_DAPM_INPUT("IN1L"),
  1959. SND_SOC_DAPM_INPUT("IN1R"),
  1960. SND_SOC_DAPM_INPUT("IN2L"),
  1961. SND_SOC_DAPM_INPUT("IN2R"),
  1962. SND_SOC_DAPM_INPUT("IN3L"),
  1963. SND_SOC_DAPM_INPUT("IN3R"),
  1964. SND_SOC_DAPM_INPUT("IN4L"),
  1965. SND_SOC_DAPM_INPUT("IN4R"),
  1966. SND_SOC_DAPM_SIGGEN("Beep"),
  1967. SND_SOC_DAPM_INPUT("DMICDAT"),
  1968. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
  1969. SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
  1970. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
  1971. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
  1972. SND_SOC_DAPM_POST_PMU),
  1973. SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
  1974. SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
  1975. WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
  1976. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1977. SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event,
  1978. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1979. SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event,
  1980. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1981. SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
  1982. inpgal, ARRAY_SIZE(inpgal)),
  1983. SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
  1984. inpgar, ARRAY_SIZE(inpgar)),
  1985. SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
  1986. mixinl, ARRAY_SIZE(mixinl)),
  1987. SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
  1988. mixinr, ARRAY_SIZE(mixinr)),
  1989. SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
  1990. SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux),
  1991. SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux),
  1992. SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
  1993. SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
  1994. SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
  1995. SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
  1996. SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
  1997. SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
  1998. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  1999. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  2000. SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
  2001. hpmixl, ARRAY_SIZE(hpmixl)),
  2002. SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
  2003. hpmixr, ARRAY_SIZE(hpmixr)),
  2004. SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
  2005. out_pga_event, SND_SOC_DAPM_POST_PMU),
  2006. SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
  2007. out_pga_event, SND_SOC_DAPM_POST_PMU),
  2008. SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
  2009. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  2010. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  2011. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  2012. };
  2013. static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
  2014. SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
  2015. spkmixl, ARRAY_SIZE(spkmixl)),
  2016. SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  2017. out_pga_event, SND_SOC_DAPM_POST_PMU),
  2018. SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  2019. SND_SOC_DAPM_OUTPUT("SPKOUT"),
  2020. };
  2021. static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
  2022. SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
  2023. spkmixl, ARRAY_SIZE(spkmixl)),
  2024. SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
  2025. spkmixr, ARRAY_SIZE(spkmixr)),
  2026. SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  2027. out_pga_event, SND_SOC_DAPM_POST_PMU),
  2028. SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
  2029. out_pga_event, SND_SOC_DAPM_POST_PMU),
  2030. SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  2031. SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
  2032. SND_SOC_DAPM_OUTPUT("SPKOUTL"),
  2033. SND_SOC_DAPM_OUTPUT("SPKOUTR"),
  2034. };
  2035. static const struct snd_soc_dapm_route wm8962_intercon[] = {
  2036. { "INPGAL", "IN1L Switch", "IN1L" },
  2037. { "INPGAL", "IN2L Switch", "IN2L" },
  2038. { "INPGAL", "IN3L Switch", "IN3L" },
  2039. { "INPGAL", "IN4L Switch", "IN4L" },
  2040. { "INPGAR", "IN1R Switch", "IN1R" },
  2041. { "INPGAR", "IN2R Switch", "IN2R" },
  2042. { "INPGAR", "IN3R Switch", "IN3R" },
  2043. { "INPGAR", "IN4R Switch", "IN4R" },
  2044. { "MIXINL", "IN2L Switch", "IN2L" },
  2045. { "MIXINL", "IN3L Switch", "IN3L" },
  2046. { "MIXINL", "PGA Switch", "INPGAL" },
  2047. { "MIXINR", "IN2R Switch", "IN2R" },
  2048. { "MIXINR", "IN3R Switch", "IN3R" },
  2049. { "MIXINR", "PGA Switch", "INPGAR" },
  2050. { "MICBIAS", NULL, "SYSCLK" },
  2051. { "DMIC_ENA", NULL, "DMICDAT" },
  2052. { "Input Mode L", "Analog", "MIXINL" },
  2053. { "Input Mode L", "Digital", "DMIC_ENA" },
  2054. { "Input Mode R", "Analog", "MIXINR" },
  2055. { "Input Mode R", "Digital", "DMIC_ENA" },
  2056. { "ADCL", NULL, "SYSCLK" },
  2057. { "ADCL", NULL, "TOCLK" },
  2058. { "ADCL", NULL, "Input Mode L" },
  2059. { "ADCL", NULL, "DSP2" },
  2060. { "ADCR", NULL, "SYSCLK" },
  2061. { "ADCR", NULL, "TOCLK" },
  2062. { "ADCR", NULL, "Input Mode R" },
  2063. { "ADCR", NULL, "DSP2" },
  2064. { "STL", "Left", "ADCL" },
  2065. { "STL", "Right", "ADCR" },
  2066. { "STL", NULL, "Class G" },
  2067. { "STR", "Left", "ADCL" },
  2068. { "STR", "Right", "ADCR" },
  2069. { "STR", NULL, "Class G" },
  2070. { "DACL", NULL, "SYSCLK" },
  2071. { "DACL", NULL, "TOCLK" },
  2072. { "DACL", NULL, "Beep" },
  2073. { "DACL", NULL, "STL" },
  2074. { "DACL", NULL, "DSP2" },
  2075. { "DACR", NULL, "SYSCLK" },
  2076. { "DACR", NULL, "TOCLK" },
  2077. { "DACR", NULL, "Beep" },
  2078. { "DACR", NULL, "STR" },
  2079. { "DACR", NULL, "DSP2" },
  2080. { "HPMIXL", "IN4L Switch", "IN4L" },
  2081. { "HPMIXL", "IN4R Switch", "IN4R" },
  2082. { "HPMIXL", "DACL Switch", "DACL" },
  2083. { "HPMIXL", "DACR Switch", "DACR" },
  2084. { "HPMIXL", "MIXINL Switch", "MIXINL" },
  2085. { "HPMIXL", "MIXINR Switch", "MIXINR" },
  2086. { "HPMIXR", "IN4L Switch", "IN4L" },
  2087. { "HPMIXR", "IN4R Switch", "IN4R" },
  2088. { "HPMIXR", "DACL Switch", "DACL" },
  2089. { "HPMIXR", "DACR Switch", "DACR" },
  2090. { "HPMIXR", "MIXINL Switch", "MIXINL" },
  2091. { "HPMIXR", "MIXINR Switch", "MIXINR" },
  2092. { "Left Bypass", NULL, "HPMIXL" },
  2093. { "Left Bypass", NULL, "Class G" },
  2094. { "Right Bypass", NULL, "HPMIXR" },
  2095. { "Right Bypass", NULL, "Class G" },
  2096. { "HPOUTL PGA", "Mixer", "Left Bypass" },
  2097. { "HPOUTL PGA", "DAC", "DACL" },
  2098. { "HPOUTR PGA", "Mixer", "Right Bypass" },
  2099. { "HPOUTR PGA", "DAC", "DACR" },
  2100. { "HPOUT", NULL, "HPOUTL PGA" },
  2101. { "HPOUT", NULL, "HPOUTR PGA" },
  2102. { "HPOUT", NULL, "Charge Pump" },
  2103. { "HPOUT", NULL, "SYSCLK" },
  2104. { "HPOUT", NULL, "TOCLK" },
  2105. { "HPOUTL", NULL, "HPOUT" },
  2106. { "HPOUTR", NULL, "HPOUT" },
  2107. { "HPOUTL", NULL, "TEMP_HP" },
  2108. { "HPOUTR", NULL, "TEMP_HP" },
  2109. };
  2110. static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
  2111. { "Speaker Mixer", "IN4L Switch", "IN4L" },
  2112. { "Speaker Mixer", "IN4R Switch", "IN4R" },
  2113. { "Speaker Mixer", "DACL Switch", "DACL" },
  2114. { "Speaker Mixer", "DACR Switch", "DACR" },
  2115. { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
  2116. { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
  2117. { "Speaker PGA", "Mixer", "Speaker Mixer" },
  2118. { "Speaker PGA", "DAC", "DACL" },
  2119. { "Speaker Output", NULL, "Speaker PGA" },
  2120. { "Speaker Output", NULL, "SYSCLK" },
  2121. { "Speaker Output", NULL, "TOCLK" },
  2122. { "Speaker Output", NULL, "TEMP_SPK" },
  2123. { "SPKOUT", NULL, "Speaker Output" },
  2124. };
  2125. static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
  2126. { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
  2127. { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
  2128. { "SPKOUTL Mixer", "DACL Switch", "DACL" },
  2129. { "SPKOUTL Mixer", "DACR Switch", "DACR" },
  2130. { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
  2131. { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
  2132. { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
  2133. { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
  2134. { "SPKOUTR Mixer", "DACL Switch", "DACL" },
  2135. { "SPKOUTR Mixer", "DACR Switch", "DACR" },
  2136. { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
  2137. { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
  2138. { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
  2139. { "SPKOUTL PGA", "DAC", "DACL" },
  2140. { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
  2141. { "SPKOUTR PGA", "DAC", "DACR" },
  2142. { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
  2143. { "SPKOUTL Output", NULL, "SYSCLK" },
  2144. { "SPKOUTL Output", NULL, "TOCLK" },
  2145. { "SPKOUTL Output", NULL, "TEMP_SPK" },
  2146. { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
  2147. { "SPKOUTR Output", NULL, "SYSCLK" },
  2148. { "SPKOUTR Output", NULL, "TOCLK" },
  2149. { "SPKOUTR Output", NULL, "TEMP_SPK" },
  2150. { "SPKOUTL", NULL, "SPKOUTL Output" },
  2151. { "SPKOUTR", NULL, "SPKOUTR Output" },
  2152. };
  2153. static int wm8962_add_widgets(struct snd_soc_component *component)
  2154. {
  2155. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2156. struct wm8962_pdata *pdata = &wm8962->pdata;
  2157. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2158. snd_soc_add_component_controls(component, wm8962_snd_controls,
  2159. ARRAY_SIZE(wm8962_snd_controls));
  2160. if (pdata->spk_mono)
  2161. snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
  2162. ARRAY_SIZE(wm8962_spk_mono_controls));
  2163. else
  2164. snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
  2165. ARRAY_SIZE(wm8962_spk_stereo_controls));
  2166. snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
  2167. ARRAY_SIZE(wm8962_dapm_widgets));
  2168. if (pdata->spk_mono)
  2169. snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
  2170. ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
  2171. else
  2172. snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
  2173. ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
  2174. snd_soc_dapm_add_routes(dapm, wm8962_intercon,
  2175. ARRAY_SIZE(wm8962_intercon));
  2176. if (pdata->spk_mono)
  2177. snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
  2178. ARRAY_SIZE(wm8962_spk_mono_intercon));
  2179. else
  2180. snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
  2181. ARRAY_SIZE(wm8962_spk_stereo_intercon));
  2182. snd_soc_dapm_disable_pin(dapm, "Beep");
  2183. return 0;
  2184. }
  2185. /* -1 for reserved values */
  2186. static const int bclk_divs[] = {
  2187. 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
  2188. };
  2189. static const int sysclk_rates[] = {
  2190. 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
  2191. };
  2192. static void wm8962_configure_bclk(struct snd_soc_component *component)
  2193. {
  2194. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2195. int best, min_diff, diff;
  2196. int dspclk, i;
  2197. int clocking2 = 0;
  2198. int clocking4 = 0;
  2199. int aif2 = 0;
  2200. if (!wm8962->sysclk_rate) {
  2201. dev_dbg(component->dev, "No SYSCLK configured\n");
  2202. return;
  2203. }
  2204. if (!wm8962->bclk || !wm8962->lrclk) {
  2205. dev_dbg(component->dev, "No audio clocks configured\n");
  2206. return;
  2207. }
  2208. for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
  2209. if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
  2210. clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
  2211. break;
  2212. }
  2213. }
  2214. if (i == ARRAY_SIZE(sysclk_rates)) {
  2215. dev_err(component->dev, "Unsupported sysclk ratio %d\n",
  2216. wm8962->sysclk_rate / wm8962->lrclk);
  2217. return;
  2218. }
  2219. dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
  2220. snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
  2221. WM8962_SYSCLK_RATE_MASK, clocking4);
  2222. /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
  2223. * So we here provisionally enable it and then disable it afterward
  2224. * if current bias_level hasn't reached SND_SOC_BIAS_ON.
  2225. */
  2226. if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
  2227. snd_soc_component_update_bits(component, WM8962_CLOCKING2,
  2228. WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
  2229. /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
  2230. * correct frequency of LRCLK and BCLK. Sometimes the read-only value
  2231. * can't be updated timely after enabling SYSCLK. This results in wrong
  2232. * calculation values. Delay is introduced here to wait for newest
  2233. * value from register. The time of the delay should be at least
  2234. * 500~1000us according to test.
  2235. */
  2236. usleep_range(500, 1000);
  2237. dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
  2238. if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
  2239. snd_soc_component_update_bits(component, WM8962_CLOCKING2,
  2240. WM8962_SYSCLK_ENA_MASK, 0);
  2241. if (dspclk < 0) {
  2242. dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
  2243. return;
  2244. }
  2245. dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
  2246. switch (dspclk) {
  2247. case 0:
  2248. dspclk = wm8962->sysclk_rate;
  2249. break;
  2250. case 1:
  2251. dspclk = wm8962->sysclk_rate / 2;
  2252. break;
  2253. case 2:
  2254. dspclk = wm8962->sysclk_rate / 4;
  2255. break;
  2256. default:
  2257. dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
  2258. dspclk = wm8962->sysclk_rate;
  2259. }
  2260. dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
  2261. /* Search a proper bclk, not exact match. */
  2262. best = 0;
  2263. min_diff = INT_MAX;
  2264. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  2265. if (bclk_divs[i] < 0)
  2266. continue;
  2267. diff = (dspclk / bclk_divs[i]) - wm8962->bclk;
  2268. if (diff < 0) /* Table is sorted */
  2269. break;
  2270. if (diff < min_diff) {
  2271. best = i;
  2272. min_diff = diff;
  2273. }
  2274. }
  2275. wm8962->bclk = dspclk / bclk_divs[best];
  2276. clocking2 |= best;
  2277. dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
  2278. bclk_divs[best], wm8962->bclk);
  2279. aif2 |= wm8962->bclk / wm8962->lrclk;
  2280. dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
  2281. wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
  2282. snd_soc_component_update_bits(component, WM8962_CLOCKING2,
  2283. WM8962_BCLK_DIV_MASK, clocking2);
  2284. snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
  2285. WM8962_AIF_RATE_MASK, aif2);
  2286. }
  2287. static int wm8962_set_bias_level(struct snd_soc_component *component,
  2288. enum snd_soc_bias_level level)
  2289. {
  2290. switch (level) {
  2291. case SND_SOC_BIAS_ON:
  2292. break;
  2293. case SND_SOC_BIAS_PREPARE:
  2294. /* VMID 2*50k */
  2295. snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
  2296. WM8962_VMID_SEL_MASK, 0x80);
  2297. wm8962_configure_bclk(component);
  2298. break;
  2299. case SND_SOC_BIAS_STANDBY:
  2300. /* VMID 2*250k */
  2301. snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
  2302. WM8962_VMID_SEL_MASK, 0x100);
  2303. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  2304. msleep(100);
  2305. break;
  2306. case SND_SOC_BIAS_OFF:
  2307. break;
  2308. }
  2309. return 0;
  2310. }
  2311. static const struct {
  2312. int rate;
  2313. int reg;
  2314. } sr_vals[] = {
  2315. { 48000, 0 },
  2316. { 44100, 0 },
  2317. { 32000, 1 },
  2318. { 22050, 2 },
  2319. { 24000, 2 },
  2320. { 16000, 3 },
  2321. { 11025, 4 },
  2322. { 12000, 4 },
  2323. { 8000, 5 },
  2324. { 88200, 6 },
  2325. { 96000, 6 },
  2326. };
  2327. static int wm8962_hw_params(struct snd_pcm_substream *substream,
  2328. struct snd_pcm_hw_params *params,
  2329. struct snd_soc_dai *dai)
  2330. {
  2331. struct snd_soc_component *component = dai->component;
  2332. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2333. int i;
  2334. int aif0 = 0;
  2335. int adctl3 = 0;
  2336. wm8962->bclk = snd_soc_params_to_bclk(params);
  2337. if (params_channels(params) == 1)
  2338. wm8962->bclk *= 2;
  2339. wm8962->lrclk = params_rate(params);
  2340. for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
  2341. if (sr_vals[i].rate == wm8962->lrclk) {
  2342. adctl3 |= sr_vals[i].reg;
  2343. break;
  2344. }
  2345. }
  2346. if (i == ARRAY_SIZE(sr_vals)) {
  2347. dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
  2348. return -EINVAL;
  2349. }
  2350. if (wm8962->lrclk % 8000 == 0)
  2351. adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
  2352. switch (params_width(params)) {
  2353. case 16:
  2354. break;
  2355. case 20:
  2356. aif0 |= 0x4;
  2357. break;
  2358. case 24:
  2359. aif0 |= 0x8;
  2360. break;
  2361. case 32:
  2362. aif0 |= 0xc;
  2363. break;
  2364. default:
  2365. return -EINVAL;
  2366. }
  2367. snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
  2368. WM8962_WL_MASK, aif0);
  2369. snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
  2370. WM8962_SAMPLE_RATE_INT_MODE |
  2371. WM8962_SAMPLE_RATE_MASK, adctl3);
  2372. dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
  2373. wm8962->bclk, wm8962->lrclk);
  2374. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
  2375. wm8962_configure_bclk(component);
  2376. return 0;
  2377. }
  2378. static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  2379. unsigned int freq, int dir)
  2380. {
  2381. struct snd_soc_component *component = dai->component;
  2382. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2383. int src;
  2384. switch (clk_id) {
  2385. case WM8962_SYSCLK_MCLK:
  2386. wm8962->sysclk = WM8962_SYSCLK_MCLK;
  2387. src = 0;
  2388. break;
  2389. case WM8962_SYSCLK_FLL:
  2390. wm8962->sysclk = WM8962_SYSCLK_FLL;
  2391. src = 1 << WM8962_SYSCLK_SRC_SHIFT;
  2392. break;
  2393. default:
  2394. return -EINVAL;
  2395. }
  2396. snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
  2397. src);
  2398. wm8962->sysclk_rate = freq;
  2399. return 0;
  2400. }
  2401. static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2402. {
  2403. struct snd_soc_component *component = dai->component;
  2404. int aif0 = 0;
  2405. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2406. case SND_SOC_DAIFMT_DSP_B:
  2407. aif0 |= WM8962_LRCLK_INV | 3;
  2408. fallthrough;
  2409. case SND_SOC_DAIFMT_DSP_A:
  2410. aif0 |= 3;
  2411. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2412. case SND_SOC_DAIFMT_NB_NF:
  2413. case SND_SOC_DAIFMT_IB_NF:
  2414. break;
  2415. default:
  2416. return -EINVAL;
  2417. }
  2418. break;
  2419. case SND_SOC_DAIFMT_RIGHT_J:
  2420. break;
  2421. case SND_SOC_DAIFMT_LEFT_J:
  2422. aif0 |= 1;
  2423. break;
  2424. case SND_SOC_DAIFMT_I2S:
  2425. aif0 |= 2;
  2426. break;
  2427. default:
  2428. return -EINVAL;
  2429. }
  2430. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2431. case SND_SOC_DAIFMT_NB_NF:
  2432. break;
  2433. case SND_SOC_DAIFMT_IB_NF:
  2434. aif0 |= WM8962_BCLK_INV;
  2435. break;
  2436. case SND_SOC_DAIFMT_NB_IF:
  2437. aif0 |= WM8962_LRCLK_INV;
  2438. break;
  2439. case SND_SOC_DAIFMT_IB_IF:
  2440. aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
  2441. break;
  2442. default:
  2443. return -EINVAL;
  2444. }
  2445. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2446. case SND_SOC_DAIFMT_CBM_CFM:
  2447. aif0 |= WM8962_MSTR;
  2448. break;
  2449. case SND_SOC_DAIFMT_CBS_CFS:
  2450. break;
  2451. default:
  2452. return -EINVAL;
  2453. }
  2454. snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
  2455. WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
  2456. WM8962_LRCLK_INV, aif0);
  2457. return 0;
  2458. }
  2459. struct _fll_div {
  2460. u16 fll_fratio;
  2461. u16 fll_outdiv;
  2462. u16 fll_refclk_div;
  2463. u16 n;
  2464. u16 theta;
  2465. u16 lambda;
  2466. };
  2467. /* The size in bits of the FLL divide multiplied by 10
  2468. * to allow rounding later */
  2469. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  2470. static struct {
  2471. unsigned int min;
  2472. unsigned int max;
  2473. u16 fll_fratio;
  2474. int ratio;
  2475. } fll_fratios[] = {
  2476. { 0, 64000, 4, 16 },
  2477. { 64000, 128000, 3, 8 },
  2478. { 128000, 256000, 2, 4 },
  2479. { 256000, 1000000, 1, 2 },
  2480. { 1000000, 13500000, 0, 1 },
  2481. };
  2482. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  2483. unsigned int Fout)
  2484. {
  2485. unsigned int target;
  2486. unsigned int div;
  2487. unsigned int fratio, gcd_fll;
  2488. int i;
  2489. /* Fref must be <=13.5MHz */
  2490. div = 1;
  2491. fll_div->fll_refclk_div = 0;
  2492. while ((Fref / div) > 13500000) {
  2493. div *= 2;
  2494. fll_div->fll_refclk_div++;
  2495. if (div > 4) {
  2496. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  2497. Fref);
  2498. return -EINVAL;
  2499. }
  2500. }
  2501. pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
  2502. /* Apply the division for our remaining calculations */
  2503. Fref /= div;
  2504. /* Fvco should be 90-100MHz; don't check the upper bound */
  2505. div = 2;
  2506. while (Fout * div < 90000000) {
  2507. div++;
  2508. if (div > 64) {
  2509. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  2510. Fout);
  2511. return -EINVAL;
  2512. }
  2513. }
  2514. target = Fout * div;
  2515. fll_div->fll_outdiv = div - 1;
  2516. pr_debug("FLL Fvco=%dHz\n", target);
  2517. /* Find an appropriate FLL_FRATIO and factor it out of the target */
  2518. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  2519. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  2520. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  2521. fratio = fll_fratios[i].ratio;
  2522. break;
  2523. }
  2524. }
  2525. if (i == ARRAY_SIZE(fll_fratios)) {
  2526. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  2527. return -EINVAL;
  2528. }
  2529. fll_div->n = target / (fratio * Fref);
  2530. if (target % Fref == 0) {
  2531. fll_div->theta = 0;
  2532. fll_div->lambda = 1;
  2533. } else {
  2534. gcd_fll = gcd(target, fratio * Fref);
  2535. fll_div->theta = (target - (fll_div->n * fratio * Fref))
  2536. / gcd_fll;
  2537. fll_div->lambda = (fratio * Fref) / gcd_fll;
  2538. }
  2539. pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
  2540. fll_div->n, fll_div->theta, fll_div->lambda);
  2541. pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
  2542. fll_div->fll_fratio, fll_div->fll_outdiv,
  2543. fll_div->fll_refclk_div);
  2544. return 0;
  2545. }
  2546. static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
  2547. unsigned int Fref, unsigned int Fout)
  2548. {
  2549. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2550. struct _fll_div fll_div;
  2551. unsigned long timeout;
  2552. int ret;
  2553. int fll1 = 0;
  2554. /* Any change? */
  2555. if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
  2556. Fout == wm8962->fll_fout)
  2557. return 0;
  2558. if (Fout == 0) {
  2559. dev_dbg(component->dev, "FLL disabled\n");
  2560. wm8962->fll_fref = 0;
  2561. wm8962->fll_fout = 0;
  2562. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
  2563. WM8962_FLL_ENA, 0);
  2564. pm_runtime_put(component->dev);
  2565. return 0;
  2566. }
  2567. ret = fll_factors(&fll_div, Fref, Fout);
  2568. if (ret != 0)
  2569. return ret;
  2570. /* Parameters good, disable so we can reprogram */
  2571. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
  2572. switch (fll_id) {
  2573. case WM8962_FLL_MCLK:
  2574. case WM8962_FLL_BCLK:
  2575. case WM8962_FLL_OSC:
  2576. fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
  2577. break;
  2578. case WM8962_FLL_INT:
  2579. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
  2580. WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
  2581. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
  2582. WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
  2583. break;
  2584. default:
  2585. dev_err(component->dev, "Unknown FLL source %d\n", ret);
  2586. return -EINVAL;
  2587. }
  2588. if (fll_div.theta)
  2589. fll1 |= WM8962_FLL_FRAC;
  2590. /* Stop the FLL while we reconfigure */
  2591. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
  2592. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
  2593. WM8962_FLL_OUTDIV_MASK |
  2594. WM8962_FLL_REFCLK_DIV_MASK,
  2595. (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
  2596. (fll_div.fll_refclk_div));
  2597. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
  2598. WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
  2599. snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
  2600. snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
  2601. snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
  2602. reinit_completion(&wm8962->fll_lock);
  2603. ret = pm_runtime_resume_and_get(component->dev);
  2604. if (ret < 0) {
  2605. dev_err(component->dev, "Failed to resume device: %d\n", ret);
  2606. return ret;
  2607. }
  2608. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
  2609. WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
  2610. WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
  2611. dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  2612. /* This should be a massive overestimate but go even
  2613. * higher if we'll error out
  2614. */
  2615. if (wm8962->irq)
  2616. timeout = msecs_to_jiffies(5);
  2617. else
  2618. timeout = msecs_to_jiffies(1);
  2619. timeout = wait_for_completion_timeout(&wm8962->fll_lock,
  2620. timeout);
  2621. if (timeout == 0 && wm8962->irq) {
  2622. dev_err(component->dev, "FLL lock timed out");
  2623. snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
  2624. WM8962_FLL_ENA, 0);
  2625. pm_runtime_put(component->dev);
  2626. return -ETIMEDOUT;
  2627. }
  2628. wm8962->fll_fref = Fref;
  2629. wm8962->fll_fout = Fout;
  2630. wm8962->fll_src = source;
  2631. return 0;
  2632. }
  2633. static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
  2634. {
  2635. struct snd_soc_component *component = dai->component;
  2636. int val, ret;
  2637. if (mute)
  2638. val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
  2639. else
  2640. val = 0;
  2641. /**
  2642. * The DAC mute bit is mirrored in two registers, update both to keep
  2643. * the register cache consistent.
  2644. */
  2645. ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
  2646. WM8962_DAC_MUTE_ALT, val);
  2647. if (ret < 0)
  2648. return ret;
  2649. return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
  2650. WM8962_DAC_MUTE, val);
  2651. }
  2652. #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
  2653. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  2654. #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  2655. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2656. static const struct snd_soc_dai_ops wm8962_dai_ops = {
  2657. .hw_params = wm8962_hw_params,
  2658. .set_sysclk = wm8962_set_dai_sysclk,
  2659. .set_fmt = wm8962_set_dai_fmt,
  2660. .mute_stream = wm8962_mute,
  2661. .no_capture_mute = 1,
  2662. };
  2663. static struct snd_soc_dai_driver wm8962_dai = {
  2664. .name = "wm8962",
  2665. .playback = {
  2666. .stream_name = "Playback",
  2667. .channels_min = 1,
  2668. .channels_max = 2,
  2669. .rates = WM8962_RATES,
  2670. .formats = WM8962_FORMATS,
  2671. },
  2672. .capture = {
  2673. .stream_name = "Capture",
  2674. .channels_min = 1,
  2675. .channels_max = 2,
  2676. .rates = WM8962_RATES,
  2677. .formats = WM8962_FORMATS,
  2678. },
  2679. .ops = &wm8962_dai_ops,
  2680. .symmetric_rate = 1,
  2681. };
  2682. static void wm8962_mic_work(struct work_struct *work)
  2683. {
  2684. struct wm8962_priv *wm8962 = container_of(work,
  2685. struct wm8962_priv,
  2686. mic_work.work);
  2687. struct snd_soc_component *component = wm8962->component;
  2688. int status = 0;
  2689. int irq_pol = 0;
  2690. int reg;
  2691. reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
  2692. if (reg & WM8962_MICDET_STS) {
  2693. status |= SND_JACK_MICROPHONE;
  2694. irq_pol |= WM8962_MICD_IRQ_POL;
  2695. }
  2696. if (reg & WM8962_MICSHORT_STS) {
  2697. status |= SND_JACK_BTN_0;
  2698. irq_pol |= WM8962_MICSCD_IRQ_POL;
  2699. }
  2700. snd_soc_jack_report(wm8962->jack, status,
  2701. SND_JACK_MICROPHONE | SND_JACK_BTN_0);
  2702. snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
  2703. WM8962_MICSCD_IRQ_POL |
  2704. WM8962_MICD_IRQ_POL, irq_pol);
  2705. }
  2706. static irqreturn_t wm8962_irq(int irq, void *data)
  2707. {
  2708. struct device *dev = data;
  2709. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  2710. unsigned int mask;
  2711. unsigned int active;
  2712. int reg, ret;
  2713. ret = pm_runtime_resume_and_get(dev);
  2714. if (ret < 0) {
  2715. dev_err(dev, "Failed to resume: %d\n", ret);
  2716. return IRQ_NONE;
  2717. }
  2718. ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
  2719. &mask);
  2720. if (ret != 0) {
  2721. pm_runtime_put(dev);
  2722. dev_err(dev, "Failed to read interrupt mask: %d\n",
  2723. ret);
  2724. return IRQ_NONE;
  2725. }
  2726. ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
  2727. if (ret != 0) {
  2728. pm_runtime_put(dev);
  2729. dev_err(dev, "Failed to read interrupt: %d\n", ret);
  2730. return IRQ_NONE;
  2731. }
  2732. active &= ~mask;
  2733. if (!active) {
  2734. pm_runtime_put(dev);
  2735. return IRQ_NONE;
  2736. }
  2737. /* Acknowledge the interrupts */
  2738. ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
  2739. if (ret != 0)
  2740. dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
  2741. if (active & WM8962_FLL_LOCK_EINT) {
  2742. dev_dbg(dev, "FLL locked\n");
  2743. complete(&wm8962->fll_lock);
  2744. }
  2745. if (active & WM8962_FIFOS_ERR_EINT)
  2746. dev_err(dev, "FIFO error\n");
  2747. if (active & WM8962_TEMP_SHUT_EINT) {
  2748. dev_crit(dev, "Thermal shutdown\n");
  2749. ret = regmap_read(wm8962->regmap,
  2750. WM8962_THERMAL_SHUTDOWN_STATUS, &reg);
  2751. if (ret != 0) {
  2752. dev_warn(dev, "Failed to read thermal status: %d\n",
  2753. ret);
  2754. reg = 0;
  2755. }
  2756. if (reg & WM8962_TEMP_ERR_HP)
  2757. dev_crit(dev, "Headphone thermal error\n");
  2758. if (reg & WM8962_TEMP_WARN_HP)
  2759. dev_crit(dev, "Headphone thermal warning\n");
  2760. if (reg & WM8962_TEMP_ERR_SPK)
  2761. dev_crit(dev, "Speaker thermal error\n");
  2762. if (reg & WM8962_TEMP_WARN_SPK)
  2763. dev_crit(dev, "Speaker thermal warning\n");
  2764. }
  2765. if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
  2766. dev_dbg(dev, "Microphone event detected\n");
  2767. #ifndef CONFIG_SND_SOC_WM8962_MODULE
  2768. trace_snd_soc_jack_irq(dev_name(dev));
  2769. #endif
  2770. pm_wakeup_event(dev, 300);
  2771. queue_delayed_work(system_power_efficient_wq,
  2772. &wm8962->mic_work,
  2773. msecs_to_jiffies(250));
  2774. }
  2775. pm_runtime_put(dev);
  2776. return IRQ_HANDLED;
  2777. }
  2778. /**
  2779. * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
  2780. *
  2781. * @component: WM8962 component
  2782. * @jack: jack to report detection events on
  2783. *
  2784. * Enable microphone detection via IRQ on the WM8962. If GPIOs are
  2785. * being used to bring out signals to the processor then only platform
  2786. * data configuration is needed for WM8962 and processor GPIOs should
  2787. * be configured using snd_soc_jack_add_gpios() instead.
  2788. *
  2789. * If no jack is supplied detection will be disabled.
  2790. */
  2791. int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
  2792. {
  2793. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2794. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2795. int irq_mask, enable;
  2796. wm8962->jack = jack;
  2797. if (jack) {
  2798. irq_mask = 0;
  2799. enable = WM8962_MICDET_ENA;
  2800. } else {
  2801. irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
  2802. enable = 0;
  2803. }
  2804. snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
  2805. WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
  2806. snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
  2807. WM8962_MICDET_ENA, enable);
  2808. /* Send an initial empty report */
  2809. snd_soc_jack_report(wm8962->jack, 0,
  2810. SND_JACK_MICROPHONE | SND_JACK_BTN_0);
  2811. snd_soc_dapm_mutex_lock(dapm);
  2812. if (jack) {
  2813. snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
  2814. snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
  2815. } else {
  2816. snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
  2817. snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
  2818. }
  2819. snd_soc_dapm_mutex_unlock(dapm);
  2820. return 0;
  2821. }
  2822. EXPORT_SYMBOL_GPL(wm8962_mic_detect);
  2823. static int beep_rates[] = {
  2824. 500, 1000, 2000, 4000,
  2825. };
  2826. static void wm8962_beep_work(struct work_struct *work)
  2827. {
  2828. struct wm8962_priv *wm8962 =
  2829. container_of(work, struct wm8962_priv, beep_work);
  2830. struct snd_soc_component *component = wm8962->component;
  2831. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2832. int i;
  2833. int reg = 0;
  2834. int best = 0;
  2835. if (wm8962->beep_rate) {
  2836. for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
  2837. if (abs(wm8962->beep_rate - beep_rates[i]) <
  2838. abs(wm8962->beep_rate - beep_rates[best]))
  2839. best = i;
  2840. }
  2841. dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
  2842. beep_rates[best], wm8962->beep_rate);
  2843. reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
  2844. snd_soc_dapm_enable_pin(dapm, "Beep");
  2845. } else {
  2846. dev_dbg(component->dev, "Disabling beep\n");
  2847. snd_soc_dapm_disable_pin(dapm, "Beep");
  2848. }
  2849. snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
  2850. WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
  2851. snd_soc_dapm_sync(dapm);
  2852. }
  2853. /* For usability define a way of injecting beep events for the device -
  2854. * many systems will not have a keyboard.
  2855. */
  2856. static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
  2857. unsigned int code, int hz)
  2858. {
  2859. struct snd_soc_component *component = input_get_drvdata(dev);
  2860. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2861. dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
  2862. switch (code) {
  2863. case SND_BELL:
  2864. if (hz)
  2865. hz = 1000;
  2866. fallthrough;
  2867. case SND_TONE:
  2868. break;
  2869. default:
  2870. return -1;
  2871. }
  2872. /* Kick the beep from a workqueue */
  2873. wm8962->beep_rate = hz;
  2874. schedule_work(&wm8962->beep_work);
  2875. return 0;
  2876. }
  2877. static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
  2878. const char *buf, size_t count)
  2879. {
  2880. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  2881. long int time;
  2882. int ret;
  2883. ret = kstrtol(buf, 10, &time);
  2884. if (ret != 0)
  2885. return ret;
  2886. input_event(wm8962->beep, EV_SND, SND_TONE, time);
  2887. return count;
  2888. }
  2889. static DEVICE_ATTR_WO(beep);
  2890. static void wm8962_init_beep(struct snd_soc_component *component)
  2891. {
  2892. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2893. int ret;
  2894. wm8962->beep = devm_input_allocate_device(component->dev);
  2895. if (!wm8962->beep) {
  2896. dev_err(component->dev, "Failed to allocate beep device\n");
  2897. return;
  2898. }
  2899. INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
  2900. wm8962->beep_rate = 0;
  2901. wm8962->beep->name = "WM8962 Beep Generator";
  2902. wm8962->beep->phys = dev_name(component->dev);
  2903. wm8962->beep->id.bustype = BUS_I2C;
  2904. wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
  2905. wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
  2906. wm8962->beep->event = wm8962_beep_event;
  2907. wm8962->beep->dev.parent = component->dev;
  2908. input_set_drvdata(wm8962->beep, component);
  2909. ret = input_register_device(wm8962->beep);
  2910. if (ret != 0) {
  2911. wm8962->beep = NULL;
  2912. dev_err(component->dev, "Failed to register beep device\n");
  2913. }
  2914. ret = device_create_file(component->dev, &dev_attr_beep);
  2915. if (ret != 0) {
  2916. dev_err(component->dev, "Failed to create keyclick file: %d\n",
  2917. ret);
  2918. }
  2919. }
  2920. static void wm8962_free_beep(struct snd_soc_component *component)
  2921. {
  2922. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  2923. device_remove_file(component->dev, &dev_attr_beep);
  2924. cancel_work_sync(&wm8962->beep_work);
  2925. wm8962->beep = NULL;
  2926. snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
  2927. }
  2928. static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
  2929. {
  2930. int mask = 0;
  2931. int val = 0;
  2932. /* Some of the GPIOs are behind MFP configuration and need to
  2933. * be put into GPIO mode. */
  2934. switch (gpio) {
  2935. case 2:
  2936. mask = WM8962_CLKOUT2_SEL_MASK;
  2937. val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
  2938. break;
  2939. case 3:
  2940. mask = WM8962_CLKOUT3_SEL_MASK;
  2941. val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
  2942. break;
  2943. default:
  2944. break;
  2945. }
  2946. if (mask)
  2947. regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
  2948. mask, val);
  2949. }
  2950. #ifdef CONFIG_GPIOLIB
  2951. static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
  2952. {
  2953. struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
  2954. /* The WM8962 GPIOs aren't linearly numbered. For simplicity
  2955. * we export linear numbers and error out if the unsupported
  2956. * ones are requsted.
  2957. */
  2958. switch (offset + 1) {
  2959. case 2:
  2960. case 3:
  2961. case 5:
  2962. case 6:
  2963. break;
  2964. default:
  2965. return -EINVAL;
  2966. }
  2967. wm8962_set_gpio_mode(wm8962, offset + 1);
  2968. return 0;
  2969. }
  2970. static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  2971. {
  2972. struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
  2973. struct snd_soc_component *component = wm8962->component;
  2974. snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
  2975. WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
  2976. }
  2977. static int wm8962_gpio_direction_out(struct gpio_chip *chip,
  2978. unsigned offset, int value)
  2979. {
  2980. struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
  2981. struct snd_soc_component *component = wm8962->component;
  2982. int ret, val;
  2983. /* Force function 1 (logic output) */
  2984. val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
  2985. ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
  2986. WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
  2987. if (ret < 0)
  2988. return ret;
  2989. return 0;
  2990. }
  2991. static const struct gpio_chip wm8962_template_chip = {
  2992. .label = "wm8962",
  2993. .owner = THIS_MODULE,
  2994. .request = wm8962_gpio_request,
  2995. .direction_output = wm8962_gpio_direction_out,
  2996. .set = wm8962_gpio_set,
  2997. .can_sleep = 1,
  2998. };
  2999. static void wm8962_init_gpio(struct snd_soc_component *component)
  3000. {
  3001. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  3002. struct wm8962_pdata *pdata = &wm8962->pdata;
  3003. int ret;
  3004. wm8962->gpio_chip = wm8962_template_chip;
  3005. wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
  3006. wm8962->gpio_chip.parent = component->dev;
  3007. if (pdata->gpio_base)
  3008. wm8962->gpio_chip.base = pdata->gpio_base;
  3009. else
  3010. wm8962->gpio_chip.base = -1;
  3011. ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
  3012. if (ret != 0)
  3013. dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
  3014. }
  3015. static void wm8962_free_gpio(struct snd_soc_component *component)
  3016. {
  3017. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  3018. gpiochip_remove(&wm8962->gpio_chip);
  3019. }
  3020. #else
  3021. static void wm8962_init_gpio(struct snd_soc_component *component)
  3022. {
  3023. }
  3024. static void wm8962_free_gpio(struct snd_soc_component *component)
  3025. {
  3026. }
  3027. #endif
  3028. static int wm8962_probe(struct snd_soc_component *component)
  3029. {
  3030. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3031. int ret;
  3032. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  3033. int i;
  3034. bool dmicclk, dmicdat;
  3035. wm8962->component = component;
  3036. wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
  3037. wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
  3038. wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
  3039. wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
  3040. wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
  3041. wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
  3042. wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
  3043. wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
  3044. /* This should really be moved into the regulator core */
  3045. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
  3046. ret = devm_regulator_register_notifier(
  3047. wm8962->supplies[i].consumer,
  3048. &wm8962->disable_nb[i]);
  3049. if (ret != 0) {
  3050. dev_err(component->dev,
  3051. "Failed to register regulator notifier: %d\n",
  3052. ret);
  3053. }
  3054. }
  3055. wm8962_add_widgets(component);
  3056. /* Save boards having to disable DMIC when not in use */
  3057. dmicclk = false;
  3058. dmicdat = false;
  3059. for (i = 1; i < WM8962_MAX_GPIO; i++) {
  3060. /*
  3061. * Register 515 (WM8962_GPIO_BASE + 3) does not exist,
  3062. * so skip its access
  3063. */
  3064. if (i == 3)
  3065. continue;
  3066. switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
  3067. & WM8962_GP2_FN_MASK) {
  3068. case WM8962_GPIO_FN_DMICCLK:
  3069. dmicclk = true;
  3070. break;
  3071. case WM8962_GPIO_FN_DMICDAT:
  3072. dmicdat = true;
  3073. break;
  3074. default:
  3075. break;
  3076. }
  3077. }
  3078. if (!dmicclk || !dmicdat) {
  3079. dev_dbg(component->dev, "DMIC not in use, disabling\n");
  3080. snd_soc_dapm_nc_pin(dapm, "DMICDAT");
  3081. }
  3082. if (dmicclk != dmicdat)
  3083. dev_warn(component->dev, "DMIC GPIOs partially configured\n");
  3084. wm8962_init_beep(component);
  3085. wm8962_init_gpio(component);
  3086. return 0;
  3087. }
  3088. static void wm8962_remove(struct snd_soc_component *component)
  3089. {
  3090. struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
  3091. cancel_delayed_work_sync(&wm8962->mic_work);
  3092. wm8962_free_gpio(component);
  3093. wm8962_free_beep(component);
  3094. }
  3095. static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
  3096. .probe = wm8962_probe,
  3097. .remove = wm8962_remove,
  3098. .set_bias_level = wm8962_set_bias_level,
  3099. .set_pll = wm8962_set_fll,
  3100. .use_pmdown_time = 1,
  3101. .endianness = 1,
  3102. };
  3103. /* Improve power consumption for IN4 DC measurement mode */
  3104. static const struct reg_sequence wm8962_dc_measure[] = {
  3105. { 0xfd, 0x1 },
  3106. { 0xcc, 0x40 },
  3107. { 0xfd, 0 },
  3108. };
  3109. static const struct regmap_config wm8962_regmap = {
  3110. .reg_bits = 16,
  3111. .val_bits = 16,
  3112. .max_register = WM8962_MAX_REGISTER,
  3113. .reg_defaults = wm8962_reg,
  3114. .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
  3115. .volatile_reg = wm8962_volatile_register,
  3116. .readable_reg = wm8962_readable_register,
  3117. .cache_type = REGCACHE_RBTREE,
  3118. };
  3119. static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
  3120. struct wm8962_pdata *pdata)
  3121. {
  3122. const struct device_node *np = i2c->dev.of_node;
  3123. u32 val32;
  3124. int i;
  3125. if (of_property_read_bool(np, "spk-mono"))
  3126. pdata->spk_mono = true;
  3127. if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
  3128. pdata->mic_cfg = val32;
  3129. if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
  3130. ARRAY_SIZE(pdata->gpio_init)) >= 0)
  3131. for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
  3132. /*
  3133. * The range of GPIO register value is [0x0, 0xffff]
  3134. * While the default value of each register is 0x0
  3135. * Any other value will be regarded as default value
  3136. */
  3137. if (pdata->gpio_init[i] > 0xffff)
  3138. pdata->gpio_init[i] = 0x0;
  3139. }
  3140. pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL);
  3141. return PTR_ERR_OR_ZERO(pdata->mclk);
  3142. }
  3143. static int wm8962_i2c_probe(struct i2c_client *i2c)
  3144. {
  3145. struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
  3146. struct wm8962_priv *wm8962;
  3147. unsigned int reg;
  3148. int ret, i, irq_pol, trigger;
  3149. wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
  3150. if (wm8962 == NULL)
  3151. return -ENOMEM;
  3152. mutex_init(&wm8962->dsp2_ena_lock);
  3153. i2c_set_clientdata(i2c, wm8962);
  3154. INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
  3155. init_completion(&wm8962->fll_lock);
  3156. wm8962->irq = i2c->irq;
  3157. /* If platform data was supplied, update the default data in priv */
  3158. if (pdata) {
  3159. memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
  3160. } else if (i2c->dev.of_node) {
  3161. ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
  3162. if (ret != 0)
  3163. return ret;
  3164. }
  3165. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  3166. wm8962->supplies[i].supply = wm8962_supply_names[i];
  3167. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
  3168. wm8962->supplies);
  3169. if (ret != 0) {
  3170. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  3171. goto err;
  3172. }
  3173. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  3174. wm8962->supplies);
  3175. if (ret != 0) {
  3176. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  3177. return ret;
  3178. }
  3179. wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
  3180. if (IS_ERR(wm8962->regmap)) {
  3181. ret = PTR_ERR(wm8962->regmap);
  3182. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  3183. goto err_enable;
  3184. }
  3185. /*
  3186. * We haven't marked the chip revision as volatile due to
  3187. * sharing a register with the right input volume; explicitly
  3188. * bypass the cache to read it.
  3189. */
  3190. regcache_cache_bypass(wm8962->regmap, true);
  3191. ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
  3192. if (ret < 0) {
  3193. dev_err(&i2c->dev, "Failed to read ID register\n");
  3194. goto err_enable;
  3195. }
  3196. if (reg != 0x6243) {
  3197. dev_err(&i2c->dev,
  3198. "Device is not a WM8962, ID %x != 0x6243\n", reg);
  3199. ret = -EINVAL;
  3200. goto err_enable;
  3201. }
  3202. ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
  3203. if (ret < 0) {
  3204. dev_err(&i2c->dev, "Failed to read device revision: %d\n",
  3205. ret);
  3206. goto err_enable;
  3207. }
  3208. dev_info(&i2c->dev, "customer id %x revision %c\n",
  3209. (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
  3210. ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
  3211. + 'A');
  3212. regcache_cache_bypass(wm8962->regmap, false);
  3213. ret = wm8962_reset(wm8962);
  3214. if (ret < 0) {
  3215. dev_err(&i2c->dev, "Failed to issue reset\n");
  3216. goto err_enable;
  3217. }
  3218. /* SYSCLK defaults to on; make sure it is off so we can safely
  3219. * write to registers if the device is declocked.
  3220. */
  3221. regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
  3222. WM8962_SYSCLK_ENA, 0);
  3223. /* Ensure we have soft control over all registers */
  3224. regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
  3225. WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
  3226. /* Ensure that the oscillator and PLLs are disabled */
  3227. regmap_update_bits(wm8962->regmap, WM8962_PLL2,
  3228. WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
  3229. 0);
  3230. /* Apply static configuration for GPIOs */
  3231. for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
  3232. if (wm8962->pdata.gpio_init[i]) {
  3233. wm8962_set_gpio_mode(wm8962, i + 1);
  3234. regmap_write(wm8962->regmap, 0x200 + i,
  3235. wm8962->pdata.gpio_init[i] & 0xffff);
  3236. }
  3237. /* Put the speakers into mono mode? */
  3238. if (wm8962->pdata.spk_mono)
  3239. regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
  3240. WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
  3241. /* Micbias setup, detection enable and detection
  3242. * threasholds. */
  3243. if (wm8962->pdata.mic_cfg)
  3244. regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
  3245. WM8962_MICDET_ENA |
  3246. WM8962_MICDET_THR_MASK |
  3247. WM8962_MICSHORT_THR_MASK |
  3248. WM8962_MICBIAS_LVL,
  3249. wm8962->pdata.mic_cfg);
  3250. /* Latch volume update bits */
  3251. regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
  3252. WM8962_IN_VU, WM8962_IN_VU);
  3253. regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
  3254. WM8962_IN_VU, WM8962_IN_VU);
  3255. regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
  3256. WM8962_ADC_VU, WM8962_ADC_VU);
  3257. regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
  3258. WM8962_ADC_VU, WM8962_ADC_VU);
  3259. regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
  3260. WM8962_DAC_VU, WM8962_DAC_VU);
  3261. regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
  3262. WM8962_DAC_VU, WM8962_DAC_VU);
  3263. regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
  3264. WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
  3265. regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
  3266. WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
  3267. regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
  3268. WM8962_HPOUT_VU, WM8962_HPOUT_VU);
  3269. regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
  3270. WM8962_HPOUT_VU, WM8962_HPOUT_VU);
  3271. /* Stereo control for EQ */
  3272. regmap_update_bits(wm8962->regmap, WM8962_EQ1,
  3273. WM8962_EQ_SHARED_COEFF, 0);
  3274. /* Don't debouce interrupts so we don't need SYSCLK */
  3275. regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
  3276. WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
  3277. WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
  3278. 0);
  3279. if (wm8962->pdata.in4_dc_measure) {
  3280. ret = regmap_register_patch(wm8962->regmap,
  3281. wm8962_dc_measure,
  3282. ARRAY_SIZE(wm8962_dc_measure));
  3283. if (ret != 0)
  3284. dev_err(&i2c->dev,
  3285. "Failed to configure for DC measurement: %d\n",
  3286. ret);
  3287. }
  3288. if (wm8962->irq) {
  3289. if (wm8962->pdata.irq_active_low) {
  3290. trigger = IRQF_TRIGGER_LOW;
  3291. irq_pol = WM8962_IRQ_POL;
  3292. } else {
  3293. trigger = IRQF_TRIGGER_HIGH;
  3294. irq_pol = 0;
  3295. }
  3296. regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
  3297. WM8962_IRQ_POL, irq_pol);
  3298. ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
  3299. wm8962_irq,
  3300. trigger | IRQF_ONESHOT,
  3301. "wm8962", &i2c->dev);
  3302. if (ret != 0) {
  3303. dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
  3304. wm8962->irq, ret);
  3305. wm8962->irq = 0;
  3306. /* Non-fatal */
  3307. } else {
  3308. /* Enable some IRQs by default */
  3309. regmap_update_bits(wm8962->regmap,
  3310. WM8962_INTERRUPT_STATUS_2_MASK,
  3311. WM8962_FLL_LOCK_EINT |
  3312. WM8962_TEMP_SHUT_EINT |
  3313. WM8962_FIFOS_ERR_EINT, 0);
  3314. }
  3315. }
  3316. pm_runtime_enable(&i2c->dev);
  3317. pm_request_idle(&i2c->dev);
  3318. ret = devm_snd_soc_register_component(&i2c->dev,
  3319. &soc_component_dev_wm8962, &wm8962_dai, 1);
  3320. if (ret < 0)
  3321. goto err_pm_runtime;
  3322. regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
  3323. WM8962_TEMP_ENA_HP_MASK, 0);
  3324. regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
  3325. WM8962_TEMP_ENA_SPK_MASK, 0);
  3326. regcache_cache_only(wm8962->regmap, true);
  3327. /* The drivers should power up as needed */
  3328. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  3329. return 0;
  3330. err_pm_runtime:
  3331. pm_runtime_disable(&i2c->dev);
  3332. err_enable:
  3333. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  3334. err:
  3335. return ret;
  3336. }
  3337. static void wm8962_i2c_remove(struct i2c_client *client)
  3338. {
  3339. pm_runtime_disable(&client->dev);
  3340. }
  3341. #ifdef CONFIG_PM
  3342. static int wm8962_runtime_resume(struct device *dev)
  3343. {
  3344. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  3345. int ret;
  3346. ret = clk_prepare_enable(wm8962->pdata.mclk);
  3347. if (ret) {
  3348. dev_err(dev, "Failed to enable MCLK: %d\n", ret);
  3349. return ret;
  3350. }
  3351. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  3352. wm8962->supplies);
  3353. if (ret != 0) {
  3354. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  3355. goto disable_clock;
  3356. }
  3357. regcache_cache_only(wm8962->regmap, false);
  3358. wm8962_reset(wm8962);
  3359. regcache_mark_dirty(wm8962->regmap);
  3360. /* SYSCLK defaults to on; make sure it is off so we can safely
  3361. * write to registers if the device is declocked.
  3362. */
  3363. regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
  3364. WM8962_SYSCLK_ENA, 0);
  3365. /* Ensure we have soft control over all registers */
  3366. regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
  3367. WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
  3368. /* Ensure that the oscillator and PLLs are disabled */
  3369. regmap_update_bits(wm8962->regmap, WM8962_PLL2,
  3370. WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
  3371. 0);
  3372. regcache_sync(wm8962->regmap);
  3373. regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
  3374. WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
  3375. WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
  3376. /* Bias enable at 2*5k (fast start-up) */
  3377. regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
  3378. WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
  3379. WM8962_BIAS_ENA | 0x180);
  3380. msleep(5);
  3381. return 0;
  3382. disable_clock:
  3383. clk_disable_unprepare(wm8962->pdata.mclk);
  3384. return ret;
  3385. }
  3386. static int wm8962_runtime_suspend(struct device *dev)
  3387. {
  3388. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  3389. regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
  3390. WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
  3391. regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
  3392. WM8962_STARTUP_BIAS_ENA |
  3393. WM8962_VMID_BUF_ENA, 0);
  3394. regcache_cache_only(wm8962->regmap, true);
  3395. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
  3396. wm8962->supplies);
  3397. clk_disable_unprepare(wm8962->pdata.mclk);
  3398. return 0;
  3399. }
  3400. #endif
  3401. static const struct dev_pm_ops wm8962_pm = {
  3402. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
  3403. SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
  3404. };
  3405. static const struct i2c_device_id wm8962_i2c_id[] = {
  3406. { "wm8962", 0 },
  3407. { }
  3408. };
  3409. MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
  3410. static const struct of_device_id wm8962_of_match[] = {
  3411. { .compatible = "wlf,wm8962", },
  3412. { }
  3413. };
  3414. MODULE_DEVICE_TABLE(of, wm8962_of_match);
  3415. static struct i2c_driver wm8962_i2c_driver = {
  3416. .driver = {
  3417. .name = "wm8962",
  3418. .of_match_table = wm8962_of_match,
  3419. .pm = &wm8962_pm,
  3420. },
  3421. .probe_new = wm8962_i2c_probe,
  3422. .remove = wm8962_i2c_remove,
  3423. .id_table = wm8962_i2c_id,
  3424. };
  3425. module_i2c_driver(wm8962_i2c_driver);
  3426. MODULE_DESCRIPTION("ASoC WM8962 driver");
  3427. MODULE_AUTHOR("Mark Brown <[email protected]>");
  3428. MODULE_LICENSE("GPL");