wm8961.h 45 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * wm8961.h -- WM8961 Soc Audio driver
  4. */
  5. #ifndef _WM8961_H
  6. #define _WM8961_H
  7. #include <sound/soc.h>
  8. #define WM8961_BCLK 1
  9. #define WM8961_LRCLK 2
  10. #define WM8961_BCLK_DIV_1 0
  11. #define WM8961_BCLK_DIV_1_5 1
  12. #define WM8961_BCLK_DIV_2 2
  13. #define WM8961_BCLK_DIV_3 3
  14. #define WM8961_BCLK_DIV_4 4
  15. #define WM8961_BCLK_DIV_5_5 5
  16. #define WM8961_BCLK_DIV_6 6
  17. #define WM8961_BCLK_DIV_8 7
  18. #define WM8961_BCLK_DIV_11 8
  19. #define WM8961_BCLK_DIV_12 9
  20. #define WM8961_BCLK_DIV_16 10
  21. #define WM8961_BCLK_DIV_24 11
  22. #define WM8961_BCLK_DIV_32 13
  23. /*
  24. * Register values.
  25. */
  26. #define WM8961_LEFT_INPUT_VOLUME 0x00
  27. #define WM8961_RIGHT_INPUT_VOLUME 0x01
  28. #define WM8961_LOUT1_VOLUME 0x02
  29. #define WM8961_ROUT1_VOLUME 0x03
  30. #define WM8961_CLOCKING1 0x04
  31. #define WM8961_ADC_DAC_CONTROL_1 0x05
  32. #define WM8961_ADC_DAC_CONTROL_2 0x06
  33. #define WM8961_AUDIO_INTERFACE_0 0x07
  34. #define WM8961_CLOCKING2 0x08
  35. #define WM8961_AUDIO_INTERFACE_1 0x09
  36. #define WM8961_LEFT_DAC_VOLUME 0x0A
  37. #define WM8961_RIGHT_DAC_VOLUME 0x0B
  38. #define WM8961_AUDIO_INTERFACE_2 0x0E
  39. #define WM8961_SOFTWARE_RESET 0x0F
  40. #define WM8961_ALC1 0x11
  41. #define WM8961_ALC2 0x12
  42. #define WM8961_ALC3 0x13
  43. #define WM8961_NOISE_GATE 0x14
  44. #define WM8961_LEFT_ADC_VOLUME 0x15
  45. #define WM8961_RIGHT_ADC_VOLUME 0x16
  46. #define WM8961_ADDITIONAL_CONTROL_1 0x17
  47. #define WM8961_ADDITIONAL_CONTROL_2 0x18
  48. #define WM8961_PWR_MGMT_1 0x19
  49. #define WM8961_PWR_MGMT_2 0x1A
  50. #define WM8961_ADDITIONAL_CONTROL_3 0x1B
  51. #define WM8961_ANTI_POP 0x1C
  52. #define WM8961_CLOCKING_3 0x1E
  53. #define WM8961_ADCL_SIGNAL_PATH 0x20
  54. #define WM8961_ADCR_SIGNAL_PATH 0x21
  55. #define WM8961_LOUT2_VOLUME 0x28
  56. #define WM8961_ROUT2_VOLUME 0x29
  57. #define WM8961_PWR_MGMT_3 0x2F
  58. #define WM8961_ADDITIONAL_CONTROL_4 0x30
  59. #define WM8961_CLASS_D_CONTROL_1 0x31
  60. #define WM8961_CLASS_D_CONTROL_2 0x33
  61. #define WM8961_CLOCKING_4 0x38
  62. #define WM8961_DSP_SIDETONE_0 0x39
  63. #define WM8961_DSP_SIDETONE_1 0x3A
  64. #define WM8961_DC_SERVO_0 0x3C
  65. #define WM8961_DC_SERVO_1 0x3D
  66. #define WM8961_DC_SERVO_3 0x3F
  67. #define WM8961_DC_SERVO_5 0x41
  68. #define WM8961_ANALOGUE_PGA_BIAS 0x44
  69. #define WM8961_ANALOGUE_HP_0 0x45
  70. #define WM8961_ANALOGUE_HP_2 0x47
  71. #define WM8961_CHARGE_PUMP_1 0x48
  72. #define WM8961_CHARGE_PUMP_B 0x52
  73. #define WM8961_WRITE_SEQUENCER_1 0x57
  74. #define WM8961_WRITE_SEQUENCER_2 0x58
  75. #define WM8961_WRITE_SEQUENCER_3 0x59
  76. #define WM8961_WRITE_SEQUENCER_4 0x5A
  77. #define WM8961_WRITE_SEQUENCER_5 0x5B
  78. #define WM8961_WRITE_SEQUENCER_6 0x5C
  79. #define WM8961_WRITE_SEQUENCER_7 0x5D
  80. #define WM8961_GENERAL_TEST_1 0xFC
  81. /*
  82. * Field Definitions.
  83. */
  84. /*
  85. * R0 (0x00) - Left Input volume
  86. */
  87. #define WM8961_IPVU 0x0100 /* IPVU */
  88. #define WM8961_IPVU_MASK 0x0100 /* IPVU */
  89. #define WM8961_IPVU_SHIFT 8 /* IPVU */
  90. #define WM8961_IPVU_WIDTH 1 /* IPVU */
  91. #define WM8961_LINMUTE 0x0080 /* LINMUTE */
  92. #define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */
  93. #define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */
  94. #define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */
  95. #define WM8961_LIZC 0x0040 /* LIZC */
  96. #define WM8961_LIZC_MASK 0x0040 /* LIZC */
  97. #define WM8961_LIZC_SHIFT 6 /* LIZC */
  98. #define WM8961_LIZC_WIDTH 1 /* LIZC */
  99. #define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */
  100. #define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */
  101. #define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */
  102. /*
  103. * R1 (0x01) - Right Input volume
  104. */
  105. #define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */
  106. #define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */
  107. #define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */
  108. #define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */
  109. #define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */
  110. #define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */
  111. #define WM8961_IPVU 0x0100 /* IPVU */
  112. #define WM8961_IPVU_MASK 0x0100 /* IPVU */
  113. #define WM8961_IPVU_SHIFT 8 /* IPVU */
  114. #define WM8961_IPVU_WIDTH 1 /* IPVU */
  115. #define WM8961_RINMUTE 0x0080 /* RINMUTE */
  116. #define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */
  117. #define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */
  118. #define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */
  119. #define WM8961_RIZC 0x0040 /* RIZC */
  120. #define WM8961_RIZC_MASK 0x0040 /* RIZC */
  121. #define WM8961_RIZC_SHIFT 6 /* RIZC */
  122. #define WM8961_RIZC_WIDTH 1 /* RIZC */
  123. #define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */
  124. #define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */
  125. #define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */
  126. /*
  127. * R2 (0x02) - LOUT1 volume
  128. */
  129. #define WM8961_OUT1VU 0x0100 /* OUT1VU */
  130. #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */
  131. #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */
  132. #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */
  133. #define WM8961_LO1ZC 0x0080 /* LO1ZC */
  134. #define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */
  135. #define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */
  136. #define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */
  137. #define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */
  138. #define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */
  139. #define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */
  140. /*
  141. * R3 (0x03) - ROUT1 volume
  142. */
  143. #define WM8961_OUT1VU 0x0100 /* OUT1VU */
  144. #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */
  145. #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */
  146. #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */
  147. #define WM8961_RO1ZC 0x0080 /* RO1ZC */
  148. #define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */
  149. #define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */
  150. #define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */
  151. #define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */
  152. #define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */
  153. #define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */
  154. /*
  155. * R4 (0x04) - Clocking1
  156. */
  157. #define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */
  158. #define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */
  159. #define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */
  160. #define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */
  161. #define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */
  162. #define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */
  163. #define WM8961_MCLKDIV 0x0004 /* MCLKDIV */
  164. #define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */
  165. #define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */
  166. #define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */
  167. /*
  168. * R5 (0x05) - ADC & DAC Control 1
  169. */
  170. #define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */
  171. #define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */
  172. #define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */
  173. #define WM8961_DACMU 0x0008 /* DACMU */
  174. #define WM8961_DACMU_MASK 0x0008 /* DACMU */
  175. #define WM8961_DACMU_SHIFT 3 /* DACMU */
  176. #define WM8961_DACMU_WIDTH 1 /* DACMU */
  177. #define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
  178. #define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
  179. #define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
  180. #define WM8961_ADCHPD 0x0001 /* ADCHPD */
  181. #define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */
  182. #define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */
  183. #define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */
  184. /*
  185. * R6 (0x06) - ADC & DAC Control 2
  186. */
  187. #define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */
  188. #define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */
  189. #define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */
  190. #define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */
  191. #define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */
  192. #define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */
  193. #define WM8961_DACSMM 0x0008 /* DACSMM */
  194. #define WM8961_DACSMM_MASK 0x0008 /* DACSMM */
  195. #define WM8961_DACSMM_SHIFT 3 /* DACSMM */
  196. #define WM8961_DACSMM_WIDTH 1 /* DACSMM */
  197. #define WM8961_DACMR 0x0004 /* DACMR */
  198. #define WM8961_DACMR_MASK 0x0004 /* DACMR */
  199. #define WM8961_DACMR_SHIFT 2 /* DACMR */
  200. #define WM8961_DACMR_WIDTH 1 /* DACMR */
  201. #define WM8961_DACSLOPE 0x0002 /* DACSLOPE */
  202. #define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */
  203. #define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */
  204. #define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */
  205. #define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */
  206. #define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
  207. #define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
  208. #define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
  209. /*
  210. * R7 (0x07) - Audio Interface 0
  211. */
  212. #define WM8961_ALRSWAP 0x0100 /* ALRSWAP */
  213. #define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */
  214. #define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */
  215. #define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */
  216. #define WM8961_BCLKINV 0x0080 /* BCLKINV */
  217. #define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */
  218. #define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */
  219. #define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */
  220. #define WM8961_MS 0x0040 /* MS */
  221. #define WM8961_MS_MASK 0x0040 /* MS */
  222. #define WM8961_MS_SHIFT 6 /* MS */
  223. #define WM8961_MS_WIDTH 1 /* MS */
  224. #define WM8961_DLRSWAP 0x0020 /* DLRSWAP */
  225. #define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */
  226. #define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */
  227. #define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */
  228. #define WM8961_LRP 0x0010 /* LRP */
  229. #define WM8961_LRP_MASK 0x0010 /* LRP */
  230. #define WM8961_LRP_SHIFT 4 /* LRP */
  231. #define WM8961_LRP_WIDTH 1 /* LRP */
  232. #define WM8961_WL_MASK 0x000C /* WL - [3:2] */
  233. #define WM8961_WL_SHIFT 2 /* WL - [3:2] */
  234. #define WM8961_WL_WIDTH 2 /* WL - [3:2] */
  235. #define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */
  236. #define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */
  237. #define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */
  238. /*
  239. * R8 (0x08) - Clocking2
  240. */
  241. #define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
  242. #define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
  243. #define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
  244. #define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */
  245. #define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */
  246. #define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */
  247. #define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
  248. #define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */
  249. #define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */
  250. #define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */
  251. #define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
  252. #define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */
  253. #define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */
  254. #define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */
  255. /*
  256. * R9 (0x09) - Audio Interface 1
  257. */
  258. #define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */
  259. #define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */
  260. #define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */
  261. #define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */
  262. #define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */
  263. #define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */
  264. #define WM8961_LOOPBACK 0x0001 /* LOOPBACK */
  265. #define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */
  266. #define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */
  267. #define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */
  268. /*
  269. * R10 (0x0A) - Left DAC volume
  270. */
  271. #define WM8961_DACVU 0x0100 /* DACVU */
  272. #define WM8961_DACVU_MASK 0x0100 /* DACVU */
  273. #define WM8961_DACVU_SHIFT 8 /* DACVU */
  274. #define WM8961_DACVU_WIDTH 1 /* DACVU */
  275. #define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */
  276. #define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */
  277. #define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */
  278. /*
  279. * R11 (0x0B) - Right DAC volume
  280. */
  281. #define WM8961_DACVU 0x0100 /* DACVU */
  282. #define WM8961_DACVU_MASK 0x0100 /* DACVU */
  283. #define WM8961_DACVU_SHIFT 8 /* DACVU */
  284. #define WM8961_DACVU_WIDTH 1 /* DACVU */
  285. #define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */
  286. #define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */
  287. #define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */
  288. /*
  289. * R14 (0x0E) - Audio Interface 2
  290. */
  291. #define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */
  292. #define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */
  293. #define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */
  294. /*
  295. * R15 (0x0F) - Software Reset
  296. */
  297. #define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  298. #define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  299. #define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  300. /*
  301. * R17 (0x11) - ALC1
  302. */
  303. #define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */
  304. #define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */
  305. #define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */
  306. #define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */
  307. #define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */
  308. #define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */
  309. #define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */
  310. #define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */
  311. #define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */
  312. /*
  313. * R18 (0x12) - ALC2
  314. */
  315. #define WM8961_ALCZC 0x0080 /* ALCZC */
  316. #define WM8961_ALCZC_MASK 0x0080 /* ALCZC */
  317. #define WM8961_ALCZC_SHIFT 7 /* ALCZC */
  318. #define WM8961_ALCZC_WIDTH 1 /* ALCZC */
  319. #define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */
  320. #define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */
  321. #define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */
  322. #define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */
  323. #define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */
  324. #define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */
  325. /*
  326. * R19 (0x13) - ALC3
  327. */
  328. #define WM8961_ALCMODE 0x0100 /* ALCMODE */
  329. #define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */
  330. #define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */
  331. #define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */
  332. #define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */
  333. #define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */
  334. #define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */
  335. #define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */
  336. #define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */
  337. #define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */
  338. /*
  339. * R20 (0x14) - Noise Gate
  340. */
  341. #define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */
  342. #define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */
  343. #define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */
  344. #define WM8961_NGG 0x0002 /* NGG */
  345. #define WM8961_NGG_MASK 0x0002 /* NGG */
  346. #define WM8961_NGG_SHIFT 1 /* NGG */
  347. #define WM8961_NGG_WIDTH 1 /* NGG */
  348. #define WM8961_NGAT 0x0001 /* NGAT */
  349. #define WM8961_NGAT_MASK 0x0001 /* NGAT */
  350. #define WM8961_NGAT_SHIFT 0 /* NGAT */
  351. #define WM8961_NGAT_WIDTH 1 /* NGAT */
  352. /*
  353. * R21 (0x15) - Left ADC volume
  354. */
  355. #define WM8961_ADCVU 0x0100 /* ADCVU */
  356. #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */
  357. #define WM8961_ADCVU_SHIFT 8 /* ADCVU */
  358. #define WM8961_ADCVU_WIDTH 1 /* ADCVU */
  359. #define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */
  360. #define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */
  361. #define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */
  362. /*
  363. * R22 (0x16) - Right ADC volume
  364. */
  365. #define WM8961_ADCVU 0x0100 /* ADCVU */
  366. #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */
  367. #define WM8961_ADCVU_SHIFT 8 /* ADCVU */
  368. #define WM8961_ADCVU_WIDTH 1 /* ADCVU */
  369. #define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */
  370. #define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */
  371. #define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */
  372. /*
  373. * R23 (0x17) - Additional control(1)
  374. */
  375. #define WM8961_TSDEN 0x0100 /* TSDEN */
  376. #define WM8961_TSDEN_MASK 0x0100 /* TSDEN */
  377. #define WM8961_TSDEN_SHIFT 8 /* TSDEN */
  378. #define WM8961_TSDEN_WIDTH 1 /* TSDEN */
  379. #define WM8961_DMONOMIX 0x0010 /* DMONOMIX */
  380. #define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */
  381. #define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */
  382. #define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */
  383. #define WM8961_TOEN 0x0001 /* TOEN */
  384. #define WM8961_TOEN_MASK 0x0001 /* TOEN */
  385. #define WM8961_TOEN_SHIFT 0 /* TOEN */
  386. #define WM8961_TOEN_WIDTH 1 /* TOEN */
  387. /*
  388. * R24 (0x18) - Additional control(2)
  389. */
  390. #define WM8961_TRIS 0x0008 /* TRIS */
  391. #define WM8961_TRIS_MASK 0x0008 /* TRIS */
  392. #define WM8961_TRIS_SHIFT 3 /* TRIS */
  393. #define WM8961_TRIS_WIDTH 1 /* TRIS */
  394. /*
  395. * R25 (0x19) - Pwr Mgmt (1)
  396. */
  397. #define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */
  398. #define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */
  399. #define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */
  400. #define WM8961_VREF 0x0040 /* VREF */
  401. #define WM8961_VREF_MASK 0x0040 /* VREF */
  402. #define WM8961_VREF_SHIFT 6 /* VREF */
  403. #define WM8961_VREF_WIDTH 1 /* VREF */
  404. #define WM8961_AINL 0x0020 /* AINL */
  405. #define WM8961_AINL_MASK 0x0020 /* AINL */
  406. #define WM8961_AINL_SHIFT 5 /* AINL */
  407. #define WM8961_AINL_WIDTH 1 /* AINL */
  408. #define WM8961_AINR 0x0010 /* AINR */
  409. #define WM8961_AINR_MASK 0x0010 /* AINR */
  410. #define WM8961_AINR_SHIFT 4 /* AINR */
  411. #define WM8961_AINR_WIDTH 1 /* AINR */
  412. #define WM8961_ADCL 0x0008 /* ADCL */
  413. #define WM8961_ADCL_MASK 0x0008 /* ADCL */
  414. #define WM8961_ADCL_SHIFT 3 /* ADCL */
  415. #define WM8961_ADCL_WIDTH 1 /* ADCL */
  416. #define WM8961_ADCR 0x0004 /* ADCR */
  417. #define WM8961_ADCR_MASK 0x0004 /* ADCR */
  418. #define WM8961_ADCR_SHIFT 2 /* ADCR */
  419. #define WM8961_ADCR_WIDTH 1 /* ADCR */
  420. #define WM8961_MICB 0x0002 /* MICB */
  421. #define WM8961_MICB_MASK 0x0002 /* MICB */
  422. #define WM8961_MICB_SHIFT 1 /* MICB */
  423. #define WM8961_MICB_WIDTH 1 /* MICB */
  424. /*
  425. * R26 (0x1A) - Pwr Mgmt (2)
  426. */
  427. #define WM8961_DACL 0x0100 /* DACL */
  428. #define WM8961_DACL_MASK 0x0100 /* DACL */
  429. #define WM8961_DACL_SHIFT 8 /* DACL */
  430. #define WM8961_DACL_WIDTH 1 /* DACL */
  431. #define WM8961_DACR 0x0080 /* DACR */
  432. #define WM8961_DACR_MASK 0x0080 /* DACR */
  433. #define WM8961_DACR_SHIFT 7 /* DACR */
  434. #define WM8961_DACR_WIDTH 1 /* DACR */
  435. #define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */
  436. #define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */
  437. #define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */
  438. #define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */
  439. #define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */
  440. #define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */
  441. #define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */
  442. #define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */
  443. #define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */
  444. #define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */
  445. #define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */
  446. #define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */
  447. #define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */
  448. #define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */
  449. #define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */
  450. #define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */
  451. /*
  452. * R27 (0x1B) - Additional Control (3)
  453. */
  454. #define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */
  455. #define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */
  456. #define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */
  457. /*
  458. * R28 (0x1C) - Anti-pop
  459. */
  460. #define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */
  461. #define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */
  462. #define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */
  463. #define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */
  464. #define WM8961_BUFIOEN 0x0008 /* BUFIOEN */
  465. #define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */
  466. #define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */
  467. #define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */
  468. #define WM8961_SOFT_ST 0x0004 /* SOFT_ST */
  469. #define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */
  470. #define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */
  471. #define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */
  472. /*
  473. * R30 (0x1E) - Clocking 3
  474. */
  475. #define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */
  476. #define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */
  477. #define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */
  478. #define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */
  479. #define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */
  480. #define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */
  481. #define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */
  482. #define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */
  483. #define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */
  484. #define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */
  485. /*
  486. * R32 (0x20) - ADCL signal path
  487. */
  488. #define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */
  489. #define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */
  490. #define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */
  491. /*
  492. * R33 (0x21) - ADCR signal path
  493. */
  494. #define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */
  495. #define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */
  496. #define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */
  497. /*
  498. * R40 (0x28) - LOUT2 volume
  499. */
  500. #define WM8961_SPKVU 0x0100 /* SPKVU */
  501. #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */
  502. #define WM8961_SPKVU_SHIFT 8 /* SPKVU */
  503. #define WM8961_SPKVU_WIDTH 1 /* SPKVU */
  504. #define WM8961_SPKLZC 0x0080 /* SPKLZC */
  505. #define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */
  506. #define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */
  507. #define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */
  508. #define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */
  509. #define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */
  510. #define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */
  511. /*
  512. * R41 (0x29) - ROUT2 volume
  513. */
  514. #define WM8961_SPKVU 0x0100 /* SPKVU */
  515. #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */
  516. #define WM8961_SPKVU_SHIFT 8 /* SPKVU */
  517. #define WM8961_SPKVU_WIDTH 1 /* SPKVU */
  518. #define WM8961_SPKRZC 0x0080 /* SPKRZC */
  519. #define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */
  520. #define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */
  521. #define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */
  522. #define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */
  523. #define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */
  524. #define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */
  525. /*
  526. * R47 (0x2F) - Pwr Mgmt (3)
  527. */
  528. #define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */
  529. #define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */
  530. #define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */
  531. #define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
  532. #define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */
  533. #define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */
  534. #define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */
  535. #define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */
  536. /*
  537. * R48 (0x30) - Additional Control (4)
  538. */
  539. #define WM8961_TSENSEN 0x0002 /* TSENSEN */
  540. #define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */
  541. #define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */
  542. #define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */
  543. #define WM8961_MBSEL 0x0001 /* MBSEL */
  544. #define WM8961_MBSEL_MASK 0x0001 /* MBSEL */
  545. #define WM8961_MBSEL_SHIFT 0 /* MBSEL */
  546. #define WM8961_MBSEL_WIDTH 1 /* MBSEL */
  547. /*
  548. * R49 (0x31) - Class D Control 1
  549. */
  550. #define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */
  551. #define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */
  552. #define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */
  553. #define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */
  554. #define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */
  555. #define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */
  556. #define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */
  557. #define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */
  558. /*
  559. * R51 (0x33) - Class D Control 2
  560. */
  561. #define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */
  562. #define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */
  563. #define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */
  564. /*
  565. * R56 (0x38) - Clocking 4
  566. */
  567. #define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */
  568. #define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */
  569. #define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */
  570. #define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */
  571. #define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */
  572. #define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */
  573. /*
  574. * R57 (0x39) - DSP Sidetone 0
  575. */
  576. #define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
  577. #define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
  578. #define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
  579. #define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */
  580. #define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */
  581. #define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */
  582. /*
  583. * R58 (0x3A) - DSP Sidetone 1
  584. */
  585. #define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */
  586. #define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */
  587. #define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */
  588. #define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
  589. #define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
  590. #define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
  591. /*
  592. * R60 (0x3C) - DC Servo 0
  593. */
  594. #define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */
  595. #define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */
  596. #define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */
  597. #define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */
  598. #define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */
  599. #define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */
  600. #define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */
  601. #define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */
  602. #define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */
  603. #define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */
  604. #define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */
  605. #define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */
  606. #define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */
  607. #define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */
  608. #define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */
  609. #define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */
  610. #define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */
  611. #define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */
  612. #define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */
  613. #define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */
  614. #define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */
  615. #define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */
  616. #define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */
  617. #define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */
  618. /*
  619. * R61 (0x3D) - DC Servo 1
  620. */
  621. #define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */
  622. #define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */
  623. #define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */
  624. #define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */
  625. #define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */
  626. #define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */
  627. #define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */
  628. #define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */
  629. #define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */
  630. #define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */
  631. #define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */
  632. #define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */
  633. #define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */
  634. #define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */
  635. #define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */
  636. #define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */
  637. #define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */
  638. #define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */
  639. #define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */
  640. #define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */
  641. #define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */
  642. #define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */
  643. #define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */
  644. #define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */
  645. /*
  646. * R63 (0x3F) - DC Servo 3
  647. */
  648. #define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */
  649. #define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */
  650. #define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */
  651. /*
  652. * R65 (0x41) - DC Servo 5
  653. */
  654. #define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */
  655. #define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */
  656. #define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */
  657. /*
  658. * R68 (0x44) - Analogue PGA Bias
  659. */
  660. #define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */
  661. #define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */
  662. #define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */
  663. /*
  664. * R69 (0x45) - Analogue HP 0
  665. */
  666. #define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */
  667. #define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */
  668. #define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */
  669. #define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */
  670. #define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */
  671. #define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */
  672. #define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */
  673. #define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */
  674. #define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */
  675. #define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */
  676. #define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */
  677. #define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */
  678. #define WM8961_HPL_ENA 0x0010 /* HPL_ENA */
  679. #define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */
  680. #define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */
  681. #define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */
  682. #define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */
  683. #define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */
  684. #define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */
  685. #define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */
  686. #define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */
  687. #define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */
  688. #define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */
  689. #define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */
  690. #define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */
  691. #define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */
  692. #define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */
  693. #define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */
  694. #define WM8961_HPR_ENA 0x0001 /* HPR_ENA */
  695. #define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */
  696. #define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */
  697. #define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */
  698. /*
  699. * R71 (0x47) - Analogue HP 2
  700. */
  701. #define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */
  702. #define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */
  703. #define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */
  704. #define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */
  705. #define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */
  706. #define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */
  707. #define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */
  708. #define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */
  709. #define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */
  710. /*
  711. * R72 (0x48) - Charge Pump 1
  712. */
  713. #define WM8961_CP_ENA 0x0001 /* CP_ENA */
  714. #define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */
  715. #define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */
  716. #define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */
  717. /*
  718. * R82 (0x52) - Charge Pump B
  719. */
  720. #define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */
  721. #define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */
  722. #define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */
  723. /*
  724. * R87 (0x57) - Write Sequencer 1
  725. */
  726. #define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */
  727. #define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */
  728. #define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */
  729. #define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  730. #define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */
  731. #define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */
  732. #define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */
  733. /*
  734. * R88 (0x58) - Write Sequencer 2
  735. */
  736. #define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */
  737. #define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */
  738. #define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */
  739. #define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
  740. #define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
  741. #define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
  742. #define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
  743. /*
  744. * R89 (0x59) - Write Sequencer 3
  745. */
  746. #define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
  747. #define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
  748. #define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
  749. /*
  750. * R90 (0x5A) - Write Sequencer 4
  751. */
  752. #define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */
  753. #define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */
  754. #define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */
  755. #define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  756. #define WM8961_WSEQ_START 0x0080 /* WSEQ_START */
  757. #define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */
  758. #define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */
  759. #define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */
  760. #define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
  761. #define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
  762. #define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
  763. /*
  764. * R91 (0x5B) - Write Sequencer 5
  765. */
  766. #define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */
  767. #define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */
  768. #define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */
  769. #define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */
  770. #define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */
  771. #define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */
  772. /*
  773. * R92 (0x5C) - Write Sequencer 6
  774. */
  775. #define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */
  776. #define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */
  777. #define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */
  778. /*
  779. * R93 (0x5D) - Write Sequencer 7
  780. */
  781. #define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
  782. #define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
  783. #define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
  784. #define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  785. /*
  786. * R252 (0xFC) - General test 1
  787. */
  788. #define WM8961_ARA_ENA 0x0002 /* ARA_ENA */
  789. #define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */
  790. #define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */
  791. #define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */
  792. #define WM8961_AUTO_INC 0x0001 /* AUTO_INC */
  793. #define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */
  794. #define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */
  795. #define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */
  796. #endif