wm8955.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8955.c -- WM8955 ALSA SoC Audio driver
  4. *
  5. * Copyright 2009 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/initval.h>
  23. #include <sound/tlv.h>
  24. #include <sound/wm8955.h>
  25. #include "wm8955.h"
  26. #define WM8955_NUM_SUPPLIES 4
  27. static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
  28. "DCVDD",
  29. "DBVDD",
  30. "HPVDD",
  31. "AVDD",
  32. };
  33. /* codec private data */
  34. struct wm8955_priv {
  35. struct regmap *regmap;
  36. unsigned int mclk_rate;
  37. int deemph;
  38. int fs;
  39. struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
  40. };
  41. static const struct reg_default wm8955_reg_defaults[] = {
  42. { 2, 0x0079 }, /* R2 - LOUT1 volume */
  43. { 3, 0x0079 }, /* R3 - ROUT1 volume */
  44. { 5, 0x0008 }, /* R5 - DAC Control */
  45. { 7, 0x000A }, /* R7 - Audio Interface */
  46. { 8, 0x0000 }, /* R8 - Sample Rate */
  47. { 10, 0x00FF }, /* R10 - Left DAC volume */
  48. { 11, 0x00FF }, /* R11 - Right DAC volume */
  49. { 12, 0x000F }, /* R12 - Bass control */
  50. { 13, 0x000F }, /* R13 - Treble control */
  51. { 23, 0x00C1 }, /* R23 - Additional control (1) */
  52. { 24, 0x0000 }, /* R24 - Additional control (2) */
  53. { 25, 0x0000 }, /* R25 - Power Management (1) */
  54. { 26, 0x0000 }, /* R26 - Power Management (2) */
  55. { 27, 0x0000 }, /* R27 - Additional Control (3) */
  56. { 34, 0x0050 }, /* R34 - Left out Mix (1) */
  57. { 35, 0x0050 }, /* R35 - Left out Mix (2) */
  58. { 36, 0x0050 }, /* R36 - Right out Mix (1) */
  59. { 37, 0x0050 }, /* R37 - Right Out Mix (2) */
  60. { 38, 0x0050 }, /* R38 - Mono out Mix (1) */
  61. { 39, 0x0050 }, /* R39 - Mono out Mix (2) */
  62. { 40, 0x0079 }, /* R40 - LOUT2 volume */
  63. { 41, 0x0079 }, /* R41 - ROUT2 volume */
  64. { 42, 0x0079 }, /* R42 - MONOOUT volume */
  65. { 43, 0x0000 }, /* R43 - Clocking / PLL */
  66. { 44, 0x0103 }, /* R44 - PLL Control 1 */
  67. { 45, 0x0024 }, /* R45 - PLL Control 2 */
  68. { 46, 0x01BA }, /* R46 - PLL Control 3 */
  69. { 59, 0x0000 }, /* R59 - PLL Control 4 */
  70. };
  71. static bool wm8955_writeable(struct device *dev, unsigned int reg)
  72. {
  73. switch (reg) {
  74. case WM8955_LOUT1_VOLUME:
  75. case WM8955_ROUT1_VOLUME:
  76. case WM8955_DAC_CONTROL:
  77. case WM8955_AUDIO_INTERFACE:
  78. case WM8955_SAMPLE_RATE:
  79. case WM8955_LEFT_DAC_VOLUME:
  80. case WM8955_RIGHT_DAC_VOLUME:
  81. case WM8955_BASS_CONTROL:
  82. case WM8955_TREBLE_CONTROL:
  83. case WM8955_RESET:
  84. case WM8955_ADDITIONAL_CONTROL_1:
  85. case WM8955_ADDITIONAL_CONTROL_2:
  86. case WM8955_POWER_MANAGEMENT_1:
  87. case WM8955_POWER_MANAGEMENT_2:
  88. case WM8955_ADDITIONAL_CONTROL_3:
  89. case WM8955_LEFT_OUT_MIX_1:
  90. case WM8955_LEFT_OUT_MIX_2:
  91. case WM8955_RIGHT_OUT_MIX_1:
  92. case WM8955_RIGHT_OUT_MIX_2:
  93. case WM8955_MONO_OUT_MIX_1:
  94. case WM8955_MONO_OUT_MIX_2:
  95. case WM8955_LOUT2_VOLUME:
  96. case WM8955_ROUT2_VOLUME:
  97. case WM8955_MONOOUT_VOLUME:
  98. case WM8955_CLOCKING_PLL:
  99. case WM8955_PLL_CONTROL_1:
  100. case WM8955_PLL_CONTROL_2:
  101. case WM8955_PLL_CONTROL_3:
  102. case WM8955_PLL_CONTROL_4:
  103. return true;
  104. default:
  105. return false;
  106. }
  107. }
  108. static bool wm8955_volatile(struct device *dev, unsigned int reg)
  109. {
  110. switch (reg) {
  111. case WM8955_RESET:
  112. return true;
  113. default:
  114. return false;
  115. }
  116. }
  117. static int wm8955_reset(struct snd_soc_component *component)
  118. {
  119. return snd_soc_component_write(component, WM8955_RESET, 0);
  120. }
  121. struct pll_factors {
  122. int n;
  123. int k;
  124. int outdiv;
  125. };
  126. /* The size in bits of the FLL divide multiplied by 10
  127. * to allow rounding later */
  128. #define FIXED_FLL_SIZE ((1 << 22) * 10)
  129. static int wm8955_pll_factors(struct device *dev,
  130. int Fref, int Fout, struct pll_factors *pll)
  131. {
  132. u64 Kpart;
  133. unsigned int K, Ndiv, Nmod, target;
  134. dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
  135. /* The oscilator should run at should be 90-100MHz, and
  136. * there's a divide by 4 plus an optional divide by 2 in the
  137. * output path to generate the system clock. The clock table
  138. * is sortd so we should always generate a suitable target. */
  139. target = Fout * 4;
  140. if (target < 90000000) {
  141. pll->outdiv = 1;
  142. target *= 2;
  143. } else {
  144. pll->outdiv = 0;
  145. }
  146. WARN_ON(target < 90000000 || target > 100000000);
  147. dev_dbg(dev, "Fvco=%dHz\n", target);
  148. /* Now, calculate N.K */
  149. Ndiv = target / Fref;
  150. pll->n = Ndiv;
  151. Nmod = target % Fref;
  152. dev_dbg(dev, "Nmod=%d\n", Nmod);
  153. /* Calculate fractional part - scale up so we can round. */
  154. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  155. do_div(Kpart, Fref);
  156. K = Kpart & 0xFFFFFFFF;
  157. if ((K % 10) >= 5)
  158. K += 5;
  159. /* Move down to proper range now rounding is done */
  160. pll->k = K / 10;
  161. dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
  162. return 0;
  163. }
  164. /* Lookup table specifying SRATE (table 25 in datasheet); some of the
  165. * output frequencies have been rounded to the standard frequencies
  166. * they are intended to match where the error is slight. */
  167. static struct {
  168. int mclk;
  169. int fs;
  170. int usb;
  171. int sr;
  172. } clock_cfgs[] = {
  173. { 18432000, 8000, 0, 3, },
  174. { 18432000, 12000, 0, 9, },
  175. { 18432000, 16000, 0, 11, },
  176. { 18432000, 24000, 0, 29, },
  177. { 18432000, 32000, 0, 13, },
  178. { 18432000, 48000, 0, 1, },
  179. { 18432000, 96000, 0, 15, },
  180. { 16934400, 8018, 0, 19, },
  181. { 16934400, 11025, 0, 25, },
  182. { 16934400, 22050, 0, 27, },
  183. { 16934400, 44100, 0, 17, },
  184. { 16934400, 88200, 0, 31, },
  185. { 12000000, 8000, 1, 2, },
  186. { 12000000, 11025, 1, 25, },
  187. { 12000000, 12000, 1, 8, },
  188. { 12000000, 16000, 1, 10, },
  189. { 12000000, 22050, 1, 27, },
  190. { 12000000, 24000, 1, 28, },
  191. { 12000000, 32000, 1, 12, },
  192. { 12000000, 44100, 1, 17, },
  193. { 12000000, 48000, 1, 0, },
  194. { 12000000, 88200, 1, 31, },
  195. { 12000000, 96000, 1, 14, },
  196. { 12288000, 8000, 0, 2, },
  197. { 12288000, 12000, 0, 8, },
  198. { 12288000, 16000, 0, 10, },
  199. { 12288000, 24000, 0, 28, },
  200. { 12288000, 32000, 0, 12, },
  201. { 12288000, 48000, 0, 0, },
  202. { 12288000, 96000, 0, 14, },
  203. { 12289600, 8018, 0, 18, },
  204. { 12289600, 11025, 0, 24, },
  205. { 12289600, 22050, 0, 26, },
  206. { 11289600, 44100, 0, 16, },
  207. { 11289600, 88200, 0, 31, },
  208. };
  209. static int wm8955_configure_clocking(struct snd_soc_component *component)
  210. {
  211. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  212. int i, ret, val;
  213. int clocking = 0;
  214. int srate = 0;
  215. int sr = -1;
  216. struct pll_factors pll;
  217. /* If we're not running a sample rate currently just pick one */
  218. if (wm8955->fs == 0)
  219. wm8955->fs = 8000;
  220. /* Can we generate an exact output? */
  221. for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
  222. if (wm8955->fs != clock_cfgs[i].fs)
  223. continue;
  224. sr = i;
  225. if (wm8955->mclk_rate == clock_cfgs[i].mclk)
  226. break;
  227. }
  228. /* We should never get here with an unsupported sample rate */
  229. if (sr == -1) {
  230. dev_err(component->dev, "Sample rate %dHz unsupported\n",
  231. wm8955->fs);
  232. WARN_ON(sr == -1);
  233. return -EINVAL;
  234. }
  235. if (i == ARRAY_SIZE(clock_cfgs)) {
  236. /* If we can't generate the right clock from MCLK then
  237. * we should configure the PLL to supply us with an
  238. * appropriate clock.
  239. */
  240. clocking |= WM8955_MCLKSEL;
  241. /* Use the last divider configuration we saw for the
  242. * sample rate. */
  243. ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate,
  244. clock_cfgs[sr].mclk, &pll);
  245. if (ret != 0) {
  246. dev_err(component->dev,
  247. "Unable to generate %dHz from %dHz MCLK\n",
  248. wm8955->fs, wm8955->mclk_rate);
  249. return -EINVAL;
  250. }
  251. snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1,
  252. WM8955_N_MASK | WM8955_K_21_18_MASK,
  253. (pll.n << WM8955_N_SHIFT) |
  254. pll.k >> 18);
  255. snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2,
  256. WM8955_K_17_9_MASK,
  257. (pll.k >> 9) & WM8955_K_17_9_MASK);
  258. snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3,
  259. WM8955_K_8_0_MASK,
  260. pll.k & WM8955_K_8_0_MASK);
  261. if (pll.k)
  262. snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
  263. WM8955_KEN, WM8955_KEN);
  264. else
  265. snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
  266. WM8955_KEN, 0);
  267. if (pll.outdiv)
  268. val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
  269. else
  270. val = WM8955_PLL_RB;
  271. /* Now start the PLL running */
  272. snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
  273. WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
  274. snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
  275. WM8955_PLLEN, WM8955_PLLEN);
  276. }
  277. srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
  278. snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
  279. WM8955_USB | WM8955_SR_MASK, srate);
  280. snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
  281. WM8955_MCLKSEL, clocking);
  282. return 0;
  283. }
  284. static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
  285. struct snd_kcontrol *kcontrol, int event)
  286. {
  287. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  288. int ret = 0;
  289. /* Always disable the clocks - if we're doing reconfiguration this
  290. * avoids misclocking.
  291. */
  292. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  293. WM8955_DIGENB, 0);
  294. snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
  295. WM8955_PLL_RB | WM8955_PLLEN, 0);
  296. switch (event) {
  297. case SND_SOC_DAPM_POST_PMD:
  298. break;
  299. case SND_SOC_DAPM_PRE_PMU:
  300. ret = wm8955_configure_clocking(component);
  301. break;
  302. default:
  303. ret = -EINVAL;
  304. break;
  305. }
  306. return ret;
  307. }
  308. static int deemph_settings[] = { 0, 32000, 44100, 48000 };
  309. static int wm8955_set_deemph(struct snd_soc_component *component)
  310. {
  311. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  312. int val, i, best;
  313. /* If we're using deemphasis select the nearest available sample
  314. * rate.
  315. */
  316. if (wm8955->deemph) {
  317. best = 1;
  318. for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
  319. if (abs(deemph_settings[i] - wm8955->fs) <
  320. abs(deemph_settings[best] - wm8955->fs))
  321. best = i;
  322. }
  323. val = best << WM8955_DEEMPH_SHIFT;
  324. } else {
  325. val = 0;
  326. }
  327. dev_dbg(component->dev, "Set deemphasis %d\n", val);
  328. return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL,
  329. WM8955_DEEMPH_MASK, val);
  330. }
  331. static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
  332. struct snd_ctl_elem_value *ucontrol)
  333. {
  334. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  335. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  336. ucontrol->value.integer.value[0] = wm8955->deemph;
  337. return 0;
  338. }
  339. static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
  340. struct snd_ctl_elem_value *ucontrol)
  341. {
  342. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  343. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  344. unsigned int deemph = ucontrol->value.integer.value[0];
  345. if (deemph > 1)
  346. return -EINVAL;
  347. wm8955->deemph = deemph;
  348. return wm8955_set_deemph(component);
  349. }
  350. static const char *bass_mode_text[] = {
  351. "Linear", "Adaptive",
  352. };
  353. static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text);
  354. static const char *bass_cutoff_text[] = {
  355. "Low", "High"
  356. };
  357. static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6,
  358. bass_cutoff_text);
  359. static const char *treble_cutoff_text[] = {
  360. "High", "Low"
  361. };
  362. static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2,
  363. treble_cutoff_text);
  364. static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  365. static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
  366. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  367. static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
  368. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  369. static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
  370. static const struct snd_kcontrol_new wm8955_snd_controls[] = {
  371. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
  372. WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
  373. SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
  374. atten_tlv),
  375. SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
  376. wm8955_get_deemph, wm8955_put_deemph),
  377. SOC_ENUM("Bass Mode", bass_mode),
  378. SOC_ENUM("Bass Cutoff", bass_cutoff),
  379. SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
  380. SOC_ENUM("Treble Cutoff", treble_cutoff),
  381. SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
  382. SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
  383. bypass_tlv),
  384. SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
  385. bypass_tlv),
  386. SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
  387. bypass_tlv),
  388. SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
  389. bypass_tlv),
  390. /* Not a stereo pair so they line up with the DAPM switches */
  391. SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
  392. mono_tlv),
  393. SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
  394. mono_tlv),
  395. SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
  396. WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
  397. SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
  398. WM8955_ROUT1_VOLUME, 7, 1, 0),
  399. SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
  400. WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
  401. SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
  402. WM8955_ROUT2_VOLUME, 7, 1, 0),
  403. SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
  404. SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
  405. };
  406. static const struct snd_kcontrol_new lmixer[] = {
  407. SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
  408. SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
  409. SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
  410. SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
  411. };
  412. static const struct snd_kcontrol_new rmixer[] = {
  413. SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
  414. SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
  415. SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
  416. SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
  417. };
  418. static const struct snd_kcontrol_new mmixer[] = {
  419. SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
  420. SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
  421. SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
  422. SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
  423. };
  424. static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
  425. SND_SOC_DAPM_INPUT("MONOIN-"),
  426. SND_SOC_DAPM_INPUT("MONOIN+"),
  427. SND_SOC_DAPM_INPUT("LINEINR"),
  428. SND_SOC_DAPM_INPUT("LINEINL"),
  429. SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  430. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
  431. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  432. SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
  433. SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
  434. SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
  435. SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
  436. SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
  437. SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
  438. SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
  439. SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
  440. SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
  441. /* The names are chosen to make the control names nice */
  442. SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
  443. lmixer, ARRAY_SIZE(lmixer)),
  444. SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
  445. rmixer, ARRAY_SIZE(rmixer)),
  446. SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
  447. mmixer, ARRAY_SIZE(mmixer)),
  448. SND_SOC_DAPM_OUTPUT("LOUT1"),
  449. SND_SOC_DAPM_OUTPUT("ROUT1"),
  450. SND_SOC_DAPM_OUTPUT("LOUT2"),
  451. SND_SOC_DAPM_OUTPUT("ROUT2"),
  452. SND_SOC_DAPM_OUTPUT("MONOOUT"),
  453. SND_SOC_DAPM_OUTPUT("OUT3"),
  454. };
  455. static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
  456. { "DACL", NULL, "SYSCLK" },
  457. { "DACR", NULL, "SYSCLK" },
  458. { "Mono Input", NULL, "MONOIN-" },
  459. { "Mono Input", NULL, "MONOIN+" },
  460. { "Left", "Playback Switch", "DACL" },
  461. { "Left", "Right Playback Switch", "DACR" },
  462. { "Left", "Bypass Switch", "LINEINL" },
  463. { "Left", "Mono Switch", "Mono Input" },
  464. { "Right", "Playback Switch", "DACR" },
  465. { "Right", "Left Playback Switch", "DACL" },
  466. { "Right", "Bypass Switch", "LINEINR" },
  467. { "Right", "Mono Switch", "Mono Input" },
  468. { "Mono", "Left Playback Switch", "DACL" },
  469. { "Mono", "Right Playback Switch", "DACR" },
  470. { "Mono", "Left Bypass Switch", "LINEINL" },
  471. { "Mono", "Right Bypass Switch", "LINEINR" },
  472. { "LOUT1 PGA", NULL, "Left" },
  473. { "LOUT1", NULL, "TSDEN" },
  474. { "LOUT1", NULL, "LOUT1 PGA" },
  475. { "ROUT1 PGA", NULL, "Right" },
  476. { "ROUT1", NULL, "TSDEN" },
  477. { "ROUT1", NULL, "ROUT1 PGA" },
  478. { "LOUT2 PGA", NULL, "Left" },
  479. { "LOUT2", NULL, "TSDEN" },
  480. { "LOUT2", NULL, "LOUT2 PGA" },
  481. { "ROUT2 PGA", NULL, "Right" },
  482. { "ROUT2", NULL, "TSDEN" },
  483. { "ROUT2", NULL, "ROUT2 PGA" },
  484. { "MOUT PGA", NULL, "Mono" },
  485. { "MONOOUT", NULL, "MOUT PGA" },
  486. /* OUT3 not currently implemented */
  487. { "OUT3", NULL, "OUT3 PGA" },
  488. };
  489. static int wm8955_hw_params(struct snd_pcm_substream *substream,
  490. struct snd_pcm_hw_params *params,
  491. struct snd_soc_dai *dai)
  492. {
  493. struct snd_soc_component *component = dai->component;
  494. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  495. int ret;
  496. int wl;
  497. switch (params_width(params)) {
  498. case 16:
  499. wl = 0;
  500. break;
  501. case 20:
  502. wl = 0x4;
  503. break;
  504. case 24:
  505. wl = 0x8;
  506. break;
  507. case 32:
  508. wl = 0xc;
  509. break;
  510. default:
  511. return -EINVAL;
  512. }
  513. snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
  514. WM8955_WL_MASK, wl);
  515. wm8955->fs = params_rate(params);
  516. wm8955_set_deemph(component);
  517. /* If the chip is clocked then disable the clocks and force a
  518. * reconfiguration, otherwise DAPM will power up the
  519. * clocks for us later. */
  520. ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1);
  521. if (ret < 0)
  522. return ret;
  523. if (ret & WM8955_DIGENB) {
  524. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  525. WM8955_DIGENB, 0);
  526. snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
  527. WM8955_PLL_RB | WM8955_PLLEN, 0);
  528. wm8955_configure_clocking(component);
  529. }
  530. return 0;
  531. }
  532. static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  533. unsigned int freq, int dir)
  534. {
  535. struct snd_soc_component *component = dai->component;
  536. struct wm8955_priv *priv = snd_soc_component_get_drvdata(component);
  537. int div;
  538. switch (clk_id) {
  539. case WM8955_CLK_MCLK:
  540. if (freq > 15000000) {
  541. priv->mclk_rate = freq /= 2;
  542. div = WM8955_MCLKDIV2;
  543. } else {
  544. priv->mclk_rate = freq;
  545. div = 0;
  546. }
  547. snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
  548. WM8955_MCLKDIV2, div);
  549. break;
  550. default:
  551. return -EINVAL;
  552. }
  553. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  554. return 0;
  555. }
  556. static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  557. {
  558. struct snd_soc_component *component = dai->component;
  559. u16 aif = 0;
  560. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  561. case SND_SOC_DAIFMT_CBS_CFS:
  562. break;
  563. case SND_SOC_DAIFMT_CBM_CFM:
  564. aif |= WM8955_MS;
  565. break;
  566. default:
  567. return -EINVAL;
  568. }
  569. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  570. case SND_SOC_DAIFMT_DSP_B:
  571. aif |= WM8955_LRP;
  572. fallthrough;
  573. case SND_SOC_DAIFMT_DSP_A:
  574. aif |= 0x3;
  575. break;
  576. case SND_SOC_DAIFMT_I2S:
  577. aif |= 0x2;
  578. break;
  579. case SND_SOC_DAIFMT_RIGHT_J:
  580. break;
  581. case SND_SOC_DAIFMT_LEFT_J:
  582. aif |= 0x1;
  583. break;
  584. default:
  585. return -EINVAL;
  586. }
  587. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  588. case SND_SOC_DAIFMT_DSP_A:
  589. case SND_SOC_DAIFMT_DSP_B:
  590. /* frame inversion not valid for DSP modes */
  591. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  592. case SND_SOC_DAIFMT_NB_NF:
  593. break;
  594. case SND_SOC_DAIFMT_IB_NF:
  595. aif |= WM8955_BCLKINV;
  596. break;
  597. default:
  598. return -EINVAL;
  599. }
  600. break;
  601. case SND_SOC_DAIFMT_I2S:
  602. case SND_SOC_DAIFMT_RIGHT_J:
  603. case SND_SOC_DAIFMT_LEFT_J:
  604. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  605. case SND_SOC_DAIFMT_NB_NF:
  606. break;
  607. case SND_SOC_DAIFMT_IB_IF:
  608. aif |= WM8955_BCLKINV | WM8955_LRP;
  609. break;
  610. case SND_SOC_DAIFMT_IB_NF:
  611. aif |= WM8955_BCLKINV;
  612. break;
  613. case SND_SOC_DAIFMT_NB_IF:
  614. aif |= WM8955_LRP;
  615. break;
  616. default:
  617. return -EINVAL;
  618. }
  619. break;
  620. default:
  621. return -EINVAL;
  622. }
  623. snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
  624. WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
  625. WM8955_LRP, aif);
  626. return 0;
  627. }
  628. static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  629. {
  630. struct snd_soc_component *component = codec_dai->component;
  631. int val;
  632. if (mute)
  633. val = WM8955_DACMU;
  634. else
  635. val = 0;
  636. snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val);
  637. return 0;
  638. }
  639. static int wm8955_set_bias_level(struct snd_soc_component *component,
  640. enum snd_soc_bias_level level)
  641. {
  642. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  643. int ret;
  644. switch (level) {
  645. case SND_SOC_BIAS_ON:
  646. break;
  647. case SND_SOC_BIAS_PREPARE:
  648. /* VMID resistance 2*50k */
  649. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  650. WM8955_VMIDSEL_MASK,
  651. 0x1 << WM8955_VMIDSEL_SHIFT);
  652. /* Default bias current */
  653. snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
  654. WM8955_VSEL_MASK,
  655. 0x2 << WM8955_VSEL_SHIFT);
  656. break;
  657. case SND_SOC_BIAS_STANDBY:
  658. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  659. ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
  660. wm8955->supplies);
  661. if (ret != 0) {
  662. dev_err(component->dev,
  663. "Failed to enable supplies: %d\n",
  664. ret);
  665. return ret;
  666. }
  667. regcache_sync(wm8955->regmap);
  668. /* Enable VREF and VMID */
  669. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  670. WM8955_VREF |
  671. WM8955_VMIDSEL_MASK,
  672. WM8955_VREF |
  673. 0x3 << WM8955_VREF_SHIFT);
  674. /* Let VMID ramp */
  675. msleep(500);
  676. /* High resistance VROI to maintain outputs */
  677. snd_soc_component_update_bits(component,
  678. WM8955_ADDITIONAL_CONTROL_3,
  679. WM8955_VROI, WM8955_VROI);
  680. }
  681. /* Maintain VMID with 2*250k */
  682. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  683. WM8955_VMIDSEL_MASK,
  684. 0x2 << WM8955_VMIDSEL_SHIFT);
  685. /* Minimum bias current */
  686. snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
  687. WM8955_VSEL_MASK, 0);
  688. break;
  689. case SND_SOC_BIAS_OFF:
  690. /* Low resistance VROI to help discharge */
  691. snd_soc_component_update_bits(component,
  692. WM8955_ADDITIONAL_CONTROL_3,
  693. WM8955_VROI, 0);
  694. /* Turn off VMID and VREF */
  695. snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
  696. WM8955_VREF |
  697. WM8955_VMIDSEL_MASK, 0);
  698. regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
  699. wm8955->supplies);
  700. break;
  701. }
  702. return 0;
  703. }
  704. #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
  705. #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  706. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  707. static const struct snd_soc_dai_ops wm8955_dai_ops = {
  708. .set_sysclk = wm8955_set_sysclk,
  709. .set_fmt = wm8955_set_fmt,
  710. .hw_params = wm8955_hw_params,
  711. .mute_stream = wm8955_mute,
  712. .no_capture_mute = 1,
  713. };
  714. static struct snd_soc_dai_driver wm8955_dai = {
  715. .name = "wm8955-hifi",
  716. .playback = {
  717. .stream_name = "Playback",
  718. .channels_min = 2,
  719. .channels_max = 2,
  720. .rates = WM8955_RATES,
  721. .formats = WM8955_FORMATS,
  722. },
  723. .ops = &wm8955_dai_ops,
  724. };
  725. static int wm8955_probe(struct snd_soc_component *component)
  726. {
  727. struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
  728. struct wm8955_pdata *pdata = dev_get_platdata(component->dev);
  729. int ret, i;
  730. for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
  731. wm8955->supplies[i].supply = wm8955_supply_names[i];
  732. ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies),
  733. wm8955->supplies);
  734. if (ret != 0) {
  735. dev_err(component->dev, "Failed to request supplies: %d\n", ret);
  736. return ret;
  737. }
  738. ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
  739. wm8955->supplies);
  740. if (ret != 0) {
  741. dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
  742. return ret;
  743. }
  744. ret = wm8955_reset(component);
  745. if (ret < 0) {
  746. dev_err(component->dev, "Failed to issue reset: %d\n", ret);
  747. goto err_enable;
  748. }
  749. /* Change some default settings - latch VU and enable ZC */
  750. snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME,
  751. WM8955_LDVU, WM8955_LDVU);
  752. snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME,
  753. WM8955_RDVU, WM8955_RDVU);
  754. snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME,
  755. WM8955_LO1VU | WM8955_LO1ZC,
  756. WM8955_LO1VU | WM8955_LO1ZC);
  757. snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME,
  758. WM8955_RO1VU | WM8955_RO1ZC,
  759. WM8955_RO1VU | WM8955_RO1ZC);
  760. snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME,
  761. WM8955_LO2VU | WM8955_LO2ZC,
  762. WM8955_LO2VU | WM8955_LO2ZC);
  763. snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME,
  764. WM8955_RO2VU | WM8955_RO2ZC,
  765. WM8955_RO2VU | WM8955_RO2ZC);
  766. snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME,
  767. WM8955_MOZC, WM8955_MOZC);
  768. /* Also enable adaptive bass boost by default */
  769. snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
  770. /* Set platform data values */
  771. if (pdata) {
  772. if (pdata->out2_speaker)
  773. snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2,
  774. WM8955_ROUT2INV, WM8955_ROUT2INV);
  775. if (pdata->monoin_diff)
  776. snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1,
  777. WM8955_DMEN, WM8955_DMEN);
  778. }
  779. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  780. /* Bias level configuration will have done an extra enable */
  781. regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
  782. return 0;
  783. err_enable:
  784. regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
  785. return ret;
  786. }
  787. static const struct snd_soc_component_driver soc_component_dev_wm8955 = {
  788. .probe = wm8955_probe,
  789. .set_bias_level = wm8955_set_bias_level,
  790. .controls = wm8955_snd_controls,
  791. .num_controls = ARRAY_SIZE(wm8955_snd_controls),
  792. .dapm_widgets = wm8955_dapm_widgets,
  793. .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets),
  794. .dapm_routes = wm8955_dapm_routes,
  795. .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes),
  796. .suspend_bias_off = 1,
  797. .idle_bias_on = 1,
  798. .use_pmdown_time = 1,
  799. .endianness = 1,
  800. };
  801. static const struct regmap_config wm8955_regmap = {
  802. .reg_bits = 7,
  803. .val_bits = 9,
  804. .max_register = WM8955_MAX_REGISTER,
  805. .volatile_reg = wm8955_volatile,
  806. .writeable_reg = wm8955_writeable,
  807. .cache_type = REGCACHE_RBTREE,
  808. .reg_defaults = wm8955_reg_defaults,
  809. .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
  810. };
  811. static int wm8955_i2c_probe(struct i2c_client *i2c)
  812. {
  813. struct wm8955_priv *wm8955;
  814. int ret;
  815. wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
  816. GFP_KERNEL);
  817. if (wm8955 == NULL)
  818. return -ENOMEM;
  819. wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap);
  820. if (IS_ERR(wm8955->regmap)) {
  821. ret = PTR_ERR(wm8955->regmap);
  822. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  823. ret);
  824. return ret;
  825. }
  826. i2c_set_clientdata(i2c, wm8955);
  827. ret = devm_snd_soc_register_component(&i2c->dev,
  828. &soc_component_dev_wm8955, &wm8955_dai, 1);
  829. return ret;
  830. }
  831. static const struct i2c_device_id wm8955_i2c_id[] = {
  832. { "wm8955", 0 },
  833. { }
  834. };
  835. MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
  836. static struct i2c_driver wm8955_i2c_driver = {
  837. .driver = {
  838. .name = "wm8955",
  839. },
  840. .probe_new = wm8955_i2c_probe,
  841. .id_table = wm8955_i2c_id,
  842. };
  843. module_i2c_driver(wm8955_i2c_driver);
  844. MODULE_DESCRIPTION("ASoC WM8955 driver");
  845. MODULE_AUTHOR("Mark Brown <[email protected]>");
  846. MODULE_LICENSE("GPL");