wm8904.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8904.c -- WM8904 ALSA SoC Audio driver
  4. *
  5. * Copyright 2009-12 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/initval.h>
  23. #include <sound/tlv.h>
  24. #include <sound/wm8904.h>
  25. #include "wm8904.h"
  26. enum wm8904_type {
  27. WM8904,
  28. WM8912,
  29. };
  30. #define WM8904_NUM_DCS_CHANNELS 4
  31. #define WM8904_NUM_SUPPLIES 5
  32. static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
  33. "DCVDD",
  34. "DBVDD",
  35. "AVDD",
  36. "CPVDD",
  37. "MICVDD",
  38. };
  39. /* codec private data */
  40. struct wm8904_priv {
  41. struct regmap *regmap;
  42. struct clk *mclk;
  43. enum wm8904_type devtype;
  44. struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
  45. struct wm8904_pdata *pdata;
  46. int deemph;
  47. /* Platform provided DRC configuration */
  48. const char **drc_texts;
  49. int drc_cfg;
  50. struct soc_enum drc_enum;
  51. /* Platform provided ReTune mobile configuration */
  52. int num_retune_mobile_texts;
  53. const char **retune_mobile_texts;
  54. int retune_mobile_cfg;
  55. struct soc_enum retune_mobile_enum;
  56. /* FLL setup */
  57. int fll_src;
  58. int fll_fref;
  59. int fll_fout;
  60. /* Clocking configuration */
  61. unsigned int mclk_rate;
  62. int sysclk_src;
  63. unsigned int sysclk_rate;
  64. int tdm_width;
  65. int tdm_slots;
  66. int bclk;
  67. int fs;
  68. /* DC servo configuration - cached offset values */
  69. int dcs_state[WM8904_NUM_DCS_CHANNELS];
  70. };
  71. static const struct reg_default wm8904_reg_defaults[] = {
  72. { 4, 0x0018 }, /* R4 - Bias Control 0 */
  73. { 5, 0x0000 }, /* R5 - VMID Control 0 */
  74. { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
  75. { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
  76. { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
  77. { 9, 0x9696 }, /* R9 - mic Filter Control */
  78. { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
  79. { 12, 0x0000 }, /* R12 - Power Management 0 */
  80. { 14, 0x0000 }, /* R14 - Power Management 2 */
  81. { 15, 0x0000 }, /* R15 - Power Management 3 */
  82. { 18, 0x0000 }, /* R18 - Power Management 6 */
  83. { 20, 0x945E }, /* R20 - Clock Rates 0 */
  84. { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
  85. { 22, 0x0006 }, /* R22 - Clock Rates 2 */
  86. { 24, 0x0050 }, /* R24 - Audio Interface 0 */
  87. { 25, 0x000A }, /* R25 - Audio Interface 1 */
  88. { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
  89. { 27, 0x0040 }, /* R27 - Audio Interface 3 */
  90. { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
  91. { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
  92. { 32, 0x0000 }, /* R32 - DAC Digital 0 */
  93. { 33, 0x0008 }, /* R33 - DAC Digital 1 */
  94. { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
  95. { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
  96. { 38, 0x0010 }, /* R38 - ADC Digital 0 */
  97. { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
  98. { 40, 0x01AF }, /* R40 - DRC 0 */
  99. { 41, 0x3248 }, /* R41 - DRC 1 */
  100. { 42, 0x0000 }, /* R42 - DRC 2 */
  101. { 43, 0x0000 }, /* R43 - DRC 3 */
  102. { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
  103. { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
  104. { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
  105. { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
  106. { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
  107. { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
  108. { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
  109. { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
  110. { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
  111. { 67, 0x0000 }, /* R67 - DC Servo 0 */
  112. { 69, 0xAAAA }, /* R69 - DC Servo 2 */
  113. { 71, 0xAAAA }, /* R71 - DC Servo 4 */
  114. { 72, 0xAAAA }, /* R72 - DC Servo 5 */
  115. { 90, 0x0000 }, /* R90 - Analogue HP 0 */
  116. { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
  117. { 98, 0x0000 }, /* R98 - Charge Pump 0 */
  118. { 104, 0x0004 }, /* R104 - Class W 0 */
  119. { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
  120. { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
  121. { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
  122. { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
  123. { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
  124. { 116, 0x0000 }, /* R116 - FLL Control 1 */
  125. { 117, 0x0007 }, /* R117 - FLL Control 2 */
  126. { 118, 0x0000 }, /* R118 - FLL Control 3 */
  127. { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
  128. { 120, 0x0004 }, /* R120 - FLL Control 5 */
  129. { 121, 0x0014 }, /* R121 - GPIO Control 1 */
  130. { 122, 0x0010 }, /* R122 - GPIO Control 2 */
  131. { 123, 0x0010 }, /* R123 - GPIO Control 3 */
  132. { 124, 0x0000 }, /* R124 - GPIO Control 4 */
  133. { 126, 0x0000 }, /* R126 - Digital Pulls */
  134. { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
  135. { 129, 0x0000 }, /* R129 - Interrupt Polarity */
  136. { 130, 0x0000 }, /* R130 - Interrupt Debounce */
  137. { 134, 0x0000 }, /* R134 - EQ1 */
  138. { 135, 0x000C }, /* R135 - EQ2 */
  139. { 136, 0x000C }, /* R136 - EQ3 */
  140. { 137, 0x000C }, /* R137 - EQ4 */
  141. { 138, 0x000C }, /* R138 - EQ5 */
  142. { 139, 0x000C }, /* R139 - EQ6 */
  143. { 140, 0x0FCA }, /* R140 - EQ7 */
  144. { 141, 0x0400 }, /* R141 - EQ8 */
  145. { 142, 0x00D8 }, /* R142 - EQ9 */
  146. { 143, 0x1EB5 }, /* R143 - EQ10 */
  147. { 144, 0xF145 }, /* R144 - EQ11 */
  148. { 145, 0x0B75 }, /* R145 - EQ12 */
  149. { 146, 0x01C5 }, /* R146 - EQ13 */
  150. { 147, 0x1C58 }, /* R147 - EQ14 */
  151. { 148, 0xF373 }, /* R148 - EQ15 */
  152. { 149, 0x0A54 }, /* R149 - EQ16 */
  153. { 150, 0x0558 }, /* R150 - EQ17 */
  154. { 151, 0x168E }, /* R151 - EQ18 */
  155. { 152, 0xF829 }, /* R152 - EQ19 */
  156. { 153, 0x07AD }, /* R153 - EQ20 */
  157. { 154, 0x1103 }, /* R154 - EQ21 */
  158. { 155, 0x0564 }, /* R155 - EQ22 */
  159. { 156, 0x0559 }, /* R156 - EQ23 */
  160. { 157, 0x4000 }, /* R157 - EQ24 */
  161. { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
  162. { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
  163. { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
  164. { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
  165. };
  166. static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
  167. {
  168. switch (reg) {
  169. case WM8904_SW_RESET_AND_ID:
  170. case WM8904_REVISION:
  171. case WM8904_DC_SERVO_1:
  172. case WM8904_DC_SERVO_6:
  173. case WM8904_DC_SERVO_7:
  174. case WM8904_DC_SERVO_8:
  175. case WM8904_DC_SERVO_9:
  176. case WM8904_DC_SERVO_READBACK_0:
  177. case WM8904_INTERRUPT_STATUS:
  178. return true;
  179. default:
  180. return false;
  181. }
  182. }
  183. static bool wm8904_readable_register(struct device *dev, unsigned int reg)
  184. {
  185. switch (reg) {
  186. case WM8904_SW_RESET_AND_ID:
  187. case WM8904_REVISION:
  188. case WM8904_BIAS_CONTROL_0:
  189. case WM8904_VMID_CONTROL_0:
  190. case WM8904_MIC_BIAS_CONTROL_0:
  191. case WM8904_MIC_BIAS_CONTROL_1:
  192. case WM8904_ANALOGUE_DAC_0:
  193. case WM8904_MIC_FILTER_CONTROL:
  194. case WM8904_ANALOGUE_ADC_0:
  195. case WM8904_POWER_MANAGEMENT_0:
  196. case WM8904_POWER_MANAGEMENT_2:
  197. case WM8904_POWER_MANAGEMENT_3:
  198. case WM8904_POWER_MANAGEMENT_6:
  199. case WM8904_CLOCK_RATES_0:
  200. case WM8904_CLOCK_RATES_1:
  201. case WM8904_CLOCK_RATES_2:
  202. case WM8904_AUDIO_INTERFACE_0:
  203. case WM8904_AUDIO_INTERFACE_1:
  204. case WM8904_AUDIO_INTERFACE_2:
  205. case WM8904_AUDIO_INTERFACE_3:
  206. case WM8904_DAC_DIGITAL_VOLUME_LEFT:
  207. case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
  208. case WM8904_DAC_DIGITAL_0:
  209. case WM8904_DAC_DIGITAL_1:
  210. case WM8904_ADC_DIGITAL_VOLUME_LEFT:
  211. case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
  212. case WM8904_ADC_DIGITAL_0:
  213. case WM8904_DIGITAL_MICROPHONE_0:
  214. case WM8904_DRC_0:
  215. case WM8904_DRC_1:
  216. case WM8904_DRC_2:
  217. case WM8904_DRC_3:
  218. case WM8904_ANALOGUE_LEFT_INPUT_0:
  219. case WM8904_ANALOGUE_RIGHT_INPUT_0:
  220. case WM8904_ANALOGUE_LEFT_INPUT_1:
  221. case WM8904_ANALOGUE_RIGHT_INPUT_1:
  222. case WM8904_ANALOGUE_OUT1_LEFT:
  223. case WM8904_ANALOGUE_OUT1_RIGHT:
  224. case WM8904_ANALOGUE_OUT2_LEFT:
  225. case WM8904_ANALOGUE_OUT2_RIGHT:
  226. case WM8904_ANALOGUE_OUT12_ZC:
  227. case WM8904_DC_SERVO_0:
  228. case WM8904_DC_SERVO_1:
  229. case WM8904_DC_SERVO_2:
  230. case WM8904_DC_SERVO_4:
  231. case WM8904_DC_SERVO_5:
  232. case WM8904_DC_SERVO_6:
  233. case WM8904_DC_SERVO_7:
  234. case WM8904_DC_SERVO_8:
  235. case WM8904_DC_SERVO_9:
  236. case WM8904_DC_SERVO_READBACK_0:
  237. case WM8904_ANALOGUE_HP_0:
  238. case WM8904_ANALOGUE_LINEOUT_0:
  239. case WM8904_CHARGE_PUMP_0:
  240. case WM8904_CLASS_W_0:
  241. case WM8904_WRITE_SEQUENCER_0:
  242. case WM8904_WRITE_SEQUENCER_1:
  243. case WM8904_WRITE_SEQUENCER_2:
  244. case WM8904_WRITE_SEQUENCER_3:
  245. case WM8904_WRITE_SEQUENCER_4:
  246. case WM8904_FLL_CONTROL_1:
  247. case WM8904_FLL_CONTROL_2:
  248. case WM8904_FLL_CONTROL_3:
  249. case WM8904_FLL_CONTROL_4:
  250. case WM8904_FLL_CONTROL_5:
  251. case WM8904_GPIO_CONTROL_1:
  252. case WM8904_GPIO_CONTROL_2:
  253. case WM8904_GPIO_CONTROL_3:
  254. case WM8904_GPIO_CONTROL_4:
  255. case WM8904_DIGITAL_PULLS:
  256. case WM8904_INTERRUPT_STATUS:
  257. case WM8904_INTERRUPT_STATUS_MASK:
  258. case WM8904_INTERRUPT_POLARITY:
  259. case WM8904_INTERRUPT_DEBOUNCE:
  260. case WM8904_EQ1:
  261. case WM8904_EQ2:
  262. case WM8904_EQ3:
  263. case WM8904_EQ4:
  264. case WM8904_EQ5:
  265. case WM8904_EQ6:
  266. case WM8904_EQ7:
  267. case WM8904_EQ8:
  268. case WM8904_EQ9:
  269. case WM8904_EQ10:
  270. case WM8904_EQ11:
  271. case WM8904_EQ12:
  272. case WM8904_EQ13:
  273. case WM8904_EQ14:
  274. case WM8904_EQ15:
  275. case WM8904_EQ16:
  276. case WM8904_EQ17:
  277. case WM8904_EQ18:
  278. case WM8904_EQ19:
  279. case WM8904_EQ20:
  280. case WM8904_EQ21:
  281. case WM8904_EQ22:
  282. case WM8904_EQ23:
  283. case WM8904_EQ24:
  284. case WM8904_CONTROL_INTERFACE_TEST_1:
  285. case WM8904_ADC_TEST_0:
  286. case WM8904_ANALOGUE_OUTPUT_BIAS_0:
  287. case WM8904_FLL_NCO_TEST_0:
  288. case WM8904_FLL_NCO_TEST_1:
  289. return true;
  290. default:
  291. return false;
  292. }
  293. }
  294. static int wm8904_configure_clocking(struct snd_soc_component *component)
  295. {
  296. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  297. unsigned int clock0, clock2, rate;
  298. /* Gate the clock while we're updating to avoid misclocking */
  299. clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
  300. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
  301. WM8904_SYSCLK_SRC, 0);
  302. /* This should be done on init() for bypass paths */
  303. switch (wm8904->sysclk_src) {
  304. case WM8904_CLK_MCLK:
  305. dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
  306. clock2 &= ~WM8904_SYSCLK_SRC;
  307. rate = wm8904->mclk_rate;
  308. /* Ensure the FLL is stopped */
  309. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  310. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  311. break;
  312. case WM8904_CLK_FLL:
  313. dev_dbg(component->dev, "Using %dHz FLL clock\n",
  314. wm8904->fll_fout);
  315. clock2 |= WM8904_SYSCLK_SRC;
  316. rate = wm8904->fll_fout;
  317. break;
  318. default:
  319. dev_err(component->dev, "System clock not configured\n");
  320. return -EINVAL;
  321. }
  322. /* SYSCLK shouldn't be over 13.5MHz */
  323. if (rate > 13500000) {
  324. clock0 = WM8904_MCLK_DIV;
  325. wm8904->sysclk_rate = rate / 2;
  326. } else {
  327. clock0 = 0;
  328. wm8904->sysclk_rate = rate;
  329. }
  330. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
  331. clock0);
  332. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
  333. WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
  334. dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
  335. return 0;
  336. }
  337. static void wm8904_set_drc(struct snd_soc_component *component)
  338. {
  339. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  340. struct wm8904_pdata *pdata = wm8904->pdata;
  341. int save, i;
  342. /* Save any enables; the configuration should clear them. */
  343. save = snd_soc_component_read(component, WM8904_DRC_0);
  344. for (i = 0; i < WM8904_DRC_REGS; i++)
  345. snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff,
  346. pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
  347. /* Reenable the DRC */
  348. snd_soc_component_update_bits(component, WM8904_DRC_0,
  349. WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
  350. }
  351. static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
  352. struct snd_ctl_elem_value *ucontrol)
  353. {
  354. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  355. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  356. struct wm8904_pdata *pdata = wm8904->pdata;
  357. int value = ucontrol->value.enumerated.item[0];
  358. if (value >= pdata->num_drc_cfgs)
  359. return -EINVAL;
  360. wm8904->drc_cfg = value;
  361. wm8904_set_drc(component);
  362. return 0;
  363. }
  364. static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
  365. struct snd_ctl_elem_value *ucontrol)
  366. {
  367. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  368. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  369. ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
  370. return 0;
  371. }
  372. static void wm8904_set_retune_mobile(struct snd_soc_component *component)
  373. {
  374. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  375. struct wm8904_pdata *pdata = wm8904->pdata;
  376. int best, best_val, save, i, cfg;
  377. if (!pdata || !wm8904->num_retune_mobile_texts)
  378. return;
  379. /* Find the version of the currently selected configuration
  380. * with the nearest sample rate. */
  381. cfg = wm8904->retune_mobile_cfg;
  382. best = 0;
  383. best_val = INT_MAX;
  384. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  385. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  386. wm8904->retune_mobile_texts[cfg]) == 0 &&
  387. abs(pdata->retune_mobile_cfgs[i].rate
  388. - wm8904->fs) < best_val) {
  389. best = i;
  390. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  391. - wm8904->fs);
  392. }
  393. }
  394. dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
  395. pdata->retune_mobile_cfgs[best].name,
  396. pdata->retune_mobile_cfgs[best].rate,
  397. wm8904->fs);
  398. /* The EQ will be disabled while reconfiguring it, remember the
  399. * current configuration.
  400. */
  401. save = snd_soc_component_read(component, WM8904_EQ1);
  402. for (i = 0; i < WM8904_EQ_REGS; i++)
  403. snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff,
  404. pdata->retune_mobile_cfgs[best].regs[i]);
  405. snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save);
  406. }
  407. static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  408. struct snd_ctl_elem_value *ucontrol)
  409. {
  410. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  411. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  412. struct wm8904_pdata *pdata = wm8904->pdata;
  413. int value = ucontrol->value.enumerated.item[0];
  414. if (value >= pdata->num_retune_mobile_cfgs)
  415. return -EINVAL;
  416. wm8904->retune_mobile_cfg = value;
  417. wm8904_set_retune_mobile(component);
  418. return 0;
  419. }
  420. static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  421. struct snd_ctl_elem_value *ucontrol)
  422. {
  423. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  424. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  425. ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
  426. return 0;
  427. }
  428. static int deemph_settings[] = { 0, 32000, 44100, 48000 };
  429. static int wm8904_set_deemph(struct snd_soc_component *component)
  430. {
  431. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  432. int val, i, best;
  433. /* If we're using deemphasis select the nearest available sample
  434. * rate.
  435. */
  436. if (wm8904->deemph) {
  437. best = 1;
  438. for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
  439. if (abs(deemph_settings[i] - wm8904->fs) <
  440. abs(deemph_settings[best] - wm8904->fs))
  441. best = i;
  442. }
  443. val = best << WM8904_DEEMPH_SHIFT;
  444. } else {
  445. val = 0;
  446. }
  447. dev_dbg(component->dev, "Set deemphasis %d\n", val);
  448. return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
  449. WM8904_DEEMPH_MASK, val);
  450. }
  451. static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
  452. struct snd_ctl_elem_value *ucontrol)
  453. {
  454. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  455. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  456. ucontrol->value.integer.value[0] = wm8904->deemph;
  457. return 0;
  458. }
  459. static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
  460. struct snd_ctl_elem_value *ucontrol)
  461. {
  462. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  463. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  464. unsigned int deemph = ucontrol->value.integer.value[0];
  465. if (deemph > 1)
  466. return -EINVAL;
  467. wm8904->deemph = deemph;
  468. return wm8904_set_deemph(component);
  469. }
  470. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  471. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  472. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  473. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  474. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  475. static const char *hpf_mode_text[] = {
  476. "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
  477. };
  478. static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
  479. hpf_mode_text);
  480. static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
  481. struct snd_ctl_elem_value *ucontrol)
  482. {
  483. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  484. unsigned int val;
  485. int ret;
  486. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  487. if (ret < 0)
  488. return ret;
  489. if (ucontrol->value.integer.value[0])
  490. val = 0;
  491. else
  492. val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
  493. snd_soc_component_update_bits(component, WM8904_ADC_TEST_0,
  494. WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
  495. val);
  496. return ret;
  497. }
  498. static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
  499. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
  500. WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
  501. /* No TLV since it depends on mode */
  502. SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
  503. WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
  504. SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
  505. WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
  506. SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
  507. SOC_ENUM("High Pass Filter Mode", hpf_mode),
  508. SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
  509. snd_soc_get_volsw, wm8904_adc_osr_put),
  510. };
  511. static const char *drc_path_text[] = {
  512. "ADC", "DAC"
  513. };
  514. static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
  515. static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
  516. SOC_SINGLE_TLV("Digital Playback Boost Volume",
  517. WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
  518. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
  519. WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
  520. SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
  521. WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
  522. SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
  523. WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
  524. SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
  525. WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
  526. SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
  527. WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
  528. SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
  529. WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
  530. SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
  531. WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
  532. SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
  533. SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
  534. SOC_ENUM("DRC Path", drc_path),
  535. SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
  536. SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
  537. wm8904_get_deemph, wm8904_put_deemph),
  538. };
  539. static const struct snd_kcontrol_new wm8904_snd_controls[] = {
  540. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
  541. sidetone_tlv),
  542. };
  543. static const struct snd_kcontrol_new wm8904_eq_controls[] = {
  544. SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
  545. SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
  546. SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
  547. SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
  548. SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
  549. };
  550. static int cp_event(struct snd_soc_dapm_widget *w,
  551. struct snd_kcontrol *kcontrol, int event)
  552. {
  553. if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
  554. return -EINVAL;
  555. /* Maximum startup time */
  556. udelay(500);
  557. return 0;
  558. }
  559. static int sysclk_event(struct snd_soc_dapm_widget *w,
  560. struct snd_kcontrol *kcontrol, int event)
  561. {
  562. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  563. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  564. switch (event) {
  565. case SND_SOC_DAPM_PRE_PMU:
  566. /* If we're using the FLL then we only start it when
  567. * required; we assume that the configuration has been
  568. * done previously and all we need to do is kick it
  569. * off.
  570. */
  571. switch (wm8904->sysclk_src) {
  572. case WM8904_CLK_FLL:
  573. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  574. WM8904_FLL_OSC_ENA,
  575. WM8904_FLL_OSC_ENA);
  576. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  577. WM8904_FLL_ENA,
  578. WM8904_FLL_ENA);
  579. break;
  580. default:
  581. break;
  582. }
  583. break;
  584. case SND_SOC_DAPM_POST_PMD:
  585. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  586. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  587. break;
  588. }
  589. return 0;
  590. }
  591. static int out_pga_event(struct snd_soc_dapm_widget *w,
  592. struct snd_kcontrol *kcontrol, int event)
  593. {
  594. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  595. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  596. int reg, val;
  597. int dcs_mask;
  598. int dcs_l, dcs_r;
  599. int dcs_l_reg, dcs_r_reg;
  600. int an_out_reg;
  601. int timeout;
  602. int pwr_reg;
  603. /* This code is shared between HP and LINEOUT; we do all our
  604. * power management in stereo pairs to avoid latency issues so
  605. * we reuse shift to identify which rather than strcmp() the
  606. * name. */
  607. reg = w->shift;
  608. switch (reg) {
  609. case WM8904_ANALOGUE_HP_0:
  610. pwr_reg = WM8904_POWER_MANAGEMENT_2;
  611. dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
  612. dcs_r_reg = WM8904_DC_SERVO_8;
  613. dcs_l_reg = WM8904_DC_SERVO_9;
  614. an_out_reg = WM8904_ANALOGUE_OUT1_LEFT;
  615. dcs_l = 0;
  616. dcs_r = 1;
  617. break;
  618. case WM8904_ANALOGUE_LINEOUT_0:
  619. pwr_reg = WM8904_POWER_MANAGEMENT_3;
  620. dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
  621. dcs_r_reg = WM8904_DC_SERVO_6;
  622. dcs_l_reg = WM8904_DC_SERVO_7;
  623. an_out_reg = WM8904_ANALOGUE_OUT2_LEFT;
  624. dcs_l = 2;
  625. dcs_r = 3;
  626. break;
  627. default:
  628. WARN(1, "Invalid reg %d\n", reg);
  629. return -EINVAL;
  630. }
  631. switch (event) {
  632. case SND_SOC_DAPM_PRE_PMU:
  633. /* Power on the PGAs */
  634. snd_soc_component_update_bits(component, pwr_reg,
  635. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  636. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
  637. /* Power on the amplifier */
  638. snd_soc_component_update_bits(component, reg,
  639. WM8904_HPL_ENA | WM8904_HPR_ENA,
  640. WM8904_HPL_ENA | WM8904_HPR_ENA);
  641. /* Enable the first stage */
  642. snd_soc_component_update_bits(component, reg,
  643. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
  644. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
  645. /* Power up the DC servo */
  646. snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
  647. dcs_mask, dcs_mask);
  648. /* Either calibrate the DC servo or restore cached state
  649. * if we have that.
  650. */
  651. if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
  652. dev_dbg(component->dev, "Restoring DC servo state\n");
  653. snd_soc_component_write(component, dcs_l_reg,
  654. wm8904->dcs_state[dcs_l]);
  655. snd_soc_component_write(component, dcs_r_reg,
  656. wm8904->dcs_state[dcs_r]);
  657. snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask);
  658. timeout = 20;
  659. } else {
  660. dev_dbg(component->dev, "Calibrating DC servo\n");
  661. snd_soc_component_write(component, WM8904_DC_SERVO_1,
  662. dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
  663. timeout = 500;
  664. }
  665. /* Wait for DC servo to complete */
  666. dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
  667. do {
  668. val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0);
  669. if ((val & dcs_mask) == dcs_mask)
  670. break;
  671. msleep(1);
  672. } while (--timeout);
  673. if ((val & dcs_mask) != dcs_mask)
  674. dev_warn(component->dev, "DC servo timed out\n");
  675. else
  676. dev_dbg(component->dev, "DC servo ready\n");
  677. /* Enable the output stage */
  678. snd_soc_component_update_bits(component, reg,
  679. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  680. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
  681. /* Update volume, requires PGA to be powered */
  682. val = snd_soc_component_read(component, an_out_reg);
  683. snd_soc_component_write(component, an_out_reg, val);
  684. break;
  685. case SND_SOC_DAPM_POST_PMU:
  686. /* Unshort the output itself */
  687. snd_soc_component_update_bits(component, reg,
  688. WM8904_HPL_RMV_SHORT |
  689. WM8904_HPR_RMV_SHORT,
  690. WM8904_HPL_RMV_SHORT |
  691. WM8904_HPR_RMV_SHORT);
  692. break;
  693. case SND_SOC_DAPM_PRE_PMD:
  694. /* Short the output */
  695. snd_soc_component_update_bits(component, reg,
  696. WM8904_HPL_RMV_SHORT |
  697. WM8904_HPR_RMV_SHORT, 0);
  698. break;
  699. case SND_SOC_DAPM_POST_PMD:
  700. /* Cache the DC servo configuration; this will be
  701. * invalidated if we change the configuration. */
  702. wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg);
  703. wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg);
  704. snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
  705. dcs_mask, 0);
  706. /* Disable the amplifier input and output stages */
  707. snd_soc_component_update_bits(component, reg,
  708. WM8904_HPL_ENA | WM8904_HPR_ENA |
  709. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
  710. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  711. 0);
  712. /* PGAs too */
  713. snd_soc_component_update_bits(component, pwr_reg,
  714. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  715. 0);
  716. break;
  717. }
  718. return 0;
  719. }
  720. static const char *input_mode_text[] = {
  721. "Single-Ended", "Differential Line", "Differential Mic"
  722. };
  723. static const char *lin_text[] = {
  724. "IN1L", "IN2L", "IN3L"
  725. };
  726. static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
  727. lin_text);
  728. static const struct snd_kcontrol_new lin_mux =
  729. SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
  730. static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
  731. lin_text);
  732. static const struct snd_kcontrol_new lin_inv_mux =
  733. SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum);
  734. static SOC_ENUM_SINGLE_DECL(lin_mode_enum,
  735. WM8904_ANALOGUE_LEFT_INPUT_1, 0,
  736. input_mode_text);
  737. static const struct snd_kcontrol_new lin_mode =
  738. SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum);
  739. static const char *rin_text[] = {
  740. "IN1R", "IN2R", "IN3R"
  741. };
  742. static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
  743. rin_text);
  744. static const struct snd_kcontrol_new rin_mux =
  745. SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
  746. static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
  747. rin_text);
  748. static const struct snd_kcontrol_new rin_inv_mux =
  749. SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum);
  750. static SOC_ENUM_SINGLE_DECL(rin_mode_enum,
  751. WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
  752. input_mode_text);
  753. static const struct snd_kcontrol_new rin_mode =
  754. SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum);
  755. static const char *aif_text[] = {
  756. "Left", "Right"
  757. };
  758. static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
  759. aif_text);
  760. static const struct snd_kcontrol_new aifoutl_mux =
  761. SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
  762. static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
  763. aif_text);
  764. static const struct snd_kcontrol_new aifoutr_mux =
  765. SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
  766. static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
  767. aif_text);
  768. static const struct snd_kcontrol_new aifinl_mux =
  769. SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
  770. static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
  771. aif_text);
  772. static const struct snd_kcontrol_new aifinr_mux =
  773. SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
  774. static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
  775. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
  776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  777. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
  778. SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
  779. };
  780. static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
  781. SND_SOC_DAPM_INPUT("IN1L"),
  782. SND_SOC_DAPM_INPUT("IN1R"),
  783. SND_SOC_DAPM_INPUT("IN2L"),
  784. SND_SOC_DAPM_INPUT("IN2R"),
  785. SND_SOC_DAPM_INPUT("IN3L"),
  786. SND_SOC_DAPM_INPUT("IN3R"),
  787. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
  788. SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
  789. SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  790. &lin_inv_mux),
  791. SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode),
  792. SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
  793. SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  794. &rin_inv_mux),
  795. SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode),
  796. SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
  797. NULL, 0),
  798. SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
  799. NULL, 0),
  800. SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
  801. SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
  802. SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
  803. SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
  804. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  805. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  806. };
  807. static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
  808. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  809. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  810. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
  811. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
  812. SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
  813. SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
  814. SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
  815. SND_SOC_DAPM_POST_PMU),
  816. SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  817. SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  818. SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  819. SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  820. SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
  821. 0, NULL, 0, out_pga_event,
  822. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  823. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  824. SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
  825. 0, NULL, 0, out_pga_event,
  826. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  827. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  828. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  829. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  830. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  831. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  832. };
  833. static const char *out_mux_text[] = {
  834. "DAC", "Bypass"
  835. };
  836. static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
  837. out_mux_text);
  838. static const struct snd_kcontrol_new hpl_mux =
  839. SOC_DAPM_ENUM("HPL Mux", hpl_enum);
  840. static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
  841. out_mux_text);
  842. static const struct snd_kcontrol_new hpr_mux =
  843. SOC_DAPM_ENUM("HPR Mux", hpr_enum);
  844. static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
  845. out_mux_text);
  846. static const struct snd_kcontrol_new linel_mux =
  847. SOC_DAPM_ENUM("LINEL Mux", linel_enum);
  848. static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
  849. out_mux_text);
  850. static const struct snd_kcontrol_new liner_mux =
  851. SOC_DAPM_ENUM("LINER Mux", liner_enum);
  852. static const char *sidetone_text[] = {
  853. "None", "Left", "Right"
  854. };
  855. static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
  856. sidetone_text);
  857. static const struct snd_kcontrol_new dacl_sidetone_mux =
  858. SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
  859. static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
  860. sidetone_text);
  861. static const struct snd_kcontrol_new dacr_sidetone_mux =
  862. SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
  863. static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
  864. SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
  865. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  866. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  867. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
  868. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
  869. SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  870. SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  871. SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
  872. SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
  873. };
  874. static const struct snd_soc_dapm_route core_intercon[] = {
  875. { "CLK_DSP", NULL, "SYSCLK" },
  876. { "TOCLK", NULL, "SYSCLK" },
  877. };
  878. static const struct snd_soc_dapm_route adc_intercon[] = {
  879. { "Left Capture Mux", "IN1L", "IN1L" },
  880. { "Left Capture Mux", "IN2L", "IN2L" },
  881. { "Left Capture Mux", "IN3L", "IN3L" },
  882. { "Left Capture Inverting Mux", "IN1L", "IN1L" },
  883. { "Left Capture Inverting Mux", "IN2L", "IN2L" },
  884. { "Left Capture Inverting Mux", "IN3L", "IN3L" },
  885. { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
  886. { "Left Capture Mode", "Differential Line", "Left Capture Mux" },
  887. { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" },
  888. { "Left Capture Mode", "Differential Mic", "Left Capture Mux" },
  889. { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" },
  890. { "Right Capture Mux", "IN1R", "IN1R" },
  891. { "Right Capture Mux", "IN2R", "IN2R" },
  892. { "Right Capture Mux", "IN3R", "IN3R" },
  893. { "Right Capture Inverting Mux", "IN1R", "IN1R" },
  894. { "Right Capture Inverting Mux", "IN2R", "IN2R" },
  895. { "Right Capture Inverting Mux", "IN3R", "IN3R" },
  896. { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
  897. { "Right Capture Mode", "Differential Line", "Right Capture Mux" },
  898. { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" },
  899. { "Right Capture Mode", "Differential Mic", "Right Capture Mux" },
  900. { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" },
  901. { "Left Capture PGA", NULL, "Left Capture Mode" },
  902. { "Right Capture PGA", NULL, "Right Capture Mode" },
  903. { "AIFOUTL Mux", "Left", "ADCL" },
  904. { "AIFOUTL Mux", "Right", "ADCR" },
  905. { "AIFOUTR Mux", "Left", "ADCL" },
  906. { "AIFOUTR Mux", "Right", "ADCR" },
  907. { "AIFOUTL", NULL, "AIFOUTL Mux" },
  908. { "AIFOUTR", NULL, "AIFOUTR Mux" },
  909. { "ADCL", NULL, "CLK_DSP" },
  910. { "ADCL", NULL, "Left Capture PGA" },
  911. { "ADCR", NULL, "CLK_DSP" },
  912. { "ADCR", NULL, "Right Capture PGA" },
  913. };
  914. static const struct snd_soc_dapm_route dac_intercon[] = {
  915. { "DACL Mux", "Left", "AIFINL" },
  916. { "DACL Mux", "Right", "AIFINR" },
  917. { "DACR Mux", "Left", "AIFINL" },
  918. { "DACR Mux", "Right", "AIFINR" },
  919. { "DACL", NULL, "DACL Mux" },
  920. { "DACL", NULL, "CLK_DSP" },
  921. { "DACR", NULL, "DACR Mux" },
  922. { "DACR", NULL, "CLK_DSP" },
  923. { "Charge pump", NULL, "SYSCLK" },
  924. { "Headphone Output", NULL, "HPL PGA" },
  925. { "Headphone Output", NULL, "HPR PGA" },
  926. { "Headphone Output", NULL, "Charge pump" },
  927. { "Headphone Output", NULL, "TOCLK" },
  928. { "Line Output", NULL, "LINEL PGA" },
  929. { "Line Output", NULL, "LINER PGA" },
  930. { "Line Output", NULL, "Charge pump" },
  931. { "Line Output", NULL, "TOCLK" },
  932. { "HPOUTL", NULL, "Headphone Output" },
  933. { "HPOUTR", NULL, "Headphone Output" },
  934. { "LINEOUTL", NULL, "Line Output" },
  935. { "LINEOUTR", NULL, "Line Output" },
  936. };
  937. static const struct snd_soc_dapm_route wm8904_intercon[] = {
  938. { "Left Sidetone", "Left", "ADCL" },
  939. { "Left Sidetone", "Right", "ADCR" },
  940. { "DACL", NULL, "Left Sidetone" },
  941. { "Right Sidetone", "Left", "ADCL" },
  942. { "Right Sidetone", "Right", "ADCR" },
  943. { "DACR", NULL, "Right Sidetone" },
  944. { "Left Bypass", NULL, "Class G" },
  945. { "Left Bypass", NULL, "Left Capture PGA" },
  946. { "Right Bypass", NULL, "Class G" },
  947. { "Right Bypass", NULL, "Right Capture PGA" },
  948. { "HPL Mux", "DAC", "DACL" },
  949. { "HPL Mux", "Bypass", "Left Bypass" },
  950. { "HPR Mux", "DAC", "DACR" },
  951. { "HPR Mux", "Bypass", "Right Bypass" },
  952. { "LINEL Mux", "DAC", "DACL" },
  953. { "LINEL Mux", "Bypass", "Left Bypass" },
  954. { "LINER Mux", "DAC", "DACR" },
  955. { "LINER Mux", "Bypass", "Right Bypass" },
  956. { "HPL PGA", NULL, "HPL Mux" },
  957. { "HPR PGA", NULL, "HPR Mux" },
  958. { "LINEL PGA", NULL, "LINEL Mux" },
  959. { "LINER PGA", NULL, "LINER Mux" },
  960. };
  961. static const struct snd_soc_dapm_route wm8912_intercon[] = {
  962. { "HPL PGA", NULL, "DACL" },
  963. { "HPR PGA", NULL, "DACR" },
  964. { "LINEL PGA", NULL, "DACL" },
  965. { "LINER PGA", NULL, "DACR" },
  966. };
  967. static int wm8904_add_widgets(struct snd_soc_component *component)
  968. {
  969. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  970. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  971. snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
  972. ARRAY_SIZE(wm8904_core_dapm_widgets));
  973. snd_soc_dapm_add_routes(dapm, core_intercon,
  974. ARRAY_SIZE(core_intercon));
  975. switch (wm8904->devtype) {
  976. case WM8904:
  977. snd_soc_add_component_controls(component, wm8904_adc_snd_controls,
  978. ARRAY_SIZE(wm8904_adc_snd_controls));
  979. snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
  980. ARRAY_SIZE(wm8904_dac_snd_controls));
  981. snd_soc_add_component_controls(component, wm8904_snd_controls,
  982. ARRAY_SIZE(wm8904_snd_controls));
  983. snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
  984. ARRAY_SIZE(wm8904_adc_dapm_widgets));
  985. snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
  986. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  987. snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
  988. ARRAY_SIZE(wm8904_dapm_widgets));
  989. snd_soc_dapm_add_routes(dapm, adc_intercon,
  990. ARRAY_SIZE(adc_intercon));
  991. snd_soc_dapm_add_routes(dapm, dac_intercon,
  992. ARRAY_SIZE(dac_intercon));
  993. snd_soc_dapm_add_routes(dapm, wm8904_intercon,
  994. ARRAY_SIZE(wm8904_intercon));
  995. break;
  996. case WM8912:
  997. snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
  998. ARRAY_SIZE(wm8904_dac_snd_controls));
  999. snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
  1000. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  1001. snd_soc_dapm_add_routes(dapm, dac_intercon,
  1002. ARRAY_SIZE(dac_intercon));
  1003. snd_soc_dapm_add_routes(dapm, wm8912_intercon,
  1004. ARRAY_SIZE(wm8912_intercon));
  1005. break;
  1006. }
  1007. return 0;
  1008. }
  1009. static struct {
  1010. int ratio;
  1011. unsigned int clk_sys_rate;
  1012. } clk_sys_rates[] = {
  1013. { 64, 0 },
  1014. { 128, 1 },
  1015. { 192, 2 },
  1016. { 256, 3 },
  1017. { 384, 4 },
  1018. { 512, 5 },
  1019. { 786, 6 },
  1020. { 1024, 7 },
  1021. { 1408, 8 },
  1022. { 1536, 9 },
  1023. };
  1024. static struct {
  1025. int rate;
  1026. int sample_rate;
  1027. } sample_rates[] = {
  1028. { 8000, 0 },
  1029. { 11025, 1 },
  1030. { 12000, 1 },
  1031. { 16000, 2 },
  1032. { 22050, 3 },
  1033. { 24000, 3 },
  1034. { 32000, 4 },
  1035. { 44100, 5 },
  1036. { 48000, 5 },
  1037. };
  1038. static struct {
  1039. int div; /* *10 due to .5s */
  1040. int bclk_div;
  1041. } bclk_divs[] = {
  1042. { 10, 0 },
  1043. { 15, 1 },
  1044. { 20, 2 },
  1045. { 30, 3 },
  1046. { 40, 4 },
  1047. { 50, 5 },
  1048. { 55, 6 },
  1049. { 60, 7 },
  1050. { 80, 8 },
  1051. { 100, 9 },
  1052. { 110, 10 },
  1053. { 120, 11 },
  1054. { 160, 12 },
  1055. { 200, 13 },
  1056. { 220, 14 },
  1057. { 240, 16 },
  1058. { 200, 17 },
  1059. { 320, 18 },
  1060. { 440, 19 },
  1061. { 480, 20 },
  1062. };
  1063. static int wm8904_hw_params(struct snd_pcm_substream *substream,
  1064. struct snd_pcm_hw_params *params,
  1065. struct snd_soc_dai *dai)
  1066. {
  1067. struct snd_soc_component *component = dai->component;
  1068. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1069. int ret, i, best, best_val, cur_val;
  1070. unsigned int aif1 = 0;
  1071. unsigned int aif2 = 0;
  1072. unsigned int aif3 = 0;
  1073. unsigned int clock1 = 0;
  1074. unsigned int dac_digital1 = 0;
  1075. /* What BCLK do we need? */
  1076. wm8904->fs = params_rate(params);
  1077. if (wm8904->tdm_slots) {
  1078. dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
  1079. wm8904->tdm_slots, wm8904->tdm_width);
  1080. wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
  1081. wm8904->tdm_width, 2,
  1082. wm8904->tdm_slots);
  1083. } else {
  1084. wm8904->bclk = snd_soc_params_to_bclk(params);
  1085. }
  1086. switch (params_width(params)) {
  1087. case 16:
  1088. break;
  1089. case 20:
  1090. aif1 |= 0x40;
  1091. break;
  1092. case 24:
  1093. aif1 |= 0x80;
  1094. break;
  1095. case 32:
  1096. aif1 |= 0xc0;
  1097. break;
  1098. default:
  1099. return -EINVAL;
  1100. }
  1101. dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
  1102. ret = wm8904_configure_clocking(component);
  1103. if (ret != 0)
  1104. return ret;
  1105. /* Select nearest CLK_SYS_RATE */
  1106. best = 0;
  1107. best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
  1108. - wm8904->fs);
  1109. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  1110. cur_val = abs((wm8904->sysclk_rate /
  1111. clk_sys_rates[i].ratio) - wm8904->fs);
  1112. if (cur_val < best_val) {
  1113. best = i;
  1114. best_val = cur_val;
  1115. }
  1116. }
  1117. dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
  1118. clk_sys_rates[best].ratio);
  1119. clock1 |= (clk_sys_rates[best].clk_sys_rate
  1120. << WM8904_CLK_SYS_RATE_SHIFT);
  1121. /* SAMPLE_RATE */
  1122. best = 0;
  1123. best_val = abs(wm8904->fs - sample_rates[0].rate);
  1124. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1125. /* Closest match */
  1126. cur_val = abs(wm8904->fs - sample_rates[i].rate);
  1127. if (cur_val < best_val) {
  1128. best = i;
  1129. best_val = cur_val;
  1130. }
  1131. }
  1132. dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
  1133. sample_rates[best].rate);
  1134. clock1 |= (sample_rates[best].sample_rate
  1135. << WM8904_SAMPLE_RATE_SHIFT);
  1136. /* Enable sloping stopband filter for low sample rates */
  1137. if (wm8904->fs <= 24000)
  1138. dac_digital1 |= WM8904_DAC_SB_FILT;
  1139. /* BCLK_DIV */
  1140. best = 0;
  1141. best_val = INT_MAX;
  1142. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1143. cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
  1144. - wm8904->bclk;
  1145. if (cur_val < 0) /* Table is sorted */
  1146. break;
  1147. if (cur_val < best_val) {
  1148. best = i;
  1149. best_val = cur_val;
  1150. }
  1151. }
  1152. wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
  1153. dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  1154. bclk_divs[best].div, wm8904->bclk);
  1155. aif2 |= bclk_divs[best].bclk_div;
  1156. /* LRCLK is a simple fraction of BCLK */
  1157. dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
  1158. aif3 |= wm8904->bclk / wm8904->fs;
  1159. /* Apply the settings */
  1160. snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
  1161. WM8904_DAC_SB_FILT, dac_digital1);
  1162. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
  1163. WM8904_AIF_WL_MASK, aif1);
  1164. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2,
  1165. WM8904_BCLK_DIV_MASK, aif2);
  1166. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
  1167. WM8904_LRCLK_RATE_MASK, aif3);
  1168. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1,
  1169. WM8904_SAMPLE_RATE_MASK |
  1170. WM8904_CLK_SYS_RATE_MASK, clock1);
  1171. /* Update filters for the new settings */
  1172. wm8904_set_retune_mobile(component);
  1173. wm8904_set_deemph(component);
  1174. return 0;
  1175. }
  1176. static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1177. {
  1178. struct snd_soc_component *component = dai->component;
  1179. unsigned int aif1 = 0;
  1180. unsigned int aif3 = 0;
  1181. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1182. case SND_SOC_DAIFMT_CBS_CFS:
  1183. break;
  1184. case SND_SOC_DAIFMT_CBS_CFM:
  1185. aif3 |= WM8904_LRCLK_DIR;
  1186. break;
  1187. case SND_SOC_DAIFMT_CBM_CFS:
  1188. aif1 |= WM8904_BCLK_DIR;
  1189. break;
  1190. case SND_SOC_DAIFMT_CBM_CFM:
  1191. aif1 |= WM8904_BCLK_DIR;
  1192. aif3 |= WM8904_LRCLK_DIR;
  1193. break;
  1194. default:
  1195. return -EINVAL;
  1196. }
  1197. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1198. case SND_SOC_DAIFMT_DSP_B:
  1199. aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
  1200. fallthrough;
  1201. case SND_SOC_DAIFMT_DSP_A:
  1202. aif1 |= 0x3;
  1203. break;
  1204. case SND_SOC_DAIFMT_I2S:
  1205. aif1 |= 0x2;
  1206. break;
  1207. case SND_SOC_DAIFMT_RIGHT_J:
  1208. break;
  1209. case SND_SOC_DAIFMT_LEFT_J:
  1210. aif1 |= 0x1;
  1211. break;
  1212. default:
  1213. return -EINVAL;
  1214. }
  1215. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1216. case SND_SOC_DAIFMT_DSP_A:
  1217. case SND_SOC_DAIFMT_DSP_B:
  1218. /* frame inversion not valid for DSP modes */
  1219. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1220. case SND_SOC_DAIFMT_NB_NF:
  1221. break;
  1222. case SND_SOC_DAIFMT_IB_NF:
  1223. aif1 |= WM8904_AIF_BCLK_INV;
  1224. break;
  1225. default:
  1226. return -EINVAL;
  1227. }
  1228. break;
  1229. case SND_SOC_DAIFMT_I2S:
  1230. case SND_SOC_DAIFMT_RIGHT_J:
  1231. case SND_SOC_DAIFMT_LEFT_J:
  1232. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1233. case SND_SOC_DAIFMT_NB_NF:
  1234. break;
  1235. case SND_SOC_DAIFMT_IB_IF:
  1236. aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
  1237. break;
  1238. case SND_SOC_DAIFMT_IB_NF:
  1239. aif1 |= WM8904_AIF_BCLK_INV;
  1240. break;
  1241. case SND_SOC_DAIFMT_NB_IF:
  1242. aif1 |= WM8904_AIF_LRCLK_INV;
  1243. break;
  1244. default:
  1245. return -EINVAL;
  1246. }
  1247. break;
  1248. default:
  1249. return -EINVAL;
  1250. }
  1251. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
  1252. WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
  1253. WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
  1254. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
  1255. WM8904_LRCLK_DIR, aif3);
  1256. return 0;
  1257. }
  1258. static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1259. unsigned int rx_mask, int slots, int slot_width)
  1260. {
  1261. struct snd_soc_component *component = dai->component;
  1262. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1263. int aif1 = 0;
  1264. /* Don't need to validate anything if we're turning off TDM */
  1265. if (slots == 0)
  1266. goto out;
  1267. /* Note that we allow configurations we can't handle ourselves -
  1268. * for example, we can generate clocks for slots 2 and up even if
  1269. * we can't use those slots ourselves.
  1270. */
  1271. aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
  1272. switch (rx_mask) {
  1273. case 3:
  1274. break;
  1275. case 0xc:
  1276. aif1 |= WM8904_AIFADC_TDM_CHAN;
  1277. break;
  1278. default:
  1279. return -EINVAL;
  1280. }
  1281. switch (tx_mask) {
  1282. case 3:
  1283. break;
  1284. case 0xc:
  1285. aif1 |= WM8904_AIFDAC_TDM_CHAN;
  1286. break;
  1287. default:
  1288. return -EINVAL;
  1289. }
  1290. out:
  1291. wm8904->tdm_width = slot_width;
  1292. wm8904->tdm_slots = slots / 2;
  1293. snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
  1294. WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
  1295. WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
  1296. return 0;
  1297. }
  1298. struct _fll_div {
  1299. u16 fll_fratio;
  1300. u16 fll_outdiv;
  1301. u16 fll_clk_ref_div;
  1302. u16 n;
  1303. u16 k;
  1304. };
  1305. /* The size in bits of the FLL divide multiplied by 10
  1306. * to allow rounding later */
  1307. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1308. static struct {
  1309. unsigned int min;
  1310. unsigned int max;
  1311. u16 fll_fratio;
  1312. int ratio;
  1313. } fll_fratios[] = {
  1314. { 0, 64000, 4, 16 },
  1315. { 64000, 128000, 3, 8 },
  1316. { 128000, 256000, 2, 4 },
  1317. { 256000, 1000000, 1, 2 },
  1318. { 1000000, 13500000, 0, 1 },
  1319. };
  1320. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1321. unsigned int Fout)
  1322. {
  1323. u64 Kpart;
  1324. unsigned int K, Ndiv, Nmod, target;
  1325. unsigned int div;
  1326. int i;
  1327. /* Fref must be <=13.5MHz */
  1328. div = 1;
  1329. fll_div->fll_clk_ref_div = 0;
  1330. while ((Fref / div) > 13500000) {
  1331. div *= 2;
  1332. fll_div->fll_clk_ref_div++;
  1333. if (div > 8) {
  1334. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1335. Fref);
  1336. return -EINVAL;
  1337. }
  1338. }
  1339. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  1340. /* Apply the division for our remaining calculations */
  1341. Fref /= div;
  1342. /* Fvco should be 90-100MHz; don't check the upper bound */
  1343. div = 4;
  1344. while (Fout * div < 90000000) {
  1345. div++;
  1346. if (div > 64) {
  1347. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1348. Fout);
  1349. return -EINVAL;
  1350. }
  1351. }
  1352. target = Fout * div;
  1353. fll_div->fll_outdiv = div - 1;
  1354. pr_debug("Fvco=%dHz\n", target);
  1355. /* Find an appropriate FLL_FRATIO and factor it out of the target */
  1356. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1357. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1358. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1359. target /= fll_fratios[i].ratio;
  1360. break;
  1361. }
  1362. }
  1363. if (i == ARRAY_SIZE(fll_fratios)) {
  1364. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1365. return -EINVAL;
  1366. }
  1367. /* Now, calculate N.K */
  1368. Ndiv = target / Fref;
  1369. fll_div->n = Ndiv;
  1370. Nmod = target % Fref;
  1371. pr_debug("Nmod=%d\n", Nmod);
  1372. /* Calculate fractional part - scale up so we can round. */
  1373. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1374. do_div(Kpart, Fref);
  1375. K = Kpart & 0xFFFFFFFF;
  1376. if ((K % 10) >= 5)
  1377. K += 5;
  1378. /* Move down to proper range now rounding is done */
  1379. fll_div->k = K / 10;
  1380. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  1381. fll_div->n, fll_div->k,
  1382. fll_div->fll_fratio, fll_div->fll_outdiv,
  1383. fll_div->fll_clk_ref_div);
  1384. return 0;
  1385. }
  1386. static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1387. unsigned int Fref, unsigned int Fout)
  1388. {
  1389. struct snd_soc_component *component = dai->component;
  1390. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1391. struct _fll_div fll_div;
  1392. int ret, val;
  1393. int clock2, fll1;
  1394. /* Any change? */
  1395. if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
  1396. Fout == wm8904->fll_fout)
  1397. return 0;
  1398. clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
  1399. if (Fout == 0) {
  1400. dev_dbg(component->dev, "FLL disabled\n");
  1401. wm8904->fll_fref = 0;
  1402. wm8904->fll_fout = 0;
  1403. /* Gate SYSCLK to avoid glitches */
  1404. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
  1405. WM8904_CLK_SYS_ENA, 0);
  1406. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  1407. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1408. goto out;
  1409. }
  1410. /* Validate the FLL ID */
  1411. switch (source) {
  1412. case WM8904_FLL_MCLK:
  1413. case WM8904_FLL_LRCLK:
  1414. case WM8904_FLL_BCLK:
  1415. ret = fll_factors(&fll_div, Fref, Fout);
  1416. if (ret != 0)
  1417. return ret;
  1418. break;
  1419. case WM8904_FLL_FREE_RUNNING:
  1420. dev_dbg(component->dev, "Using free running FLL\n");
  1421. /* Force 12MHz and output/4 for now */
  1422. Fout = 12000000;
  1423. Fref = 12000000;
  1424. memset(&fll_div, 0, sizeof(fll_div));
  1425. fll_div.fll_outdiv = 3;
  1426. break;
  1427. default:
  1428. dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
  1429. return -EINVAL;
  1430. }
  1431. /* Save current state then disable the FLL and SYSCLK to avoid
  1432. * misclocking */
  1433. fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1);
  1434. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
  1435. WM8904_CLK_SYS_ENA, 0);
  1436. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  1437. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1438. /* Unlock forced oscilator control to switch it on/off */
  1439. snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
  1440. WM8904_USER_KEY, WM8904_USER_KEY);
  1441. if (fll_id == WM8904_FLL_FREE_RUNNING) {
  1442. val = WM8904_FLL_FRC_NCO;
  1443. } else {
  1444. val = 0;
  1445. }
  1446. snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
  1447. val);
  1448. snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
  1449. WM8904_USER_KEY, 0);
  1450. switch (fll_id) {
  1451. case WM8904_FLL_MCLK:
  1452. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
  1453. WM8904_FLL_CLK_REF_SRC_MASK, 0);
  1454. break;
  1455. case WM8904_FLL_LRCLK:
  1456. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
  1457. WM8904_FLL_CLK_REF_SRC_MASK, 1);
  1458. break;
  1459. case WM8904_FLL_BCLK:
  1460. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
  1461. WM8904_FLL_CLK_REF_SRC_MASK, 2);
  1462. break;
  1463. }
  1464. if (fll_div.k)
  1465. val = WM8904_FLL_FRACN_ENA;
  1466. else
  1467. val = 0;
  1468. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  1469. WM8904_FLL_FRACN_ENA, val);
  1470. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2,
  1471. WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
  1472. (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
  1473. (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
  1474. snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
  1475. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
  1476. fll_div.n << WM8904_FLL_N_SHIFT);
  1477. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
  1478. WM8904_FLL_CLK_REF_DIV_MASK,
  1479. fll_div.fll_clk_ref_div
  1480. << WM8904_FLL_CLK_REF_DIV_SHIFT);
  1481. dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1482. wm8904->fll_fref = Fref;
  1483. wm8904->fll_fout = Fout;
  1484. wm8904->fll_src = source;
  1485. /* Enable the FLL if it was previously active */
  1486. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  1487. WM8904_FLL_OSC_ENA, fll1);
  1488. snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
  1489. WM8904_FLL_ENA, fll1);
  1490. out:
  1491. /* Reenable SYSCLK if it was previously active */
  1492. snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
  1493. WM8904_CLK_SYS_ENA, clock2);
  1494. return 0;
  1495. }
  1496. static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  1497. unsigned int freq, int dir)
  1498. {
  1499. struct snd_soc_component *component = dai->component;
  1500. struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
  1501. unsigned long mclk_freq;
  1502. int ret;
  1503. switch (clk_id) {
  1504. case WM8904_CLK_AUTO:
  1505. /* We don't have any rate constraints, so just ignore the
  1506. * request to disable constraining.
  1507. */
  1508. if (!freq)
  1509. return 0;
  1510. mclk_freq = clk_get_rate(priv->mclk);
  1511. /* enable FLL if a different sysclk is desired */
  1512. if (mclk_freq != freq) {
  1513. priv->sysclk_src = WM8904_CLK_FLL;
  1514. ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
  1515. WM8904_FLL_MCLK,
  1516. mclk_freq, freq);
  1517. if (ret)
  1518. return ret;
  1519. break;
  1520. }
  1521. clk_id = WM8904_CLK_MCLK;
  1522. fallthrough;
  1523. case WM8904_CLK_MCLK:
  1524. priv->sysclk_src = clk_id;
  1525. priv->mclk_rate = freq;
  1526. break;
  1527. case WM8904_CLK_FLL:
  1528. priv->sysclk_src = clk_id;
  1529. break;
  1530. default:
  1531. return -EINVAL;
  1532. }
  1533. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  1534. wm8904_configure_clocking(component);
  1535. return 0;
  1536. }
  1537. static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  1538. {
  1539. struct snd_soc_component *component = codec_dai->component;
  1540. int val;
  1541. if (mute)
  1542. val = WM8904_DAC_MUTE;
  1543. else
  1544. val = 0;
  1545. snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
  1546. return 0;
  1547. }
  1548. static int wm8904_set_bias_level(struct snd_soc_component *component,
  1549. enum snd_soc_bias_level level)
  1550. {
  1551. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1552. int ret;
  1553. switch (level) {
  1554. case SND_SOC_BIAS_ON:
  1555. break;
  1556. case SND_SOC_BIAS_PREPARE:
  1557. /* VMID resistance 2*50k */
  1558. snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
  1559. WM8904_VMID_RES_MASK,
  1560. 0x1 << WM8904_VMID_RES_SHIFT);
  1561. /* Normal bias current */
  1562. snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
  1563. WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
  1564. break;
  1565. case SND_SOC_BIAS_STANDBY:
  1566. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1567. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  1568. wm8904->supplies);
  1569. if (ret != 0) {
  1570. dev_err(component->dev,
  1571. "Failed to enable supplies: %d\n",
  1572. ret);
  1573. return ret;
  1574. }
  1575. ret = clk_prepare_enable(wm8904->mclk);
  1576. if (ret) {
  1577. dev_err(component->dev,
  1578. "Failed to enable MCLK: %d\n", ret);
  1579. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
  1580. wm8904->supplies);
  1581. return ret;
  1582. }
  1583. regcache_cache_only(wm8904->regmap, false);
  1584. regcache_sync(wm8904->regmap);
  1585. /* Enable bias */
  1586. snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
  1587. WM8904_BIAS_ENA, WM8904_BIAS_ENA);
  1588. /* Enable VMID, VMID buffering, 2*5k resistance */
  1589. snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
  1590. WM8904_VMID_ENA |
  1591. WM8904_VMID_RES_MASK,
  1592. WM8904_VMID_ENA |
  1593. 0x3 << WM8904_VMID_RES_SHIFT);
  1594. /* Let VMID ramp */
  1595. msleep(1);
  1596. }
  1597. /* Maintain VMID with 2*250k */
  1598. snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
  1599. WM8904_VMID_RES_MASK,
  1600. 0x2 << WM8904_VMID_RES_SHIFT);
  1601. /* Bias current *0.5 */
  1602. snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
  1603. WM8904_ISEL_MASK, 0);
  1604. break;
  1605. case SND_SOC_BIAS_OFF:
  1606. /* Turn off VMID */
  1607. snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
  1608. WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
  1609. /* Stop bias generation */
  1610. snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
  1611. WM8904_BIAS_ENA, 0);
  1612. snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0);
  1613. regcache_cache_only(wm8904->regmap, true);
  1614. regcache_mark_dirty(wm8904->regmap);
  1615. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
  1616. wm8904->supplies);
  1617. clk_disable_unprepare(wm8904->mclk);
  1618. break;
  1619. }
  1620. return 0;
  1621. }
  1622. #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
  1623. #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1624. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1625. static const struct snd_soc_dai_ops wm8904_dai_ops = {
  1626. .set_sysclk = wm8904_set_sysclk,
  1627. .set_fmt = wm8904_set_fmt,
  1628. .set_tdm_slot = wm8904_set_tdm_slot,
  1629. .set_pll = wm8904_set_fll,
  1630. .hw_params = wm8904_hw_params,
  1631. .mute_stream = wm8904_mute,
  1632. .no_capture_mute = 1,
  1633. };
  1634. static struct snd_soc_dai_driver wm8904_dai = {
  1635. .name = "wm8904-hifi",
  1636. .playback = {
  1637. .stream_name = "Playback",
  1638. .channels_min = 2,
  1639. .channels_max = 2,
  1640. .rates = WM8904_RATES,
  1641. .formats = WM8904_FORMATS,
  1642. },
  1643. .capture = {
  1644. .stream_name = "Capture",
  1645. .channels_min = 2,
  1646. .channels_max = 2,
  1647. .rates = WM8904_RATES,
  1648. .formats = WM8904_FORMATS,
  1649. },
  1650. .ops = &wm8904_dai_ops,
  1651. .symmetric_rate = 1,
  1652. };
  1653. static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component)
  1654. {
  1655. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1656. struct wm8904_pdata *pdata = wm8904->pdata;
  1657. struct snd_kcontrol_new control =
  1658. SOC_ENUM_EXT("EQ Mode",
  1659. wm8904->retune_mobile_enum,
  1660. wm8904_get_retune_mobile_enum,
  1661. wm8904_put_retune_mobile_enum);
  1662. int ret, i, j;
  1663. const char **t;
  1664. /* We need an array of texts for the enum API but the number
  1665. * of texts is likely to be less than the number of
  1666. * configurations due to the sample rate dependency of the
  1667. * configurations. */
  1668. wm8904->num_retune_mobile_texts = 0;
  1669. wm8904->retune_mobile_texts = NULL;
  1670. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  1671. for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
  1672. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  1673. wm8904->retune_mobile_texts[j]) == 0)
  1674. break;
  1675. }
  1676. if (j != wm8904->num_retune_mobile_texts)
  1677. continue;
  1678. /* Expand the array... */
  1679. t = krealloc(wm8904->retune_mobile_texts,
  1680. sizeof(char *) *
  1681. (wm8904->num_retune_mobile_texts + 1),
  1682. GFP_KERNEL);
  1683. if (t == NULL)
  1684. continue;
  1685. /* ...store the new entry... */
  1686. t[wm8904->num_retune_mobile_texts] =
  1687. pdata->retune_mobile_cfgs[i].name;
  1688. /* ...and remember the new version. */
  1689. wm8904->num_retune_mobile_texts++;
  1690. wm8904->retune_mobile_texts = t;
  1691. }
  1692. dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
  1693. wm8904->num_retune_mobile_texts);
  1694. wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
  1695. wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
  1696. ret = snd_soc_add_component_controls(component, &control, 1);
  1697. if (ret != 0)
  1698. dev_err(component->dev,
  1699. "Failed to add ReTune Mobile control: %d\n", ret);
  1700. }
  1701. static void wm8904_handle_pdata(struct snd_soc_component *component)
  1702. {
  1703. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1704. struct wm8904_pdata *pdata = wm8904->pdata;
  1705. int ret, i;
  1706. if (!pdata) {
  1707. snd_soc_add_component_controls(component, wm8904_eq_controls,
  1708. ARRAY_SIZE(wm8904_eq_controls));
  1709. return;
  1710. }
  1711. dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  1712. if (pdata->num_drc_cfgs) {
  1713. struct snd_kcontrol_new control =
  1714. SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
  1715. wm8904_get_drc_enum, wm8904_put_drc_enum);
  1716. /* We need an array of texts for the enum API */
  1717. wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
  1718. sizeof(char *),
  1719. GFP_KERNEL);
  1720. if (!wm8904->drc_texts)
  1721. return;
  1722. for (i = 0; i < pdata->num_drc_cfgs; i++)
  1723. wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
  1724. wm8904->drc_enum.items = pdata->num_drc_cfgs;
  1725. wm8904->drc_enum.texts = wm8904->drc_texts;
  1726. ret = snd_soc_add_component_controls(component, &control, 1);
  1727. if (ret != 0)
  1728. dev_err(component->dev,
  1729. "Failed to add DRC mode control: %d\n", ret);
  1730. wm8904_set_drc(component);
  1731. }
  1732. dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
  1733. pdata->num_retune_mobile_cfgs);
  1734. if (pdata->num_retune_mobile_cfgs)
  1735. wm8904_handle_retune_mobile_pdata(component);
  1736. else
  1737. snd_soc_add_component_controls(component, wm8904_eq_controls,
  1738. ARRAY_SIZE(wm8904_eq_controls));
  1739. }
  1740. static int wm8904_probe(struct snd_soc_component *component)
  1741. {
  1742. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1743. switch (wm8904->devtype) {
  1744. case WM8904:
  1745. break;
  1746. case WM8912:
  1747. memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
  1748. break;
  1749. default:
  1750. dev_err(component->dev, "Unknown device type %d\n",
  1751. wm8904->devtype);
  1752. return -EINVAL;
  1753. }
  1754. wm8904_handle_pdata(component);
  1755. wm8904_add_widgets(component);
  1756. return 0;
  1757. }
  1758. static void wm8904_remove(struct snd_soc_component *component)
  1759. {
  1760. struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
  1761. kfree(wm8904->retune_mobile_texts);
  1762. kfree(wm8904->drc_texts);
  1763. }
  1764. static const struct snd_soc_component_driver soc_component_dev_wm8904 = {
  1765. .probe = wm8904_probe,
  1766. .remove = wm8904_remove,
  1767. .set_bias_level = wm8904_set_bias_level,
  1768. .use_pmdown_time = 1,
  1769. .endianness = 1,
  1770. };
  1771. static const struct regmap_config wm8904_regmap = {
  1772. .reg_bits = 8,
  1773. .val_bits = 16,
  1774. .max_register = WM8904_MAX_REGISTER,
  1775. .volatile_reg = wm8904_volatile_register,
  1776. .readable_reg = wm8904_readable_register,
  1777. .cache_type = REGCACHE_RBTREE,
  1778. .reg_defaults = wm8904_reg_defaults,
  1779. .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
  1780. };
  1781. #ifdef CONFIG_OF
  1782. static const struct of_device_id wm8904_of_match[] = {
  1783. {
  1784. .compatible = "wlf,wm8904",
  1785. .data = (void *)WM8904,
  1786. }, {
  1787. .compatible = "wlf,wm8912",
  1788. .data = (void *)WM8912,
  1789. }, {
  1790. /* sentinel */
  1791. }
  1792. };
  1793. MODULE_DEVICE_TABLE(of, wm8904_of_match);
  1794. #endif
  1795. static const struct i2c_device_id wm8904_i2c_id[];
  1796. static int wm8904_i2c_probe(struct i2c_client *i2c)
  1797. {
  1798. struct wm8904_priv *wm8904;
  1799. unsigned int val;
  1800. int ret, i;
  1801. wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
  1802. GFP_KERNEL);
  1803. if (wm8904 == NULL)
  1804. return -ENOMEM;
  1805. wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
  1806. if (IS_ERR(wm8904->mclk)) {
  1807. ret = PTR_ERR(wm8904->mclk);
  1808. dev_err(&i2c->dev, "Failed to get MCLK\n");
  1809. return ret;
  1810. }
  1811. wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
  1812. if (IS_ERR(wm8904->regmap)) {
  1813. ret = PTR_ERR(wm8904->regmap);
  1814. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1815. ret);
  1816. return ret;
  1817. }
  1818. if (i2c->dev.of_node) {
  1819. const struct of_device_id *match;
  1820. match = of_match_node(wm8904_of_match, i2c->dev.of_node);
  1821. if (match == NULL)
  1822. return -EINVAL;
  1823. wm8904->devtype = (enum wm8904_type)match->data;
  1824. } else {
  1825. const struct i2c_device_id *id =
  1826. i2c_match_id(wm8904_i2c_id, i2c);
  1827. wm8904->devtype = id->driver_data;
  1828. }
  1829. i2c_set_clientdata(i2c, wm8904);
  1830. wm8904->pdata = i2c->dev.platform_data;
  1831. for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
  1832. wm8904->supplies[i].supply = wm8904_supply_names[i];
  1833. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
  1834. wm8904->supplies);
  1835. if (ret != 0) {
  1836. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  1837. return ret;
  1838. }
  1839. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  1840. wm8904->supplies);
  1841. if (ret != 0) {
  1842. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  1843. return ret;
  1844. }
  1845. ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
  1846. if (ret < 0) {
  1847. dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
  1848. goto err_enable;
  1849. }
  1850. if (val != 0x8904) {
  1851. dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
  1852. ret = -EINVAL;
  1853. goto err_enable;
  1854. }
  1855. ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
  1856. if (ret < 0) {
  1857. dev_err(&i2c->dev, "Failed to read device revision: %d\n",
  1858. ret);
  1859. goto err_enable;
  1860. }
  1861. dev_info(&i2c->dev, "revision %c\n", val + 'A');
  1862. ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
  1863. if (ret < 0) {
  1864. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  1865. goto err_enable;
  1866. }
  1867. /* Change some default settings - latch VU and enable ZC */
  1868. regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
  1869. WM8904_ADC_VU, WM8904_ADC_VU);
  1870. regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
  1871. WM8904_ADC_VU, WM8904_ADC_VU);
  1872. regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
  1873. WM8904_DAC_VU, WM8904_DAC_VU);
  1874. regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
  1875. WM8904_DAC_VU, WM8904_DAC_VU);
  1876. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
  1877. WM8904_HPOUT_VU | WM8904_HPOUTLZC,
  1878. WM8904_HPOUT_VU | WM8904_HPOUTLZC);
  1879. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
  1880. WM8904_HPOUT_VU | WM8904_HPOUTRZC,
  1881. WM8904_HPOUT_VU | WM8904_HPOUTRZC);
  1882. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
  1883. WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
  1884. WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
  1885. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
  1886. WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
  1887. WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
  1888. regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
  1889. WM8904_SR_MODE, 0);
  1890. /* Apply configuration from the platform data. */
  1891. if (wm8904->pdata) {
  1892. for (i = 0; i < WM8904_GPIO_REGS; i++) {
  1893. if (!wm8904->pdata->gpio_cfg[i])
  1894. continue;
  1895. regmap_update_bits(wm8904->regmap,
  1896. WM8904_GPIO_CONTROL_1 + i,
  1897. 0xffff,
  1898. wm8904->pdata->gpio_cfg[i]);
  1899. }
  1900. /* Zero is the default value for these anyway */
  1901. for (i = 0; i < WM8904_MIC_REGS; i++)
  1902. regmap_update_bits(wm8904->regmap,
  1903. WM8904_MIC_BIAS_CONTROL_0 + i,
  1904. 0xffff,
  1905. wm8904->pdata->mic_cfg[i]);
  1906. }
  1907. /* Set Class W by default - this will be managed by the Class
  1908. * G widget at runtime where bypass paths are available.
  1909. */
  1910. regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
  1911. WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
  1912. /* Use normal bias source */
  1913. regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
  1914. WM8904_POBCTRL, 0);
  1915. /* Fill the cache for the ADC test register */
  1916. regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val);
  1917. /* Can leave the device powered off until we need it */
  1918. regcache_cache_only(wm8904->regmap, true);
  1919. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  1920. ret = devm_snd_soc_register_component(&i2c->dev,
  1921. &soc_component_dev_wm8904, &wm8904_dai, 1);
  1922. if (ret != 0)
  1923. return ret;
  1924. return 0;
  1925. err_enable:
  1926. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  1927. return ret;
  1928. }
  1929. static const struct i2c_device_id wm8904_i2c_id[] = {
  1930. { "wm8904", WM8904 },
  1931. { "wm8912", WM8912 },
  1932. { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
  1933. { }
  1934. };
  1935. MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
  1936. static struct i2c_driver wm8904_i2c_driver = {
  1937. .driver = {
  1938. .name = "wm8904",
  1939. .of_match_table = of_match_ptr(wm8904_of_match),
  1940. },
  1941. .probe_new = wm8904_i2c_probe,
  1942. .id_table = wm8904_i2c_id,
  1943. };
  1944. module_i2c_driver(wm8904_i2c_driver);
  1945. MODULE_DESCRIPTION("ASoC WM8904 driver");
  1946. MODULE_AUTHOR("Mark Brown <[email protected]>");
  1947. MODULE_LICENSE("GPL");