wm8903.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8903.c -- WM8903 ALSA SoC Audio driver
  4. *
  5. * Copyright 2008-12 Wolfson Microelectronics
  6. * Copyright 2011-2012 NVIDIA, Inc.
  7. *
  8. * Author: Mark Brown <[email protected]>
  9. *
  10. * TODO:
  11. * - TDM mode configuration.
  12. * - Digital microphone support.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/init.h>
  17. #include <linux/completion.h>
  18. #include <linux/delay.h>
  19. #include <linux/gpio/driver.h>
  20. #include <linux/pm.h>
  21. #include <linux/i2c.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/slab.h>
  25. #include <linux/irq.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/jack.h>
  29. #include <sound/pcm.h>
  30. #include <sound/pcm_params.h>
  31. #include <sound/tlv.h>
  32. #include <sound/soc.h>
  33. #include <sound/initval.h>
  34. #include <sound/wm8903.h>
  35. #include <trace/events/asoc.h>
  36. #include "wm8903.h"
  37. /* Register defaults at reset */
  38. static const struct reg_default wm8903_reg_defaults[] = {
  39. { 4, 0x0018 }, /* R4 - Bias Control 0 */
  40. { 5, 0x0000 }, /* R5 - VMID Control 0 */
  41. { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
  42. { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
  43. { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
  44. { 12, 0x0000 }, /* R12 - Power Management 0 */
  45. { 13, 0x0000 }, /* R13 - Power Management 1 */
  46. { 14, 0x0000 }, /* R14 - Power Management 2 */
  47. { 15, 0x0000 }, /* R15 - Power Management 3 */
  48. { 16, 0x0000 }, /* R16 - Power Management 4 */
  49. { 17, 0x0000 }, /* R17 - Power Management 5 */
  50. { 18, 0x0000 }, /* R18 - Power Management 6 */
  51. { 20, 0x0400 }, /* R20 - Clock Rates 0 */
  52. { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
  53. { 22, 0x0000 }, /* R22 - Clock Rates 2 */
  54. { 24, 0x0050 }, /* R24 - Audio Interface 0 */
  55. { 25, 0x0242 }, /* R25 - Audio Interface 1 */
  56. { 26, 0x0008 }, /* R26 - Audio Interface 2 */
  57. { 27, 0x0022 }, /* R27 - Audio Interface 3 */
  58. { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
  59. { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
  60. { 32, 0x0000 }, /* R32 - DAC Digital 0 */
  61. { 33, 0x0000 }, /* R33 - DAC Digital 1 */
  62. { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
  63. { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
  64. { 38, 0x0000 }, /* R38 - ADC Digital 0 */
  65. { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
  66. { 40, 0x09BF }, /* R40 - DRC 0 */
  67. { 41, 0x3241 }, /* R41 - DRC 1 */
  68. { 42, 0x0020 }, /* R42 - DRC 2 */
  69. { 43, 0x0000 }, /* R43 - DRC 3 */
  70. { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
  71. { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
  72. { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
  73. { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
  74. { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
  75. { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
  76. { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
  77. { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
  78. { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
  79. { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
  80. { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
  81. { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
  82. { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
  83. { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
  84. { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
  85. { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
  86. { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
  87. { 67, 0x0010 }, /* R67 - DC Servo 0 */
  88. { 69, 0x00A4 }, /* R69 - DC Servo 2 */
  89. { 90, 0x0000 }, /* R90 - Analogue HP 0 */
  90. { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
  91. { 98, 0x0000 }, /* R98 - Charge Pump 0 */
  92. { 104, 0x0000 }, /* R104 - Class W 0 */
  93. { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
  94. { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
  95. { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
  96. { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
  97. { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
  98. { 114, 0x0000 }, /* R114 - Control Interface */
  99. { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
  100. { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
  101. { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
  102. { 119, 0x0220 }, /* R119 - GPIO Control 4 */
  103. { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
  104. { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
  105. { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
  106. { 126, 0x0000 }, /* R126 - Interrupt Control */
  107. { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
  108. { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
  109. { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
  110. { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
  111. };
  112. #define WM8903_NUM_SUPPLIES 4
  113. static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = {
  114. "AVDD",
  115. "CPVDD",
  116. "DBVDD",
  117. "DCVDD",
  118. };
  119. struct wm8903_priv {
  120. struct wm8903_platform_data *pdata;
  121. struct device *dev;
  122. struct regmap *regmap;
  123. struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES];
  124. int sysclk;
  125. int irq;
  126. struct mutex lock;
  127. int fs;
  128. int deemph;
  129. int dcs_pending;
  130. int dcs_cache[4];
  131. /* Reference count */
  132. int class_w_users;
  133. struct snd_soc_jack *mic_jack;
  134. int mic_det;
  135. int mic_short;
  136. int mic_last_report;
  137. int mic_delay;
  138. #ifdef CONFIG_GPIOLIB
  139. struct gpio_chip gpio_chip;
  140. #endif
  141. };
  142. static bool wm8903_readable_register(struct device *dev, unsigned int reg)
  143. {
  144. switch (reg) {
  145. case WM8903_SW_RESET_AND_ID:
  146. case WM8903_REVISION_NUMBER:
  147. case WM8903_BIAS_CONTROL_0:
  148. case WM8903_VMID_CONTROL_0:
  149. case WM8903_MIC_BIAS_CONTROL_0:
  150. case WM8903_ANALOGUE_DAC_0:
  151. case WM8903_ANALOGUE_ADC_0:
  152. case WM8903_POWER_MANAGEMENT_0:
  153. case WM8903_POWER_MANAGEMENT_1:
  154. case WM8903_POWER_MANAGEMENT_2:
  155. case WM8903_POWER_MANAGEMENT_3:
  156. case WM8903_POWER_MANAGEMENT_4:
  157. case WM8903_POWER_MANAGEMENT_5:
  158. case WM8903_POWER_MANAGEMENT_6:
  159. case WM8903_CLOCK_RATES_0:
  160. case WM8903_CLOCK_RATES_1:
  161. case WM8903_CLOCK_RATES_2:
  162. case WM8903_AUDIO_INTERFACE_0:
  163. case WM8903_AUDIO_INTERFACE_1:
  164. case WM8903_AUDIO_INTERFACE_2:
  165. case WM8903_AUDIO_INTERFACE_3:
  166. case WM8903_DAC_DIGITAL_VOLUME_LEFT:
  167. case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
  168. case WM8903_DAC_DIGITAL_0:
  169. case WM8903_DAC_DIGITAL_1:
  170. case WM8903_ADC_DIGITAL_VOLUME_LEFT:
  171. case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
  172. case WM8903_ADC_DIGITAL_0:
  173. case WM8903_DIGITAL_MICROPHONE_0:
  174. case WM8903_DRC_0:
  175. case WM8903_DRC_1:
  176. case WM8903_DRC_2:
  177. case WM8903_DRC_3:
  178. case WM8903_ANALOGUE_LEFT_INPUT_0:
  179. case WM8903_ANALOGUE_RIGHT_INPUT_0:
  180. case WM8903_ANALOGUE_LEFT_INPUT_1:
  181. case WM8903_ANALOGUE_RIGHT_INPUT_1:
  182. case WM8903_ANALOGUE_LEFT_MIX_0:
  183. case WM8903_ANALOGUE_RIGHT_MIX_0:
  184. case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
  185. case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
  186. case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
  187. case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
  188. case WM8903_ANALOGUE_OUT1_LEFT:
  189. case WM8903_ANALOGUE_OUT1_RIGHT:
  190. case WM8903_ANALOGUE_OUT2_LEFT:
  191. case WM8903_ANALOGUE_OUT2_RIGHT:
  192. case WM8903_ANALOGUE_OUT3_LEFT:
  193. case WM8903_ANALOGUE_OUT3_RIGHT:
  194. case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
  195. case WM8903_DC_SERVO_0:
  196. case WM8903_DC_SERVO_2:
  197. case WM8903_DC_SERVO_READBACK_1:
  198. case WM8903_DC_SERVO_READBACK_2:
  199. case WM8903_DC_SERVO_READBACK_3:
  200. case WM8903_DC_SERVO_READBACK_4:
  201. case WM8903_ANALOGUE_HP_0:
  202. case WM8903_ANALOGUE_LINEOUT_0:
  203. case WM8903_CHARGE_PUMP_0:
  204. case WM8903_CLASS_W_0:
  205. case WM8903_WRITE_SEQUENCER_0:
  206. case WM8903_WRITE_SEQUENCER_1:
  207. case WM8903_WRITE_SEQUENCER_2:
  208. case WM8903_WRITE_SEQUENCER_3:
  209. case WM8903_WRITE_SEQUENCER_4:
  210. case WM8903_CONTROL_INTERFACE:
  211. case WM8903_GPIO_CONTROL_1:
  212. case WM8903_GPIO_CONTROL_2:
  213. case WM8903_GPIO_CONTROL_3:
  214. case WM8903_GPIO_CONTROL_4:
  215. case WM8903_GPIO_CONTROL_5:
  216. case WM8903_INTERRUPT_STATUS_1:
  217. case WM8903_INTERRUPT_STATUS_1_MASK:
  218. case WM8903_INTERRUPT_POLARITY_1:
  219. case WM8903_INTERRUPT_CONTROL:
  220. case WM8903_CLOCK_RATE_TEST_4:
  221. case WM8903_ANALOGUE_OUTPUT_BIAS_0:
  222. return true;
  223. default:
  224. return false;
  225. }
  226. }
  227. static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
  228. {
  229. switch (reg) {
  230. case WM8903_SW_RESET_AND_ID:
  231. case WM8903_REVISION_NUMBER:
  232. case WM8903_INTERRUPT_STATUS_1:
  233. case WM8903_WRITE_SEQUENCER_4:
  234. case WM8903_DC_SERVO_READBACK_1:
  235. case WM8903_DC_SERVO_READBACK_2:
  236. case WM8903_DC_SERVO_READBACK_3:
  237. case WM8903_DC_SERVO_READBACK_4:
  238. return true;
  239. default:
  240. return false;
  241. }
  242. }
  243. static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
  244. struct snd_kcontrol *kcontrol, int event)
  245. {
  246. WARN_ON(event != SND_SOC_DAPM_POST_PMU);
  247. mdelay(4);
  248. return 0;
  249. }
  250. static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
  251. struct snd_kcontrol *kcontrol, int event)
  252. {
  253. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  254. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  255. switch (event) {
  256. case SND_SOC_DAPM_POST_PMU:
  257. wm8903->dcs_pending |= 1 << w->shift;
  258. break;
  259. case SND_SOC_DAPM_PRE_PMD:
  260. snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
  261. 1 << w->shift, 0);
  262. break;
  263. }
  264. return 0;
  265. }
  266. #define WM8903_DCS_MODE_WRITE_STOP 0
  267. #define WM8903_DCS_MODE_START_STOP 2
  268. static void wm8903_seq_notifier(struct snd_soc_component *component,
  269. enum snd_soc_dapm_type event, int subseq)
  270. {
  271. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  272. int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
  273. int i, val;
  274. /* Complete any pending DC servo starts */
  275. if (wm8903->dcs_pending) {
  276. dev_dbg(component->dev, "Starting DC servo for %x\n",
  277. wm8903->dcs_pending);
  278. /* If we've no cached values then we need to do startup */
  279. for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
  280. if (!(wm8903->dcs_pending & (1 << i)))
  281. continue;
  282. if (wm8903->dcs_cache[i]) {
  283. dev_dbg(component->dev,
  284. "Restore DC servo %d value %x\n",
  285. 3 - i, wm8903->dcs_cache[i]);
  286. snd_soc_component_write(component, WM8903_DC_SERVO_4 + i,
  287. wm8903->dcs_cache[i] & 0xff);
  288. } else {
  289. dev_dbg(component->dev,
  290. "Calibrate DC servo %d\n", 3 - i);
  291. dcs_mode = WM8903_DCS_MODE_START_STOP;
  292. }
  293. }
  294. /* Don't trust the cache for analogue */
  295. if (wm8903->class_w_users)
  296. dcs_mode = WM8903_DCS_MODE_START_STOP;
  297. snd_soc_component_update_bits(component, WM8903_DC_SERVO_2,
  298. WM8903_DCS_MODE_MASK, dcs_mode);
  299. snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
  300. WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
  301. switch (dcs_mode) {
  302. case WM8903_DCS_MODE_WRITE_STOP:
  303. break;
  304. case WM8903_DCS_MODE_START_STOP:
  305. msleep(270);
  306. /* Cache the measured offsets for digital */
  307. if (wm8903->class_w_users)
  308. break;
  309. for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
  310. if (!(wm8903->dcs_pending & (1 << i)))
  311. continue;
  312. val = snd_soc_component_read(component,
  313. WM8903_DC_SERVO_READBACK_1 + i);
  314. dev_dbg(component->dev, "DC servo %d: %x\n",
  315. 3 - i, val);
  316. wm8903->dcs_cache[i] = val;
  317. }
  318. break;
  319. default:
  320. pr_warn("DCS mode %d delay not set\n", dcs_mode);
  321. break;
  322. }
  323. wm8903->dcs_pending = 0;
  324. }
  325. }
  326. /*
  327. * When used with DAC outputs only the WM8903 charge pump supports
  328. * operation in class W mode, providing very low power consumption
  329. * when used with digital sources. Enable and disable this mode
  330. * automatically depending on the mixer configuration.
  331. *
  332. * All the relevant controls are simple switches.
  333. */
  334. static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
  335. struct snd_ctl_elem_value *ucontrol)
  336. {
  337. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  338. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  339. u16 reg;
  340. int ret;
  341. reg = snd_soc_component_read(component, WM8903_CLASS_W_0);
  342. /* Turn it off if we're about to enable bypass */
  343. if (ucontrol->value.integer.value[0]) {
  344. if (wm8903->class_w_users == 0) {
  345. dev_dbg(component->dev, "Disabling Class W\n");
  346. snd_soc_component_write(component, WM8903_CLASS_W_0, reg &
  347. ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
  348. }
  349. wm8903->class_w_users++;
  350. }
  351. /* Implement the change */
  352. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  353. /* If we've just disabled the last bypass path turn Class W on */
  354. if (!ucontrol->value.integer.value[0]) {
  355. if (wm8903->class_w_users == 1) {
  356. dev_dbg(component->dev, "Enabling Class W\n");
  357. snd_soc_component_write(component, WM8903_CLASS_W_0, reg |
  358. WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
  359. }
  360. wm8903->class_w_users--;
  361. }
  362. dev_dbg(component->dev, "Bypass use count now %d\n",
  363. wm8903->class_w_users);
  364. return ret;
  365. }
  366. #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
  367. SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
  368. snd_soc_dapm_get_volsw, wm8903_class_w_put)
  369. static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
  370. static int wm8903_set_deemph(struct snd_soc_component *component)
  371. {
  372. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  373. int val, i, best;
  374. /* If we're using deemphasis select the nearest available sample
  375. * rate.
  376. */
  377. if (wm8903->deemph) {
  378. best = 1;
  379. for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
  380. if (abs(wm8903_deemph[i] - wm8903->fs) <
  381. abs(wm8903_deemph[best] - wm8903->fs))
  382. best = i;
  383. }
  384. val = best << WM8903_DEEMPH_SHIFT;
  385. } else {
  386. best = 0;
  387. val = 0;
  388. }
  389. dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n",
  390. best, wm8903_deemph[best]);
  391. return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1,
  392. WM8903_DEEMPH_MASK, val);
  393. }
  394. static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
  395. struct snd_ctl_elem_value *ucontrol)
  396. {
  397. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  398. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  399. ucontrol->value.integer.value[0] = wm8903->deemph;
  400. return 0;
  401. }
  402. static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
  403. struct snd_ctl_elem_value *ucontrol)
  404. {
  405. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  406. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  407. unsigned int deemph = ucontrol->value.integer.value[0];
  408. int ret = 0;
  409. if (deemph > 1)
  410. return -EINVAL;
  411. mutex_lock(&wm8903->lock);
  412. if (wm8903->deemph != deemph) {
  413. wm8903->deemph = deemph;
  414. wm8903_set_deemph(component);
  415. ret = 1;
  416. }
  417. mutex_unlock(&wm8903->lock);
  418. return ret;
  419. }
  420. /* ALSA can only do steps of .01dB */
  421. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  422. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  423. static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
  424. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  425. static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
  426. static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
  427. static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
  428. static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
  429. static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
  430. static const char *hpf_mode_text[] = {
  431. "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
  432. };
  433. static SOC_ENUM_SINGLE_DECL(hpf_mode,
  434. WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
  435. static const char *osr_text[] = {
  436. "Low power", "High performance"
  437. };
  438. static SOC_ENUM_SINGLE_DECL(adc_osr,
  439. WM8903_ANALOGUE_ADC_0, 0, osr_text);
  440. static SOC_ENUM_SINGLE_DECL(dac_osr,
  441. WM8903_DAC_DIGITAL_1, 0, osr_text);
  442. static const char *drc_slope_text[] = {
  443. "1", "1/2", "1/4", "1/8", "1/16", "0"
  444. };
  445. static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
  446. WM8903_DRC_2, 3, drc_slope_text);
  447. static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
  448. WM8903_DRC_2, 0, drc_slope_text);
  449. static const char *drc_attack_text[] = {
  450. "instantaneous",
  451. "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
  452. "46.4ms", "92.8ms", "185.6ms"
  453. };
  454. static SOC_ENUM_SINGLE_DECL(drc_attack,
  455. WM8903_DRC_1, 12, drc_attack_text);
  456. static const char *drc_decay_text[] = {
  457. "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
  458. "23.87s", "47.56s"
  459. };
  460. static SOC_ENUM_SINGLE_DECL(drc_decay,
  461. WM8903_DRC_1, 8, drc_decay_text);
  462. static const char *drc_ff_delay_text[] = {
  463. "5 samples", "9 samples"
  464. };
  465. static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
  466. WM8903_DRC_0, 5, drc_ff_delay_text);
  467. static const char *drc_qr_decay_text[] = {
  468. "0.725ms", "1.45ms", "5.8ms"
  469. };
  470. static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
  471. WM8903_DRC_1, 4, drc_qr_decay_text);
  472. static const char *drc_smoothing_text[] = {
  473. "Low", "Medium", "High"
  474. };
  475. static SOC_ENUM_SINGLE_DECL(drc_smoothing,
  476. WM8903_DRC_0, 11, drc_smoothing_text);
  477. static const char *soft_mute_text[] = {
  478. "Fast (fs/2)", "Slow (fs/32)"
  479. };
  480. static SOC_ENUM_SINGLE_DECL(soft_mute,
  481. WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
  482. static const char *mute_mode_text[] = {
  483. "Hard", "Soft"
  484. };
  485. static SOC_ENUM_SINGLE_DECL(mute_mode,
  486. WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
  487. static const char *companding_text[] = {
  488. "ulaw", "alaw"
  489. };
  490. static SOC_ENUM_SINGLE_DECL(dac_companding,
  491. WM8903_AUDIO_INTERFACE_0, 0, companding_text);
  492. static SOC_ENUM_SINGLE_DECL(adc_companding,
  493. WM8903_AUDIO_INTERFACE_0, 2, companding_text);
  494. static const char *input_mode_text[] = {
  495. "Single-Ended", "Differential Line", "Differential Mic"
  496. };
  497. static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
  498. WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
  499. static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
  500. WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
  501. static const char *linput_mux_text[] = {
  502. "IN1L", "IN2L", "IN3L"
  503. };
  504. static SOC_ENUM_SINGLE_DECL(linput_enum,
  505. WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
  506. static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
  507. WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
  508. static const char *rinput_mux_text[] = {
  509. "IN1R", "IN2R", "IN3R"
  510. };
  511. static SOC_ENUM_SINGLE_DECL(rinput_enum,
  512. WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
  513. static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
  514. WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
  515. static const char *sidetone_text[] = {
  516. "None", "Left", "Right"
  517. };
  518. static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
  519. WM8903_DAC_DIGITAL_0, 2, sidetone_text);
  520. static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
  521. WM8903_DAC_DIGITAL_0, 0, sidetone_text);
  522. static const char *adcinput_text[] = {
  523. "ADC", "DMIC"
  524. };
  525. static SOC_ENUM_SINGLE_DECL(adcinput_enum,
  526. WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
  527. static const char *aif_text[] = {
  528. "Left", "Right"
  529. };
  530. static SOC_ENUM_SINGLE_DECL(lcapture_enum,
  531. WM8903_AUDIO_INTERFACE_0, 7, aif_text);
  532. static SOC_ENUM_SINGLE_DECL(rcapture_enum,
  533. WM8903_AUDIO_INTERFACE_0, 6, aif_text);
  534. static SOC_ENUM_SINGLE_DECL(lplay_enum,
  535. WM8903_AUDIO_INTERFACE_0, 5, aif_text);
  536. static SOC_ENUM_SINGLE_DECL(rplay_enum,
  537. WM8903_AUDIO_INTERFACE_0, 4, aif_text);
  538. static const struct snd_kcontrol_new wm8903_snd_controls[] = {
  539. /* Input PGAs - No TLV since the scale depends on PGA mode */
  540. SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
  541. 7, 1, 1),
  542. SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
  543. 0, 31, 0),
  544. SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
  545. 6, 1, 0),
  546. SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
  547. 7, 1, 1),
  548. SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
  549. 0, 31, 0),
  550. SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
  551. 6, 1, 0),
  552. /* ADCs */
  553. SOC_ENUM("ADC OSR", adc_osr),
  554. SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
  555. SOC_ENUM("HPF Mode", hpf_mode),
  556. SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
  557. SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
  558. SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
  559. SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
  560. drc_tlv_thresh),
  561. SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
  562. SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
  563. SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
  564. SOC_ENUM("DRC Attack Rate", drc_attack),
  565. SOC_ENUM("DRC Decay Rate", drc_decay),
  566. SOC_ENUM("DRC FF Delay", drc_ff_delay),
  567. SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
  568. SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
  569. SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
  570. SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
  571. SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
  572. SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
  573. SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
  574. SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
  575. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
  576. WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
  577. SOC_ENUM("ADC Companding Mode", adc_companding),
  578. SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
  579. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
  580. 12, 0, digital_sidetone_tlv),
  581. /* DAC */
  582. SOC_ENUM("DAC OSR", dac_osr),
  583. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
  584. WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
  585. SOC_ENUM("DAC Soft Mute Rate", soft_mute),
  586. SOC_ENUM("DAC Mute Mode", mute_mode),
  587. SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
  588. SOC_ENUM("DAC Companding Mode", dac_companding),
  589. SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
  590. SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
  591. dac_boost_tlv),
  592. SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
  593. wm8903_get_deemph, wm8903_put_deemph),
  594. /* Headphones */
  595. SOC_DOUBLE_R("Headphone Switch",
  596. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  597. 8, 1, 1),
  598. SOC_DOUBLE_R("Headphone ZC Switch",
  599. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  600. 6, 1, 0),
  601. SOC_DOUBLE_R_TLV("Headphone Volume",
  602. WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
  603. 0, 63, 0, out_tlv),
  604. /* Line out */
  605. SOC_DOUBLE_R("Line Out Switch",
  606. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  607. 8, 1, 1),
  608. SOC_DOUBLE_R("Line Out ZC Switch",
  609. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  610. 6, 1, 0),
  611. SOC_DOUBLE_R_TLV("Line Out Volume",
  612. WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
  613. 0, 63, 0, out_tlv),
  614. /* Speaker */
  615. SOC_DOUBLE_R("Speaker Switch",
  616. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
  617. SOC_DOUBLE_R("Speaker ZC Switch",
  618. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
  619. SOC_DOUBLE_R_TLV("Speaker Volume",
  620. WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
  621. 0, 63, 0, out_tlv),
  622. };
  623. static const struct snd_kcontrol_new linput_mode_mux =
  624. SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
  625. static const struct snd_kcontrol_new rinput_mode_mux =
  626. SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
  627. static const struct snd_kcontrol_new linput_mux =
  628. SOC_DAPM_ENUM("Left Input Mux", linput_enum);
  629. static const struct snd_kcontrol_new linput_inv_mux =
  630. SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
  631. static const struct snd_kcontrol_new rinput_mux =
  632. SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
  633. static const struct snd_kcontrol_new rinput_inv_mux =
  634. SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
  635. static const struct snd_kcontrol_new lsidetone_mux =
  636. SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
  637. static const struct snd_kcontrol_new rsidetone_mux =
  638. SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
  639. static const struct snd_kcontrol_new adcinput_mux =
  640. SOC_DAPM_ENUM("ADC Input", adcinput_enum);
  641. static const struct snd_kcontrol_new lcapture_mux =
  642. SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
  643. static const struct snd_kcontrol_new rcapture_mux =
  644. SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
  645. static const struct snd_kcontrol_new lplay_mux =
  646. SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
  647. static const struct snd_kcontrol_new rplay_mux =
  648. SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
  649. static const struct snd_kcontrol_new left_output_mixer[] = {
  650. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
  651. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
  652. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
  653. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
  654. };
  655. static const struct snd_kcontrol_new right_output_mixer[] = {
  656. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
  657. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
  658. SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
  659. SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
  660. };
  661. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  662. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
  663. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
  664. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
  665. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
  666. 0, 1, 0),
  667. };
  668. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  669. SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
  670. SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
  671. SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  672. 1, 1, 0),
  673. SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
  674. 0, 1, 0),
  675. };
  676. static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
  677. SND_SOC_DAPM_INPUT("IN1L"),
  678. SND_SOC_DAPM_INPUT("IN1R"),
  679. SND_SOC_DAPM_INPUT("IN2L"),
  680. SND_SOC_DAPM_INPUT("IN2R"),
  681. SND_SOC_DAPM_INPUT("IN3L"),
  682. SND_SOC_DAPM_INPUT("IN3R"),
  683. SND_SOC_DAPM_INPUT("DMICDAT"),
  684. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  685. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  686. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  687. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  688. SND_SOC_DAPM_OUTPUT("LOP"),
  689. SND_SOC_DAPM_OUTPUT("LON"),
  690. SND_SOC_DAPM_OUTPUT("ROP"),
  691. SND_SOC_DAPM_OUTPUT("RON"),
  692. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
  693. SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
  694. SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  695. &linput_inv_mux),
  696. SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
  697. SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
  698. SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
  699. &rinput_inv_mux),
  700. SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
  701. SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
  702. SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
  703. SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
  704. SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
  705. SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
  706. SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
  707. SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
  708. SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
  709. SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
  710. SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
  711. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
  712. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
  713. SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
  714. SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
  715. SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
  716. SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
  717. SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
  718. SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
  719. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
  720. left_output_mixer, ARRAY_SIZE(left_output_mixer)),
  721. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
  722. right_output_mixer, ARRAY_SIZE(right_output_mixer)),
  723. SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
  724. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  725. SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
  726. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  727. SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
  728. 1, 0, NULL, 0),
  729. SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
  730. 0, 0, NULL, 0),
  731. SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
  732. NULL, 0),
  733. SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
  734. NULL, 0),
  735. SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
  736. SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
  737. SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
  738. SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
  739. SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
  740. SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
  741. SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
  742. SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
  743. SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
  744. NULL, 0),
  745. SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
  746. NULL, 0),
  747. SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
  748. NULL, 0),
  749. SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
  750. NULL, 0),
  751. SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
  752. NULL, 0),
  753. SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
  754. NULL, 0),
  755. SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
  756. NULL, 0),
  757. SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
  758. NULL, 0),
  759. SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
  760. SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
  761. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  762. SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
  763. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  764. SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
  765. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  766. SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
  767. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  768. SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
  769. NULL, 0),
  770. SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
  771. NULL, 0),
  772. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
  773. wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
  774. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
  775. SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
  776. };
  777. static const struct snd_soc_dapm_route wm8903_intercon[] = {
  778. { "CLK_DSP", NULL, "CLK_SYS" },
  779. { "MICBIAS", NULL, "CLK_SYS" },
  780. { "HPL_DCS", NULL, "CLK_SYS" },
  781. { "HPR_DCS", NULL, "CLK_SYS" },
  782. { "LINEOUTL_DCS", NULL, "CLK_SYS" },
  783. { "LINEOUTR_DCS", NULL, "CLK_SYS" },
  784. { "Left Input Mux", "IN1L", "IN1L" },
  785. { "Left Input Mux", "IN2L", "IN2L" },
  786. { "Left Input Mux", "IN3L", "IN3L" },
  787. { "Left Input Inverting Mux", "IN1L", "IN1L" },
  788. { "Left Input Inverting Mux", "IN2L", "IN2L" },
  789. { "Left Input Inverting Mux", "IN3L", "IN3L" },
  790. { "Right Input Mux", "IN1R", "IN1R" },
  791. { "Right Input Mux", "IN2R", "IN2R" },
  792. { "Right Input Mux", "IN3R", "IN3R" },
  793. { "Right Input Inverting Mux", "IN1R", "IN1R" },
  794. { "Right Input Inverting Mux", "IN2R", "IN2R" },
  795. { "Right Input Inverting Mux", "IN3R", "IN3R" },
  796. { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
  797. { "Left Input Mode Mux", "Differential Line",
  798. "Left Input Mux" },
  799. { "Left Input Mode Mux", "Differential Line",
  800. "Left Input Inverting Mux" },
  801. { "Left Input Mode Mux", "Differential Mic",
  802. "Left Input Mux" },
  803. { "Left Input Mode Mux", "Differential Mic",
  804. "Left Input Inverting Mux" },
  805. { "Right Input Mode Mux", "Single-Ended",
  806. "Right Input Inverting Mux" },
  807. { "Right Input Mode Mux", "Differential Line",
  808. "Right Input Mux" },
  809. { "Right Input Mode Mux", "Differential Line",
  810. "Right Input Inverting Mux" },
  811. { "Right Input Mode Mux", "Differential Mic",
  812. "Right Input Mux" },
  813. { "Right Input Mode Mux", "Differential Mic",
  814. "Right Input Inverting Mux" },
  815. { "Left Input PGA", NULL, "Left Input Mode Mux" },
  816. { "Right Input PGA", NULL, "Right Input Mode Mux" },
  817. { "Left ADC Input", "ADC", "Left Input PGA" },
  818. { "Left ADC Input", "DMIC", "DMICDAT" },
  819. { "Right ADC Input", "ADC", "Right Input PGA" },
  820. { "Right ADC Input", "DMIC", "DMICDAT" },
  821. { "Left Capture Mux", "Left", "ADCL" },
  822. { "Left Capture Mux", "Right", "ADCR" },
  823. { "Right Capture Mux", "Left", "ADCL" },
  824. { "Right Capture Mux", "Right", "ADCR" },
  825. { "AIFTXL", NULL, "Left Capture Mux" },
  826. { "AIFTXR", NULL, "Right Capture Mux" },
  827. { "ADCL", NULL, "Left ADC Input" },
  828. { "ADCL", NULL, "CLK_DSP" },
  829. { "ADCR", NULL, "Right ADC Input" },
  830. { "ADCR", NULL, "CLK_DSP" },
  831. { "Left Playback Mux", "Left", "AIFRXL" },
  832. { "Left Playback Mux", "Right", "AIFRXR" },
  833. { "Right Playback Mux", "Left", "AIFRXL" },
  834. { "Right Playback Mux", "Right", "AIFRXR" },
  835. { "DACL Sidetone", "Left", "ADCL" },
  836. { "DACL Sidetone", "Right", "ADCR" },
  837. { "DACR Sidetone", "Left", "ADCL" },
  838. { "DACR Sidetone", "Right", "ADCR" },
  839. { "DACL", NULL, "Left Playback Mux" },
  840. { "DACL", NULL, "DACL Sidetone" },
  841. { "DACL", NULL, "CLK_DSP" },
  842. { "DACR", NULL, "Right Playback Mux" },
  843. { "DACR", NULL, "DACR Sidetone" },
  844. { "DACR", NULL, "CLK_DSP" },
  845. { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  846. { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  847. { "Left Output Mixer", "DACL Switch", "DACL" },
  848. { "Left Output Mixer", "DACR Switch", "DACR" },
  849. { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
  850. { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
  851. { "Right Output Mixer", "DACL Switch", "DACL" },
  852. { "Right Output Mixer", "DACR Switch", "DACR" },
  853. { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  854. { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  855. { "Left Speaker Mixer", "DACL Switch", "DACL" },
  856. { "Left Speaker Mixer", "DACR Switch", "DACR" },
  857. { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
  858. { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
  859. { "Right Speaker Mixer", "DACL Switch", "DACL" },
  860. { "Right Speaker Mixer", "DACR Switch", "DACR" },
  861. { "Left Line Output PGA", NULL, "Left Output Mixer" },
  862. { "Right Line Output PGA", NULL, "Right Output Mixer" },
  863. { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
  864. { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
  865. { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
  866. { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
  867. { "HPL_ENA", NULL, "Left Headphone Output PGA" },
  868. { "HPR_ENA", NULL, "Right Headphone Output PGA" },
  869. { "HPL_ENA_DLY", NULL, "HPL_ENA" },
  870. { "HPR_ENA_DLY", NULL, "HPR_ENA" },
  871. { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
  872. { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
  873. { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
  874. { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
  875. { "HPL_DCS", NULL, "DCS Master" },
  876. { "HPR_DCS", NULL, "DCS Master" },
  877. { "LINEOUTL_DCS", NULL, "DCS Master" },
  878. { "LINEOUTR_DCS", NULL, "DCS Master" },
  879. { "HPL_DCS", NULL, "HPL_ENA_DLY" },
  880. { "HPR_DCS", NULL, "HPR_ENA_DLY" },
  881. { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
  882. { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
  883. { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
  884. { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
  885. { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
  886. { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
  887. { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
  888. { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
  889. { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
  890. { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
  891. { "HPOUTL", NULL, "HPL_RMV_SHORT" },
  892. { "HPOUTR", NULL, "HPR_RMV_SHORT" },
  893. { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
  894. { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
  895. { "LOP", NULL, "Left Speaker PGA" },
  896. { "LON", NULL, "Left Speaker PGA" },
  897. { "ROP", NULL, "Right Speaker PGA" },
  898. { "RON", NULL, "Right Speaker PGA" },
  899. { "Charge Pump", NULL, "CLK_DSP" },
  900. { "Left Headphone Output PGA", NULL, "Charge Pump" },
  901. { "Right Headphone Output PGA", NULL, "Charge Pump" },
  902. { "Left Line Output PGA", NULL, "Charge Pump" },
  903. { "Right Line Output PGA", NULL, "Charge Pump" },
  904. };
  905. static int wm8903_set_bias_level(struct snd_soc_component *component,
  906. enum snd_soc_bias_level level)
  907. {
  908. switch (level) {
  909. case SND_SOC_BIAS_ON:
  910. break;
  911. case SND_SOC_BIAS_PREPARE:
  912. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  913. WM8903_VMID_RES_MASK,
  914. WM8903_VMID_RES_50K);
  915. break;
  916. case SND_SOC_BIAS_STANDBY:
  917. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  918. snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
  919. WM8903_POBCTRL | WM8903_ISEL_MASK |
  920. WM8903_STARTUP_BIAS_ENA |
  921. WM8903_BIAS_ENA,
  922. WM8903_POBCTRL |
  923. (2 << WM8903_ISEL_SHIFT) |
  924. WM8903_STARTUP_BIAS_ENA);
  925. snd_soc_component_update_bits(component,
  926. WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
  927. WM8903_SPK_DISCHARGE,
  928. WM8903_SPK_DISCHARGE);
  929. msleep(33);
  930. snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
  931. WM8903_SPKL_ENA | WM8903_SPKR_ENA,
  932. WM8903_SPKL_ENA | WM8903_SPKR_ENA);
  933. snd_soc_component_update_bits(component,
  934. WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
  935. WM8903_SPK_DISCHARGE, 0);
  936. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  937. WM8903_VMID_TIE_ENA |
  938. WM8903_BUFIO_ENA |
  939. WM8903_VMID_IO_ENA |
  940. WM8903_VMID_SOFT_MASK |
  941. WM8903_VMID_RES_MASK |
  942. WM8903_VMID_BUF_ENA,
  943. WM8903_VMID_TIE_ENA |
  944. WM8903_BUFIO_ENA |
  945. WM8903_VMID_IO_ENA |
  946. (2 << WM8903_VMID_SOFT_SHIFT) |
  947. WM8903_VMID_RES_250K |
  948. WM8903_VMID_BUF_ENA);
  949. msleep(129);
  950. snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
  951. WM8903_SPKL_ENA | WM8903_SPKR_ENA,
  952. 0);
  953. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  954. WM8903_VMID_SOFT_MASK, 0);
  955. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  956. WM8903_VMID_RES_MASK,
  957. WM8903_VMID_RES_50K);
  958. snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
  959. WM8903_BIAS_ENA | WM8903_POBCTRL,
  960. WM8903_BIAS_ENA);
  961. /* By default no bypass paths are enabled so
  962. * enable Class W support.
  963. */
  964. dev_dbg(component->dev, "Enabling Class W\n");
  965. snd_soc_component_update_bits(component, WM8903_CLASS_W_0,
  966. WM8903_CP_DYN_FREQ |
  967. WM8903_CP_DYN_V,
  968. WM8903_CP_DYN_FREQ |
  969. WM8903_CP_DYN_V);
  970. }
  971. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  972. WM8903_VMID_RES_MASK,
  973. WM8903_VMID_RES_250K);
  974. break;
  975. case SND_SOC_BIAS_OFF:
  976. snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
  977. WM8903_BIAS_ENA, 0);
  978. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  979. WM8903_VMID_SOFT_MASK,
  980. 2 << WM8903_VMID_SOFT_SHIFT);
  981. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  982. WM8903_VMID_BUF_ENA, 0);
  983. msleep(290);
  984. snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
  985. WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
  986. WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
  987. WM8903_VMID_SOFT_MASK |
  988. WM8903_VMID_BUF_ENA, 0);
  989. snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
  990. WM8903_STARTUP_BIAS_ENA, 0);
  991. break;
  992. }
  993. return 0;
  994. }
  995. static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  996. int clk_id, unsigned int freq, int dir)
  997. {
  998. struct snd_soc_component *component = codec_dai->component;
  999. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  1000. wm8903->sysclk = freq;
  1001. return 0;
  1002. }
  1003. static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1004. unsigned int fmt)
  1005. {
  1006. struct snd_soc_component *component = codec_dai->component;
  1007. u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
  1008. aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
  1009. WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
  1010. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1011. case SND_SOC_DAIFMT_CBS_CFS:
  1012. break;
  1013. case SND_SOC_DAIFMT_CBS_CFM:
  1014. aif1 |= WM8903_LRCLK_DIR;
  1015. break;
  1016. case SND_SOC_DAIFMT_CBM_CFM:
  1017. aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
  1018. break;
  1019. case SND_SOC_DAIFMT_CBM_CFS:
  1020. aif1 |= WM8903_BCLK_DIR;
  1021. break;
  1022. default:
  1023. return -EINVAL;
  1024. }
  1025. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1026. case SND_SOC_DAIFMT_DSP_A:
  1027. aif1 |= 0x3;
  1028. break;
  1029. case SND_SOC_DAIFMT_DSP_B:
  1030. aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
  1031. break;
  1032. case SND_SOC_DAIFMT_I2S:
  1033. aif1 |= 0x2;
  1034. break;
  1035. case SND_SOC_DAIFMT_RIGHT_J:
  1036. aif1 |= 0x1;
  1037. break;
  1038. case SND_SOC_DAIFMT_LEFT_J:
  1039. break;
  1040. default:
  1041. return -EINVAL;
  1042. }
  1043. /* Clock inversion */
  1044. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1045. case SND_SOC_DAIFMT_DSP_A:
  1046. case SND_SOC_DAIFMT_DSP_B:
  1047. /* frame inversion not valid for DSP modes */
  1048. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1049. case SND_SOC_DAIFMT_NB_NF:
  1050. break;
  1051. case SND_SOC_DAIFMT_IB_NF:
  1052. aif1 |= WM8903_AIF_BCLK_INV;
  1053. break;
  1054. default:
  1055. return -EINVAL;
  1056. }
  1057. break;
  1058. case SND_SOC_DAIFMT_I2S:
  1059. case SND_SOC_DAIFMT_RIGHT_J:
  1060. case SND_SOC_DAIFMT_LEFT_J:
  1061. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1062. case SND_SOC_DAIFMT_NB_NF:
  1063. break;
  1064. case SND_SOC_DAIFMT_IB_IF:
  1065. aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
  1066. break;
  1067. case SND_SOC_DAIFMT_IB_NF:
  1068. aif1 |= WM8903_AIF_BCLK_INV;
  1069. break;
  1070. case SND_SOC_DAIFMT_NB_IF:
  1071. aif1 |= WM8903_AIF_LRCLK_INV;
  1072. break;
  1073. default:
  1074. return -EINVAL;
  1075. }
  1076. break;
  1077. default:
  1078. return -EINVAL;
  1079. }
  1080. snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
  1081. return 0;
  1082. }
  1083. static int wm8903_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  1084. {
  1085. struct snd_soc_component *component = codec_dai->component;
  1086. u16 reg;
  1087. reg = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
  1088. if (mute)
  1089. reg |= WM8903_DAC_MUTE;
  1090. else
  1091. reg &= ~WM8903_DAC_MUTE;
  1092. snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg);
  1093. return 0;
  1094. }
  1095. /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
  1096. * for optimal performance so we list the lower rates first and match
  1097. * on the last match we find. */
  1098. static struct {
  1099. int div;
  1100. int rate;
  1101. int mode;
  1102. int mclk_div;
  1103. } clk_sys_ratios[] = {
  1104. { 64, 0x0, 0x0, 1 },
  1105. { 68, 0x0, 0x1, 1 },
  1106. { 125, 0x0, 0x2, 1 },
  1107. { 128, 0x1, 0x0, 1 },
  1108. { 136, 0x1, 0x1, 1 },
  1109. { 192, 0x2, 0x0, 1 },
  1110. { 204, 0x2, 0x1, 1 },
  1111. { 64, 0x0, 0x0, 2 },
  1112. { 68, 0x0, 0x1, 2 },
  1113. { 125, 0x0, 0x2, 2 },
  1114. { 128, 0x1, 0x0, 2 },
  1115. { 136, 0x1, 0x1, 2 },
  1116. { 192, 0x2, 0x0, 2 },
  1117. { 204, 0x2, 0x1, 2 },
  1118. { 250, 0x2, 0x2, 1 },
  1119. { 256, 0x3, 0x0, 1 },
  1120. { 272, 0x3, 0x1, 1 },
  1121. { 384, 0x4, 0x0, 1 },
  1122. { 408, 0x4, 0x1, 1 },
  1123. { 375, 0x4, 0x2, 1 },
  1124. { 512, 0x5, 0x0, 1 },
  1125. { 544, 0x5, 0x1, 1 },
  1126. { 500, 0x5, 0x2, 1 },
  1127. { 768, 0x6, 0x0, 1 },
  1128. { 816, 0x6, 0x1, 1 },
  1129. { 750, 0x6, 0x2, 1 },
  1130. { 1024, 0x7, 0x0, 1 },
  1131. { 1088, 0x7, 0x1, 1 },
  1132. { 1000, 0x7, 0x2, 1 },
  1133. { 1408, 0x8, 0x0, 1 },
  1134. { 1496, 0x8, 0x1, 1 },
  1135. { 1536, 0x9, 0x0, 1 },
  1136. { 1632, 0x9, 0x1, 1 },
  1137. { 1500, 0x9, 0x2, 1 },
  1138. { 250, 0x2, 0x2, 2 },
  1139. { 256, 0x3, 0x0, 2 },
  1140. { 272, 0x3, 0x1, 2 },
  1141. { 384, 0x4, 0x0, 2 },
  1142. { 408, 0x4, 0x1, 2 },
  1143. { 375, 0x4, 0x2, 2 },
  1144. { 512, 0x5, 0x0, 2 },
  1145. { 544, 0x5, 0x1, 2 },
  1146. { 500, 0x5, 0x2, 2 },
  1147. { 768, 0x6, 0x0, 2 },
  1148. { 816, 0x6, 0x1, 2 },
  1149. { 750, 0x6, 0x2, 2 },
  1150. { 1024, 0x7, 0x0, 2 },
  1151. { 1088, 0x7, 0x1, 2 },
  1152. { 1000, 0x7, 0x2, 2 },
  1153. { 1408, 0x8, 0x0, 2 },
  1154. { 1496, 0x8, 0x1, 2 },
  1155. { 1536, 0x9, 0x0, 2 },
  1156. { 1632, 0x9, 0x1, 2 },
  1157. { 1500, 0x9, 0x2, 2 },
  1158. };
  1159. /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
  1160. static struct {
  1161. int ratio;
  1162. int div;
  1163. } bclk_divs[] = {
  1164. { 10, 0 },
  1165. { 20, 2 },
  1166. { 30, 3 },
  1167. { 40, 4 },
  1168. { 50, 5 },
  1169. { 60, 7 },
  1170. { 80, 8 },
  1171. { 100, 9 },
  1172. { 120, 11 },
  1173. { 160, 12 },
  1174. { 200, 13 },
  1175. { 220, 14 },
  1176. { 240, 15 },
  1177. { 300, 17 },
  1178. { 320, 18 },
  1179. { 440, 19 },
  1180. { 480, 20 },
  1181. };
  1182. /* Sample rates for DSP */
  1183. static struct {
  1184. int rate;
  1185. int value;
  1186. } sample_rates[] = {
  1187. { 8000, 0 },
  1188. { 11025, 1 },
  1189. { 12000, 2 },
  1190. { 16000, 3 },
  1191. { 22050, 4 },
  1192. { 24000, 5 },
  1193. { 32000, 6 },
  1194. { 44100, 7 },
  1195. { 48000, 8 },
  1196. { 88200, 9 },
  1197. { 96000, 10 },
  1198. { 0, 0 },
  1199. };
  1200. static int wm8903_hw_params(struct snd_pcm_substream *substream,
  1201. struct snd_pcm_hw_params *params,
  1202. struct snd_soc_dai *dai)
  1203. {
  1204. struct snd_soc_component *component = dai->component;
  1205. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  1206. int fs = params_rate(params);
  1207. int bclk;
  1208. int bclk_div;
  1209. int i;
  1210. int dsp_config;
  1211. int clk_config;
  1212. int best_val;
  1213. int cur_val;
  1214. int clk_sys;
  1215. u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
  1216. u16 aif2 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_2);
  1217. u16 aif3 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_3);
  1218. u16 clock0 = snd_soc_component_read(component, WM8903_CLOCK_RATES_0);
  1219. u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1);
  1220. u16 dac_digital1 = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
  1221. /* Enable sloping stopband filter for low sample rates */
  1222. if (fs <= 24000)
  1223. dac_digital1 |= WM8903_DAC_SB_FILT;
  1224. else
  1225. dac_digital1 &= ~WM8903_DAC_SB_FILT;
  1226. /* Configure sample rate logic for DSP - choose nearest rate */
  1227. dsp_config = 0;
  1228. best_val = abs(sample_rates[dsp_config].rate - fs);
  1229. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1230. cur_val = abs(sample_rates[i].rate - fs);
  1231. if (cur_val <= best_val) {
  1232. dsp_config = i;
  1233. best_val = cur_val;
  1234. }
  1235. }
  1236. dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
  1237. clock1 &= ~WM8903_SAMPLE_RATE_MASK;
  1238. clock1 |= sample_rates[dsp_config].value;
  1239. aif1 &= ~WM8903_AIF_WL_MASK;
  1240. bclk = 2 * fs;
  1241. switch (params_width(params)) {
  1242. case 16:
  1243. bclk *= 16;
  1244. break;
  1245. case 20:
  1246. bclk *= 20;
  1247. aif1 |= 0x4;
  1248. break;
  1249. case 24:
  1250. bclk *= 24;
  1251. aif1 |= 0x8;
  1252. break;
  1253. case 32:
  1254. bclk *= 32;
  1255. aif1 |= 0xc;
  1256. break;
  1257. default:
  1258. return -EINVAL;
  1259. }
  1260. dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n",
  1261. wm8903->sysclk, fs);
  1262. /* We may not have an MCLK which allows us to generate exactly
  1263. * the clock we want, particularly with USB derived inputs, so
  1264. * approximate.
  1265. */
  1266. clk_config = 0;
  1267. best_val = abs((wm8903->sysclk /
  1268. (clk_sys_ratios[0].mclk_div *
  1269. clk_sys_ratios[0].div)) - fs);
  1270. for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
  1271. cur_val = abs((wm8903->sysclk /
  1272. (clk_sys_ratios[i].mclk_div *
  1273. clk_sys_ratios[i].div)) - fs);
  1274. if (cur_val <= best_val) {
  1275. clk_config = i;
  1276. best_val = cur_val;
  1277. }
  1278. }
  1279. if (clk_sys_ratios[clk_config].mclk_div == 2) {
  1280. clock0 |= WM8903_MCLKDIV2;
  1281. clk_sys = wm8903->sysclk / 2;
  1282. } else {
  1283. clock0 &= ~WM8903_MCLKDIV2;
  1284. clk_sys = wm8903->sysclk;
  1285. }
  1286. clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
  1287. WM8903_CLK_SYS_MODE_MASK);
  1288. clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
  1289. clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
  1290. dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
  1291. clk_sys_ratios[clk_config].rate,
  1292. clk_sys_ratios[clk_config].mode,
  1293. clk_sys_ratios[clk_config].div);
  1294. dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
  1295. /* We may not get quite the right frequency if using
  1296. * approximate clocks so look for the closest match that is
  1297. * higher than the target (we need to ensure that there enough
  1298. * BCLKs to clock out the samples).
  1299. */
  1300. bclk_div = 0;
  1301. i = 1;
  1302. while (i < ARRAY_SIZE(bclk_divs)) {
  1303. cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
  1304. if (cur_val < 0) /* BCLK table is sorted */
  1305. break;
  1306. bclk_div = i;
  1307. i++;
  1308. }
  1309. aif2 &= ~WM8903_BCLK_DIV_MASK;
  1310. aif3 &= ~WM8903_LRCLK_RATE_MASK;
  1311. dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
  1312. bclk_divs[bclk_div].ratio / 10, bclk,
  1313. (clk_sys * 10) / bclk_divs[bclk_div].ratio);
  1314. aif2 |= bclk_divs[bclk_div].div;
  1315. aif3 |= bclk / fs;
  1316. wm8903->fs = params_rate(params);
  1317. wm8903_set_deemph(component);
  1318. snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0);
  1319. snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1);
  1320. snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
  1321. snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2);
  1322. snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3);
  1323. snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1);
  1324. return 0;
  1325. }
  1326. /**
  1327. * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
  1328. *
  1329. * @component: WM8903 component
  1330. * @jack: jack to report detection events on
  1331. * @det: value to report for presence detection
  1332. * @shrt: value to report for short detection
  1333. *
  1334. * Enable microphone detection via IRQ on the WM8903. If GPIOs are
  1335. * being used to bring out signals to the processor then only platform
  1336. * data configuration is needed for WM8903 and processor GPIOs should
  1337. * be configured using snd_soc_jack_add_gpios() instead.
  1338. *
  1339. * The current threasholds for detection should be configured using
  1340. * micdet_cfg in the platform data. Using this function will force on
  1341. * the microphone bias for the device.
  1342. */
  1343. int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
  1344. int det, int shrt)
  1345. {
  1346. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  1347. int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
  1348. dev_dbg(component->dev, "Enabling microphone detection: %x %x\n",
  1349. det, shrt);
  1350. /* Store the configuration */
  1351. wm8903->mic_jack = jack;
  1352. wm8903->mic_det = det;
  1353. wm8903->mic_short = shrt;
  1354. /* Enable interrupts we've got a report configured for */
  1355. if (det)
  1356. irq_mask &= ~WM8903_MICDET_EINT;
  1357. if (shrt)
  1358. irq_mask &= ~WM8903_MICSHRT_EINT;
  1359. snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK,
  1360. WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
  1361. irq_mask);
  1362. if (det || shrt) {
  1363. /* Enable mic detection, this may not have been set through
  1364. * platform data (eg, if the defaults are OK). */
  1365. snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0,
  1366. WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
  1367. snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
  1368. WM8903_MICDET_ENA, WM8903_MICDET_ENA);
  1369. } else {
  1370. snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
  1371. WM8903_MICDET_ENA, 0);
  1372. }
  1373. return 0;
  1374. }
  1375. EXPORT_SYMBOL_GPL(wm8903_mic_detect);
  1376. static irqreturn_t wm8903_irq(int irq, void *data)
  1377. {
  1378. struct wm8903_priv *wm8903 = data;
  1379. int mic_report, ret;
  1380. unsigned int int_val, mask, int_pol;
  1381. ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
  1382. &mask);
  1383. if (ret != 0) {
  1384. dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
  1385. return IRQ_NONE;
  1386. }
  1387. ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
  1388. if (ret != 0) {
  1389. dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
  1390. return IRQ_NONE;
  1391. }
  1392. int_val &= ~mask;
  1393. if (int_val & WM8903_WSEQ_BUSY_EINT) {
  1394. dev_warn(wm8903->dev, "Write sequencer done\n");
  1395. }
  1396. /*
  1397. * The rest is microphone jack detection. We need to manually
  1398. * invert the polarity of the interrupt after each event - to
  1399. * simplify the code keep track of the last state we reported
  1400. * and just invert the relevant bits in both the report and
  1401. * the polarity register.
  1402. */
  1403. mic_report = wm8903->mic_last_report;
  1404. ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
  1405. &int_pol);
  1406. if (ret != 0) {
  1407. dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
  1408. ret);
  1409. return IRQ_HANDLED;
  1410. }
  1411. #ifndef CONFIG_SND_SOC_WM8903_MODULE
  1412. if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
  1413. trace_snd_soc_jack_irq(dev_name(wm8903->dev));
  1414. #endif
  1415. if (int_val & WM8903_MICSHRT_EINT) {
  1416. dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
  1417. mic_report ^= wm8903->mic_short;
  1418. int_pol ^= WM8903_MICSHRT_INV;
  1419. }
  1420. if (int_val & WM8903_MICDET_EINT) {
  1421. dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
  1422. mic_report ^= wm8903->mic_det;
  1423. int_pol ^= WM8903_MICDET_INV;
  1424. msleep(wm8903->mic_delay);
  1425. }
  1426. regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
  1427. WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
  1428. snd_soc_jack_report(wm8903->mic_jack, mic_report,
  1429. wm8903->mic_short | wm8903->mic_det);
  1430. wm8903->mic_last_report = mic_report;
  1431. return IRQ_HANDLED;
  1432. }
  1433. #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
  1434. SNDRV_PCM_RATE_11025 | \
  1435. SNDRV_PCM_RATE_16000 | \
  1436. SNDRV_PCM_RATE_22050 | \
  1437. SNDRV_PCM_RATE_32000 | \
  1438. SNDRV_PCM_RATE_44100 | \
  1439. SNDRV_PCM_RATE_48000 | \
  1440. SNDRV_PCM_RATE_88200 | \
  1441. SNDRV_PCM_RATE_96000)
  1442. #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
  1443. SNDRV_PCM_RATE_11025 | \
  1444. SNDRV_PCM_RATE_16000 | \
  1445. SNDRV_PCM_RATE_22050 | \
  1446. SNDRV_PCM_RATE_32000 | \
  1447. SNDRV_PCM_RATE_44100 | \
  1448. SNDRV_PCM_RATE_48000)
  1449. #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1450. SNDRV_PCM_FMTBIT_S20_3LE |\
  1451. SNDRV_PCM_FMTBIT_S24_LE)
  1452. static const struct snd_soc_dai_ops wm8903_dai_ops = {
  1453. .hw_params = wm8903_hw_params,
  1454. .mute_stream = wm8903_mute,
  1455. .set_fmt = wm8903_set_dai_fmt,
  1456. .set_sysclk = wm8903_set_dai_sysclk,
  1457. .no_capture_mute = 1,
  1458. };
  1459. static struct snd_soc_dai_driver wm8903_dai = {
  1460. .name = "wm8903-hifi",
  1461. .playback = {
  1462. .stream_name = "Playback",
  1463. .channels_min = 2,
  1464. .channels_max = 2,
  1465. .rates = WM8903_PLAYBACK_RATES,
  1466. .formats = WM8903_FORMATS,
  1467. },
  1468. .capture = {
  1469. .stream_name = "Capture",
  1470. .channels_min = 2,
  1471. .channels_max = 2,
  1472. .rates = WM8903_CAPTURE_RATES,
  1473. .formats = WM8903_FORMATS,
  1474. },
  1475. .ops = &wm8903_dai_ops,
  1476. .symmetric_rate = 1,
  1477. };
  1478. static int wm8903_resume(struct snd_soc_component *component)
  1479. {
  1480. struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
  1481. regcache_sync(wm8903->regmap);
  1482. return 0;
  1483. }
  1484. #ifdef CONFIG_GPIOLIB
  1485. static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
  1486. {
  1487. if (offset >= WM8903_NUM_GPIO)
  1488. return -EINVAL;
  1489. return 0;
  1490. }
  1491. static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  1492. {
  1493. struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
  1494. unsigned int mask, val;
  1495. int ret;
  1496. mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
  1497. val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
  1498. WM8903_GP1_DIR;
  1499. ret = regmap_update_bits(wm8903->regmap,
  1500. WM8903_GPIO_CONTROL_1 + offset, mask, val);
  1501. if (ret < 0)
  1502. return ret;
  1503. return 0;
  1504. }
  1505. static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
  1506. {
  1507. struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
  1508. unsigned int reg;
  1509. regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
  1510. return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT);
  1511. }
  1512. static int wm8903_gpio_direction_out(struct gpio_chip *chip,
  1513. unsigned offset, int value)
  1514. {
  1515. struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
  1516. unsigned int mask, val;
  1517. int ret;
  1518. mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
  1519. val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
  1520. (value << WM8903_GP2_LVL_SHIFT);
  1521. ret = regmap_update_bits(wm8903->regmap,
  1522. WM8903_GPIO_CONTROL_1 + offset, mask, val);
  1523. if (ret < 0)
  1524. return ret;
  1525. return 0;
  1526. }
  1527. static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  1528. {
  1529. struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
  1530. regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
  1531. WM8903_GP1_LVL_MASK,
  1532. !!value << WM8903_GP1_LVL_SHIFT);
  1533. }
  1534. static const struct gpio_chip wm8903_template_chip = {
  1535. .label = "wm8903",
  1536. .owner = THIS_MODULE,
  1537. .request = wm8903_gpio_request,
  1538. .direction_input = wm8903_gpio_direction_in,
  1539. .get = wm8903_gpio_get,
  1540. .direction_output = wm8903_gpio_direction_out,
  1541. .set = wm8903_gpio_set,
  1542. .can_sleep = 1,
  1543. };
  1544. static void wm8903_init_gpio(struct wm8903_priv *wm8903)
  1545. {
  1546. struct wm8903_platform_data *pdata = wm8903->pdata;
  1547. int ret;
  1548. wm8903->gpio_chip = wm8903_template_chip;
  1549. wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
  1550. wm8903->gpio_chip.parent = wm8903->dev;
  1551. if (pdata->gpio_base)
  1552. wm8903->gpio_chip.base = pdata->gpio_base;
  1553. else
  1554. wm8903->gpio_chip.base = -1;
  1555. ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903);
  1556. if (ret != 0)
  1557. dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
  1558. }
  1559. static void wm8903_free_gpio(struct wm8903_priv *wm8903)
  1560. {
  1561. gpiochip_remove(&wm8903->gpio_chip);
  1562. }
  1563. #else
  1564. static void wm8903_init_gpio(struct wm8903_priv *wm8903)
  1565. {
  1566. }
  1567. static void wm8903_free_gpio(struct wm8903_priv *wm8903)
  1568. {
  1569. }
  1570. #endif
  1571. static const struct snd_soc_component_driver soc_component_dev_wm8903 = {
  1572. .resume = wm8903_resume,
  1573. .set_bias_level = wm8903_set_bias_level,
  1574. .seq_notifier = wm8903_seq_notifier,
  1575. .controls = wm8903_snd_controls,
  1576. .num_controls = ARRAY_SIZE(wm8903_snd_controls),
  1577. .dapm_widgets = wm8903_dapm_widgets,
  1578. .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
  1579. .dapm_routes = wm8903_intercon,
  1580. .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
  1581. .suspend_bias_off = 1,
  1582. .idle_bias_on = 1,
  1583. .use_pmdown_time = 1,
  1584. .endianness = 1,
  1585. };
  1586. static const struct regmap_config wm8903_regmap = {
  1587. .reg_bits = 8,
  1588. .val_bits = 16,
  1589. .max_register = WM8903_MAX_REGISTER,
  1590. .volatile_reg = wm8903_volatile_register,
  1591. .readable_reg = wm8903_readable_register,
  1592. .cache_type = REGCACHE_RBTREE,
  1593. .reg_defaults = wm8903_reg_defaults,
  1594. .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
  1595. };
  1596. static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
  1597. struct wm8903_platform_data *pdata)
  1598. {
  1599. struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
  1600. if (!irq_data) {
  1601. dev_err(&i2c->dev, "Invalid IRQ: %d\n",
  1602. i2c->irq);
  1603. return -EINVAL;
  1604. }
  1605. switch (irqd_get_trigger_type(irq_data)) {
  1606. case IRQ_TYPE_NONE:
  1607. default:
  1608. /*
  1609. * We assume the controller imposes no restrictions,
  1610. * so we are able to select active-high
  1611. */
  1612. fallthrough;
  1613. case IRQ_TYPE_LEVEL_HIGH:
  1614. pdata->irq_active_low = false;
  1615. break;
  1616. case IRQ_TYPE_LEVEL_LOW:
  1617. pdata->irq_active_low = true;
  1618. break;
  1619. }
  1620. return 0;
  1621. }
  1622. static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
  1623. struct wm8903_platform_data *pdata)
  1624. {
  1625. const struct device_node *np = i2c->dev.of_node;
  1626. u32 val32;
  1627. int i;
  1628. if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
  1629. pdata->micdet_cfg = val32;
  1630. if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
  1631. pdata->micdet_delay = val32;
  1632. if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
  1633. ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
  1634. /*
  1635. * In device tree: 0 means "write 0",
  1636. * 0xffffffff means "don't touch".
  1637. *
  1638. * In platform data: 0 means "don't touch",
  1639. * 0x8000 means "write 0".
  1640. *
  1641. * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
  1642. *
  1643. * Convert from DT to pdata representation here,
  1644. * so no other code needs to change.
  1645. */
  1646. for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
  1647. if (pdata->gpio_cfg[i] == 0) {
  1648. pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
  1649. } else if (pdata->gpio_cfg[i] == 0xffffffff) {
  1650. pdata->gpio_cfg[i] = 0;
  1651. } else if (pdata->gpio_cfg[i] > 0x7fff) {
  1652. dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
  1653. i, pdata->gpio_cfg[i]);
  1654. return -EINVAL;
  1655. }
  1656. }
  1657. }
  1658. return 0;
  1659. }
  1660. static int wm8903_i2c_probe(struct i2c_client *i2c)
  1661. {
  1662. struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1663. struct wm8903_priv *wm8903;
  1664. int trigger;
  1665. bool mic_gpio = false;
  1666. unsigned int val, irq_pol;
  1667. int ret, i;
  1668. wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL);
  1669. if (wm8903 == NULL)
  1670. return -ENOMEM;
  1671. mutex_init(&wm8903->lock);
  1672. wm8903->dev = &i2c->dev;
  1673. wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
  1674. if (IS_ERR(wm8903->regmap)) {
  1675. ret = PTR_ERR(wm8903->regmap);
  1676. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1677. ret);
  1678. return ret;
  1679. }
  1680. i2c_set_clientdata(i2c, wm8903);
  1681. /* If no platform data was supplied, create storage for defaults */
  1682. if (pdata) {
  1683. wm8903->pdata = pdata;
  1684. } else {
  1685. wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata),
  1686. GFP_KERNEL);
  1687. if (!wm8903->pdata)
  1688. return -ENOMEM;
  1689. if (i2c->irq) {
  1690. ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
  1691. if (ret != 0)
  1692. return ret;
  1693. }
  1694. if (i2c->dev.of_node) {
  1695. ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
  1696. if (ret != 0)
  1697. return ret;
  1698. }
  1699. }
  1700. pdata = wm8903->pdata;
  1701. for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++)
  1702. wm8903->supplies[i].supply = wm8903_supply_names[i];
  1703. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies),
  1704. wm8903->supplies);
  1705. if (ret != 0) {
  1706. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  1707. return ret;
  1708. }
  1709. ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies),
  1710. wm8903->supplies);
  1711. if (ret != 0) {
  1712. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  1713. return ret;
  1714. }
  1715. ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
  1716. if (ret != 0) {
  1717. dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
  1718. goto err;
  1719. }
  1720. if (val != 0x8903) {
  1721. dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
  1722. ret = -ENODEV;
  1723. goto err;
  1724. }
  1725. ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
  1726. if (ret != 0) {
  1727. dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
  1728. goto err;
  1729. }
  1730. dev_info(&i2c->dev, "WM8903 revision %c\n",
  1731. (val & WM8903_CHIP_REV_MASK) + 'A');
  1732. /* Reset the device */
  1733. regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
  1734. wm8903_init_gpio(wm8903);
  1735. /* Set up GPIO pin state, detect if any are MIC detect outputs */
  1736. for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
  1737. if ((!pdata->gpio_cfg[i]) ||
  1738. (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
  1739. continue;
  1740. regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
  1741. pdata->gpio_cfg[i] & 0x7fff);
  1742. val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
  1743. >> WM8903_GP1_FN_SHIFT;
  1744. switch (val) {
  1745. case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
  1746. case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
  1747. mic_gpio = true;
  1748. break;
  1749. default:
  1750. break;
  1751. }
  1752. }
  1753. /* Set up microphone detection */
  1754. regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
  1755. pdata->micdet_cfg);
  1756. /* Microphone detection needs the WSEQ clock */
  1757. if (pdata->micdet_cfg)
  1758. regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
  1759. WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
  1760. /* If microphone detection is enabled by pdata but
  1761. * detected via IRQ then interrupts can be lost before
  1762. * the machine driver has set up microphone detection
  1763. * IRQs as the IRQs are clear on read. The detection
  1764. * will be enabled when the machine driver configures.
  1765. */
  1766. WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
  1767. wm8903->mic_delay = pdata->micdet_delay;
  1768. if (i2c->irq) {
  1769. if (pdata->irq_active_low) {
  1770. trigger = IRQF_TRIGGER_LOW;
  1771. irq_pol = WM8903_IRQ_POL;
  1772. } else {
  1773. trigger = IRQF_TRIGGER_HIGH;
  1774. irq_pol = 0;
  1775. }
  1776. regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
  1777. WM8903_IRQ_POL, irq_pol);
  1778. ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
  1779. trigger | IRQF_ONESHOT,
  1780. "wm8903", wm8903);
  1781. if (ret != 0) {
  1782. dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
  1783. ret);
  1784. goto err;
  1785. }
  1786. /* Enable write sequencer interrupts */
  1787. regmap_update_bits(wm8903->regmap,
  1788. WM8903_INTERRUPT_STATUS_1_MASK,
  1789. WM8903_IM_WSEQ_BUSY_EINT, 0);
  1790. }
  1791. /* Latch volume update bits */
  1792. regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
  1793. WM8903_ADCVU, WM8903_ADCVU);
  1794. regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
  1795. WM8903_ADCVU, WM8903_ADCVU);
  1796. regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
  1797. WM8903_DACVU, WM8903_DACVU);
  1798. regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
  1799. WM8903_DACVU, WM8903_DACVU);
  1800. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
  1801. WM8903_HPOUTVU, WM8903_HPOUTVU);
  1802. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
  1803. WM8903_HPOUTVU, WM8903_HPOUTVU);
  1804. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
  1805. WM8903_LINEOUTVU, WM8903_LINEOUTVU);
  1806. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
  1807. WM8903_LINEOUTVU, WM8903_LINEOUTVU);
  1808. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
  1809. WM8903_SPKVU, WM8903_SPKVU);
  1810. regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
  1811. WM8903_SPKVU, WM8903_SPKVU);
  1812. /* Enable DAC soft mute by default */
  1813. regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
  1814. WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
  1815. WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
  1816. ret = devm_snd_soc_register_component(&i2c->dev,
  1817. &soc_component_dev_wm8903, &wm8903_dai, 1);
  1818. if (ret != 0)
  1819. goto err;
  1820. return 0;
  1821. err:
  1822. regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
  1823. wm8903->supplies);
  1824. return ret;
  1825. }
  1826. static void wm8903_i2c_remove(struct i2c_client *client)
  1827. {
  1828. struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
  1829. regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
  1830. wm8903->supplies);
  1831. if (client->irq)
  1832. free_irq(client->irq, wm8903);
  1833. wm8903_free_gpio(wm8903);
  1834. }
  1835. static const struct of_device_id wm8903_of_match[] = {
  1836. { .compatible = "wlf,wm8903", },
  1837. {},
  1838. };
  1839. MODULE_DEVICE_TABLE(of, wm8903_of_match);
  1840. static const struct i2c_device_id wm8903_i2c_id[] = {
  1841. { "wm8903", 0 },
  1842. { }
  1843. };
  1844. MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
  1845. static struct i2c_driver wm8903_i2c_driver = {
  1846. .driver = {
  1847. .name = "wm8903",
  1848. .of_match_table = wm8903_of_match,
  1849. },
  1850. .probe_new = wm8903_i2c_probe,
  1851. .remove = wm8903_i2c_remove,
  1852. .id_table = wm8903_i2c_id,
  1853. };
  1854. module_i2c_driver(wm8903_i2c_driver);
  1855. MODULE_DESCRIPTION("ASoC WM8903 driver");
  1856. MODULE_AUTHOR("Mark Brown <[email protected]>");
  1857. MODULE_LICENSE("GPL");