wm8753.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * wm8753.h -- audio driver for WM8753
  4. *
  5. * Copyright 2003 Wolfson Microelectronics PLC.
  6. * Author: Liam Girdwood <[email protected]>
  7. */
  8. #ifndef _WM8753_H
  9. #define _WM8753_H
  10. /* WM8753 register space */
  11. #define WM8753_DAC 0x01
  12. #define WM8753_ADC 0x02
  13. #define WM8753_PCM 0x03
  14. #define WM8753_HIFI 0x04
  15. #define WM8753_IOCTL 0x05
  16. #define WM8753_SRATE1 0x06
  17. #define WM8753_SRATE2 0x07
  18. #define WM8753_LDAC 0x08
  19. #define WM8753_RDAC 0x09
  20. #define WM8753_BASS 0x0a
  21. #define WM8753_TREBLE 0x0b
  22. #define WM8753_ALC1 0x0c
  23. #define WM8753_ALC2 0x0d
  24. #define WM8753_ALC3 0x0e
  25. #define WM8753_NGATE 0x0f
  26. #define WM8753_LADC 0x10
  27. #define WM8753_RADC 0x11
  28. #define WM8753_ADCTL1 0x12
  29. #define WM8753_3D 0x13
  30. #define WM8753_PWR1 0x14
  31. #define WM8753_PWR2 0x15
  32. #define WM8753_PWR3 0x16
  33. #define WM8753_PWR4 0x17
  34. #define WM8753_ID 0x18
  35. #define WM8753_INTPOL 0x19
  36. #define WM8753_INTEN 0x1a
  37. #define WM8753_GPIO1 0x1b
  38. #define WM8753_GPIO2 0x1c
  39. #define WM8753_RESET 0x1f
  40. #define WM8753_RECMIX1 0x20
  41. #define WM8753_RECMIX2 0x21
  42. #define WM8753_LOUTM1 0x22
  43. #define WM8753_LOUTM2 0x23
  44. #define WM8753_ROUTM1 0x24
  45. #define WM8753_ROUTM2 0x25
  46. #define WM8753_MOUTM1 0x26
  47. #define WM8753_MOUTM2 0x27
  48. #define WM8753_LOUT1V 0x28
  49. #define WM8753_ROUT1V 0x29
  50. #define WM8753_LOUT2V 0x2a
  51. #define WM8753_ROUT2V 0x2b
  52. #define WM8753_MOUTV 0x2c
  53. #define WM8753_OUTCTL 0x2d
  54. #define WM8753_ADCIN 0x2e
  55. #define WM8753_INCTL1 0x2f
  56. #define WM8753_INCTL2 0x30
  57. #define WM8753_LINVOL 0x31
  58. #define WM8753_RINVOL 0x32
  59. #define WM8753_MICBIAS 0x33
  60. #define WM8753_CLOCK 0x34
  61. #define WM8753_PLL1CTL1 0x35
  62. #define WM8753_PLL1CTL2 0x36
  63. #define WM8753_PLL1CTL3 0x37
  64. #define WM8753_PLL1CTL4 0x38
  65. #define WM8753_PLL2CTL1 0x39
  66. #define WM8753_PLL2CTL2 0x3a
  67. #define WM8753_PLL2CTL3 0x3b
  68. #define WM8753_PLL2CTL4 0x3c
  69. #define WM8753_BIASCTL 0x3d
  70. #define WM8753_ADCTL2 0x3f
  71. #define WM8753_PLL1 0
  72. #define WM8753_PLL2 1
  73. /* clock inputs */
  74. #define WM8753_MCLK 0
  75. #define WM8753_PCMCLK 1
  76. /* clock divider id's */
  77. #define WM8753_PCMDIV 0
  78. #define WM8753_BCLKDIV 1
  79. #define WM8753_VXCLKDIV 2
  80. /* PCM clock dividers */
  81. #define WM8753_PCM_DIV_1 (0 << 6)
  82. #define WM8753_PCM_DIV_3 (2 << 6)
  83. #define WM8753_PCM_DIV_5_5 (3 << 6)
  84. #define WM8753_PCM_DIV_2 (4 << 6)
  85. #define WM8753_PCM_DIV_4 (5 << 6)
  86. #define WM8753_PCM_DIV_6 (6 << 6)
  87. #define WM8753_PCM_DIV_8 (7 << 6)
  88. /* BCLK clock dividers */
  89. #define WM8753_BCLK_DIV_1 (0 << 3)
  90. #define WM8753_BCLK_DIV_2 (1 << 3)
  91. #define WM8753_BCLK_DIV_4 (2 << 3)
  92. #define WM8753_BCLK_DIV_8 (3 << 3)
  93. #define WM8753_BCLK_DIV_16 (4 << 3)
  94. /* VXCLK clock dividers */
  95. #define WM8753_VXCLK_DIV_1 (0 << 6)
  96. #define WM8753_VXCLK_DIV_2 (1 << 6)
  97. #define WM8753_VXCLK_DIV_4 (2 << 6)
  98. #define WM8753_VXCLK_DIV_8 (3 << 6)
  99. #define WM8753_VXCLK_DIV_16 (4 << 6)
  100. #endif