wm8580.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
  4. *
  5. * Copyright 2008-12 Wolfson Microelectronics PLC.
  6. *
  7. * Notes:
  8. * The WM8580 is a multichannel codec with S/PDIF support, featuring six
  9. * DAC channels and two ADC channels.
  10. *
  11. * The WM8581 is a multichannel codec with S/PDIF support, featuring eight
  12. * DAC channels and two ADC channels.
  13. *
  14. * Currently only the primary audio interface is supported - S/PDIF and
  15. * the secondary audio interfaces are not.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/i2c.h>
  24. #include <linux/regmap.h>
  25. #include <linux/regulator/consumer.h>
  26. #include <linux/slab.h>
  27. #include <linux/of_device.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/pcm_params.h>
  31. #include <sound/soc.h>
  32. #include <sound/tlv.h>
  33. #include <sound/initval.h>
  34. #include <asm/div64.h>
  35. #include "wm8580.h"
  36. /* WM8580 register space */
  37. #define WM8580_PLLA1 0x00
  38. #define WM8580_PLLA2 0x01
  39. #define WM8580_PLLA3 0x02
  40. #define WM8580_PLLA4 0x03
  41. #define WM8580_PLLB1 0x04
  42. #define WM8580_PLLB2 0x05
  43. #define WM8580_PLLB3 0x06
  44. #define WM8580_PLLB4 0x07
  45. #define WM8580_CLKSEL 0x08
  46. #define WM8580_PAIF1 0x09
  47. #define WM8580_PAIF2 0x0A
  48. #define WM8580_SAIF1 0x0B
  49. #define WM8580_PAIF3 0x0C
  50. #define WM8580_PAIF4 0x0D
  51. #define WM8580_SAIF2 0x0E
  52. #define WM8580_DAC_CONTROL1 0x0F
  53. #define WM8580_DAC_CONTROL2 0x10
  54. #define WM8580_DAC_CONTROL3 0x11
  55. #define WM8580_DAC_CONTROL4 0x12
  56. #define WM8580_DAC_CONTROL5 0x13
  57. #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
  58. #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
  59. #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
  60. #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
  61. #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
  62. #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
  63. #define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
  64. #define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
  65. #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
  66. #define WM8580_ADC_CONTROL1 0x1D
  67. #define WM8580_SPDTXCHAN0 0x1E
  68. #define WM8580_SPDTXCHAN1 0x1F
  69. #define WM8580_SPDTXCHAN2 0x20
  70. #define WM8580_SPDTXCHAN3 0x21
  71. #define WM8580_SPDTXCHAN4 0x22
  72. #define WM8580_SPDTXCHAN5 0x23
  73. #define WM8580_SPDMODE 0x24
  74. #define WM8580_INTMASK 0x25
  75. #define WM8580_GPO1 0x26
  76. #define WM8580_GPO2 0x27
  77. #define WM8580_GPO3 0x28
  78. #define WM8580_GPO4 0x29
  79. #define WM8580_GPO5 0x2A
  80. #define WM8580_INTSTAT 0x2B
  81. #define WM8580_SPDRXCHAN1 0x2C
  82. #define WM8580_SPDRXCHAN2 0x2D
  83. #define WM8580_SPDRXCHAN3 0x2E
  84. #define WM8580_SPDRXCHAN4 0x2F
  85. #define WM8580_SPDRXCHAN5 0x30
  86. #define WM8580_SPDSTAT 0x31
  87. #define WM8580_PWRDN1 0x32
  88. #define WM8580_PWRDN2 0x33
  89. #define WM8580_READBACK 0x34
  90. #define WM8580_RESET 0x35
  91. #define WM8580_MAX_REGISTER 0x35
  92. #define WM8580_DACOSR 0x40
  93. /* PLLB4 (register 7h) */
  94. #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
  95. #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
  96. #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
  97. #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
  98. #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
  99. #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
  100. #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
  101. #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
  102. /* CLKSEL (register 8h) */
  103. #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
  104. #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
  105. #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
  106. /* AIF control 1 (registers 9h-bh) */
  107. #define WM8580_AIF_RATE_MASK 0x7
  108. #define WM8580_AIF_BCLKSEL_MASK 0x18
  109. #define WM8580_AIF_MS 0x20
  110. #define WM8580_AIF_CLKSRC_MASK 0xc0
  111. #define WM8580_AIF_CLKSRC_PLLA 0x40
  112. #define WM8580_AIF_CLKSRC_PLLB 0x40
  113. #define WM8580_AIF_CLKSRC_MCLK 0xc0
  114. /* AIF control 2 (registers ch-eh) */
  115. #define WM8580_AIF_FMT_MASK 0x03
  116. #define WM8580_AIF_FMT_RIGHTJ 0x00
  117. #define WM8580_AIF_FMT_LEFTJ 0x01
  118. #define WM8580_AIF_FMT_I2S 0x02
  119. #define WM8580_AIF_FMT_DSP 0x03
  120. #define WM8580_AIF_LENGTH_MASK 0x0c
  121. #define WM8580_AIF_LENGTH_16 0x00
  122. #define WM8580_AIF_LENGTH_20 0x04
  123. #define WM8580_AIF_LENGTH_24 0x08
  124. #define WM8580_AIF_LENGTH_32 0x0c
  125. #define WM8580_AIF_LRP 0x10
  126. #define WM8580_AIF_BCP 0x20
  127. /* Powerdown Register 1 (register 32h) */
  128. #define WM8580_PWRDN1_PWDN 0x001
  129. #define WM8580_PWRDN1_ALLDACPD 0x040
  130. /* Powerdown Register 2 (register 33h) */
  131. #define WM8580_PWRDN2_OSSCPD 0x001
  132. #define WM8580_PWRDN2_PLLAPD 0x002
  133. #define WM8580_PWRDN2_PLLBPD 0x004
  134. #define WM8580_PWRDN2_SPDIFPD 0x008
  135. #define WM8580_PWRDN2_SPDIFTXD 0x010
  136. #define WM8580_PWRDN2_SPDIFRXD 0x020
  137. #define WM8580_DAC_CONTROL5_MUTEALL 0x10
  138. /*
  139. * wm8580 register cache
  140. * We can't read the WM8580 register space when we
  141. * are using 2 wire for device control, so we cache them instead.
  142. */
  143. static const struct reg_default wm8580_reg_defaults[] = {
  144. { 0, 0x0121 },
  145. { 1, 0x017e },
  146. { 2, 0x007d },
  147. { 3, 0x0014 },
  148. { 4, 0x0121 },
  149. { 5, 0x017e },
  150. { 6, 0x007d },
  151. { 7, 0x0194 },
  152. { 8, 0x0010 },
  153. { 9, 0x0002 },
  154. { 10, 0x0002 },
  155. { 11, 0x00c2 },
  156. { 12, 0x0182 },
  157. { 13, 0x0082 },
  158. { 14, 0x000a },
  159. { 15, 0x0024 },
  160. { 16, 0x0009 },
  161. { 17, 0x0000 },
  162. { 18, 0x00ff },
  163. { 19, 0x0000 },
  164. { 20, 0x00ff },
  165. { 21, 0x00ff },
  166. { 22, 0x00ff },
  167. { 23, 0x00ff },
  168. { 24, 0x00ff },
  169. { 25, 0x00ff },
  170. { 26, 0x00ff },
  171. { 27, 0x00ff },
  172. { 28, 0x01f0 },
  173. { 29, 0x0040 },
  174. { 30, 0x0000 },
  175. { 31, 0x0000 },
  176. { 32, 0x0000 },
  177. { 33, 0x0000 },
  178. { 34, 0x0031 },
  179. { 35, 0x000b },
  180. { 36, 0x0039 },
  181. { 37, 0x0000 },
  182. { 38, 0x0010 },
  183. { 39, 0x0032 },
  184. { 40, 0x0054 },
  185. { 41, 0x0076 },
  186. { 42, 0x0098 },
  187. { 43, 0x0000 },
  188. { 44, 0x0000 },
  189. { 45, 0x0000 },
  190. { 46, 0x0000 },
  191. { 47, 0x0000 },
  192. { 48, 0x0000 },
  193. { 49, 0x0000 },
  194. { 50, 0x005e },
  195. { 51, 0x003e },
  196. { 52, 0x0000 },
  197. };
  198. static bool wm8580_volatile(struct device *dev, unsigned int reg)
  199. {
  200. switch (reg) {
  201. case WM8580_RESET:
  202. return true;
  203. default:
  204. return false;
  205. }
  206. }
  207. struct pll_state {
  208. unsigned int in;
  209. unsigned int out;
  210. };
  211. #define WM8580_NUM_SUPPLIES 3
  212. static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
  213. "AVDD",
  214. "DVDD",
  215. "PVDD",
  216. };
  217. struct wm8580_driver_data {
  218. int num_dacs;
  219. };
  220. /* codec private data */
  221. struct wm8580_priv {
  222. struct regmap *regmap;
  223. struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
  224. struct pll_state a;
  225. struct pll_state b;
  226. const struct wm8580_driver_data *drvdata;
  227. int sysclk[2];
  228. };
  229. static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
  230. static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
  231. struct snd_ctl_elem_value *ucontrol)
  232. {
  233. struct soc_mixer_control *mc =
  234. (struct soc_mixer_control *)kcontrol->private_value;
  235. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  236. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  237. unsigned int reg = mc->reg;
  238. unsigned int reg2 = mc->rreg;
  239. int ret;
  240. /* Clear the register cache VU so we write without VU set */
  241. regcache_cache_only(wm8580->regmap, true);
  242. regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
  243. regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
  244. regcache_cache_only(wm8580->regmap, false);
  245. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  246. if (ret < 0)
  247. return ret;
  248. /* Now write again with the volume update bit set */
  249. snd_soc_component_update_bits(component, reg, 0x100, 0x100);
  250. snd_soc_component_update_bits(component, reg2, 0x100, 0x100);
  251. return 0;
  252. }
  253. static const struct snd_kcontrol_new wm8580_snd_controls[] = {
  254. SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
  255. WM8580_DIGITAL_ATTENUATION_DACL1,
  256. WM8580_DIGITAL_ATTENUATION_DACR1,
  257. 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
  258. SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
  259. WM8580_DIGITAL_ATTENUATION_DACL2,
  260. WM8580_DIGITAL_ATTENUATION_DACR2,
  261. 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
  262. SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
  263. WM8580_DIGITAL_ATTENUATION_DACL3,
  264. WM8580_DIGITAL_ATTENUATION_DACR3,
  265. 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
  266. SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
  267. SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
  268. SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
  269. SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
  270. SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
  271. SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
  272. SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
  273. SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
  274. SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
  275. SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
  276. SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
  277. SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
  278. };
  279. static const struct snd_kcontrol_new wm8581_snd_controls[] = {
  280. SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
  281. WM8581_DIGITAL_ATTENUATION_DACL4,
  282. WM8581_DIGITAL_ATTENUATION_DACR4,
  283. 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
  284. SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
  285. SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
  286. SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
  287. };
  288. static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
  289. SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
  290. SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
  291. SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
  292. SND_SOC_DAPM_OUTPUT("VOUT1L"),
  293. SND_SOC_DAPM_OUTPUT("VOUT1R"),
  294. SND_SOC_DAPM_OUTPUT("VOUT2L"),
  295. SND_SOC_DAPM_OUTPUT("VOUT2R"),
  296. SND_SOC_DAPM_OUTPUT("VOUT3L"),
  297. SND_SOC_DAPM_OUTPUT("VOUT3R"),
  298. SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
  299. SND_SOC_DAPM_INPUT("AINL"),
  300. SND_SOC_DAPM_INPUT("AINR"),
  301. };
  302. static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
  303. SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
  304. SND_SOC_DAPM_OUTPUT("VOUT4L"),
  305. SND_SOC_DAPM_OUTPUT("VOUT4R"),
  306. };
  307. static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
  308. { "VOUT1L", NULL, "DAC1" },
  309. { "VOUT1R", NULL, "DAC1" },
  310. { "VOUT2L", NULL, "DAC2" },
  311. { "VOUT2R", NULL, "DAC2" },
  312. { "VOUT3L", NULL, "DAC3" },
  313. { "VOUT3R", NULL, "DAC3" },
  314. { "ADC", NULL, "AINL" },
  315. { "ADC", NULL, "AINR" },
  316. };
  317. static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
  318. { "VOUT4L", NULL, "DAC4" },
  319. { "VOUT4R", NULL, "DAC4" },
  320. };
  321. /* PLL divisors */
  322. struct _pll_div {
  323. u32 prescale:1;
  324. u32 postscale:1;
  325. u32 freqmode:2;
  326. u32 n:4;
  327. u32 k:24;
  328. };
  329. /* The size in bits of the pll divide */
  330. #define FIXED_PLL_SIZE (1 << 22)
  331. /* PLL rate to output rate divisions */
  332. static struct {
  333. unsigned int div;
  334. unsigned int freqmode;
  335. unsigned int postscale;
  336. } post_table[] = {
  337. { 2, 0, 0 },
  338. { 4, 0, 1 },
  339. { 4, 1, 0 },
  340. { 8, 1, 1 },
  341. { 8, 2, 0 },
  342. { 16, 2, 1 },
  343. { 12, 3, 0 },
  344. { 24, 3, 1 }
  345. };
  346. static int pll_factors(struct _pll_div *pll_div, unsigned int target,
  347. unsigned int source)
  348. {
  349. u64 Kpart;
  350. unsigned int K, Ndiv, Nmod;
  351. int i;
  352. pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
  353. /* Scale the output frequency up; the PLL should run in the
  354. * region of 90-100MHz.
  355. */
  356. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  357. if (target * post_table[i].div >= 90000000 &&
  358. target * post_table[i].div <= 100000000) {
  359. pll_div->freqmode = post_table[i].freqmode;
  360. pll_div->postscale = post_table[i].postscale;
  361. target *= post_table[i].div;
  362. break;
  363. }
  364. }
  365. if (i == ARRAY_SIZE(post_table)) {
  366. printk(KERN_ERR "wm8580: Unable to scale output frequency "
  367. "%u\n", target);
  368. return -EINVAL;
  369. }
  370. Ndiv = target / source;
  371. if (Ndiv < 5) {
  372. source /= 2;
  373. pll_div->prescale = 1;
  374. Ndiv = target / source;
  375. } else
  376. pll_div->prescale = 0;
  377. if ((Ndiv < 5) || (Ndiv > 13)) {
  378. printk(KERN_ERR
  379. "WM8580 N=%u outside supported range\n", Ndiv);
  380. return -EINVAL;
  381. }
  382. pll_div->n = Ndiv;
  383. Nmod = target % source;
  384. Kpart = FIXED_PLL_SIZE * (long long)Nmod;
  385. do_div(Kpart, source);
  386. K = Kpart & 0xFFFFFFFF;
  387. pll_div->k = K;
  388. pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
  389. pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
  390. pll_div->postscale);
  391. return 0;
  392. }
  393. static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
  394. int source, unsigned int freq_in, unsigned int freq_out)
  395. {
  396. int offset;
  397. struct snd_soc_component *component = codec_dai->component;
  398. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  399. struct pll_state *state;
  400. struct _pll_div pll_div;
  401. unsigned int reg;
  402. unsigned int pwr_mask;
  403. int ret;
  404. /* GCC isn't able to work out the ifs below for initialising/using
  405. * pll_div so suppress warnings.
  406. */
  407. memset(&pll_div, 0, sizeof(pll_div));
  408. switch (pll_id) {
  409. case WM8580_PLLA:
  410. state = &wm8580->a;
  411. offset = 0;
  412. pwr_mask = WM8580_PWRDN2_PLLAPD;
  413. break;
  414. case WM8580_PLLB:
  415. state = &wm8580->b;
  416. offset = 4;
  417. pwr_mask = WM8580_PWRDN2_PLLBPD;
  418. break;
  419. default:
  420. return -ENODEV;
  421. }
  422. if (freq_in && freq_out) {
  423. ret = pll_factors(&pll_div, freq_out, freq_in);
  424. if (ret != 0)
  425. return ret;
  426. }
  427. state->in = freq_in;
  428. state->out = freq_out;
  429. /* Always disable the PLL - it is not safe to leave it running
  430. * while reprogramming it.
  431. */
  432. snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask);
  433. if (!freq_in || !freq_out)
  434. return 0;
  435. snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
  436. snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
  437. snd_soc_component_write(component, WM8580_PLLA3 + offset,
  438. (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
  439. reg = snd_soc_component_read(component, WM8580_PLLA4 + offset);
  440. reg &= ~0x1b;
  441. reg |= pll_div.prescale | pll_div.postscale << 1 |
  442. pll_div.freqmode << 3;
  443. snd_soc_component_write(component, WM8580_PLLA4 + offset, reg);
  444. /* All done, turn it on */
  445. snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0);
  446. return 0;
  447. }
  448. static const int wm8580_sysclk_ratios[] = {
  449. 128, 192, 256, 384, 512, 768, 1152,
  450. };
  451. /*
  452. * Set PCM DAI bit size and sample rate.
  453. */
  454. static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
  455. struct snd_pcm_hw_params *params,
  456. struct snd_soc_dai *dai)
  457. {
  458. struct snd_soc_component *component = dai->component;
  459. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  460. u16 paifa = 0;
  461. u16 paifb = 0;
  462. int i, ratio, osr;
  463. /* bit size */
  464. switch (params_width(params)) {
  465. case 16:
  466. paifa |= 0x8;
  467. break;
  468. case 20:
  469. paifa |= 0x0;
  470. paifb |= WM8580_AIF_LENGTH_20;
  471. break;
  472. case 24:
  473. paifa |= 0x0;
  474. paifb |= WM8580_AIF_LENGTH_24;
  475. break;
  476. case 32:
  477. paifa |= 0x0;
  478. paifb |= WM8580_AIF_LENGTH_32;
  479. break;
  480. default:
  481. return -EINVAL;
  482. }
  483. /* Look up the SYSCLK ratio; accept only exact matches */
  484. ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
  485. for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
  486. if (ratio == wm8580_sysclk_ratios[i])
  487. break;
  488. if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
  489. dev_err(component->dev, "Invalid clock ratio %d/%d\n",
  490. wm8580->sysclk[dai->driver->id], params_rate(params));
  491. return -EINVAL;
  492. }
  493. paifa |= i;
  494. dev_dbg(component->dev, "Running at %dfs with %dHz clock\n",
  495. wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
  496. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  497. switch (ratio) {
  498. case 128:
  499. case 192:
  500. osr = WM8580_DACOSR;
  501. dev_dbg(component->dev, "Selecting 64x OSR\n");
  502. break;
  503. default:
  504. osr = 0;
  505. dev_dbg(component->dev, "Selecting 128x OSR\n");
  506. break;
  507. }
  508. snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr);
  509. }
  510. snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id,
  511. WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
  512. paifa);
  513. snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id,
  514. WM8580_AIF_LENGTH_MASK, paifb);
  515. return 0;
  516. }
  517. static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
  518. unsigned int fmt)
  519. {
  520. struct snd_soc_component *component = codec_dai->component;
  521. unsigned int aifa;
  522. unsigned int aifb;
  523. int can_invert_lrclk;
  524. aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id);
  525. aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id);
  526. aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
  527. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  528. case SND_SOC_DAIFMT_CBS_CFS:
  529. aifa &= ~WM8580_AIF_MS;
  530. break;
  531. case SND_SOC_DAIFMT_CBM_CFM:
  532. aifa |= WM8580_AIF_MS;
  533. break;
  534. default:
  535. return -EINVAL;
  536. }
  537. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  538. case SND_SOC_DAIFMT_I2S:
  539. can_invert_lrclk = 1;
  540. aifb |= WM8580_AIF_FMT_I2S;
  541. break;
  542. case SND_SOC_DAIFMT_RIGHT_J:
  543. can_invert_lrclk = 1;
  544. aifb |= WM8580_AIF_FMT_RIGHTJ;
  545. break;
  546. case SND_SOC_DAIFMT_LEFT_J:
  547. can_invert_lrclk = 1;
  548. aifb |= WM8580_AIF_FMT_LEFTJ;
  549. break;
  550. case SND_SOC_DAIFMT_DSP_A:
  551. can_invert_lrclk = 0;
  552. aifb |= WM8580_AIF_FMT_DSP;
  553. break;
  554. case SND_SOC_DAIFMT_DSP_B:
  555. can_invert_lrclk = 0;
  556. aifb |= WM8580_AIF_FMT_DSP;
  557. aifb |= WM8580_AIF_LRP;
  558. break;
  559. default:
  560. return -EINVAL;
  561. }
  562. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  563. case SND_SOC_DAIFMT_NB_NF:
  564. break;
  565. case SND_SOC_DAIFMT_IB_IF:
  566. if (!can_invert_lrclk)
  567. return -EINVAL;
  568. aifb |= WM8580_AIF_BCP;
  569. aifb |= WM8580_AIF_LRP;
  570. break;
  571. case SND_SOC_DAIFMT_IB_NF:
  572. aifb |= WM8580_AIF_BCP;
  573. break;
  574. case SND_SOC_DAIFMT_NB_IF:
  575. if (!can_invert_lrclk)
  576. return -EINVAL;
  577. aifb |= WM8580_AIF_LRP;
  578. break;
  579. default:
  580. return -EINVAL;
  581. }
  582. snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa);
  583. snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb);
  584. return 0;
  585. }
  586. static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  587. int div_id, int div)
  588. {
  589. struct snd_soc_component *component = codec_dai->component;
  590. unsigned int reg;
  591. switch (div_id) {
  592. case WM8580_MCLK:
  593. reg = snd_soc_component_read(component, WM8580_PLLB4);
  594. reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
  595. switch (div) {
  596. case WM8580_CLKSRC_MCLK:
  597. /* Input */
  598. break;
  599. case WM8580_CLKSRC_PLLA:
  600. reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
  601. break;
  602. case WM8580_CLKSRC_PLLB:
  603. reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
  604. break;
  605. case WM8580_CLKSRC_OSC:
  606. reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
  607. break;
  608. default:
  609. return -EINVAL;
  610. }
  611. snd_soc_component_write(component, WM8580_PLLB4, reg);
  612. break;
  613. case WM8580_CLKOUTSRC:
  614. reg = snd_soc_component_read(component, WM8580_PLLB4);
  615. reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
  616. switch (div) {
  617. case WM8580_CLKSRC_NONE:
  618. break;
  619. case WM8580_CLKSRC_PLLA:
  620. reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
  621. break;
  622. case WM8580_CLKSRC_PLLB:
  623. reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
  624. break;
  625. case WM8580_CLKSRC_OSC:
  626. reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
  627. break;
  628. default:
  629. return -EINVAL;
  630. }
  631. snd_soc_component_write(component, WM8580_PLLB4, reg);
  632. break;
  633. default:
  634. return -EINVAL;
  635. }
  636. return 0;
  637. }
  638. static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  639. unsigned int freq, int dir)
  640. {
  641. struct snd_soc_component *component = dai->component;
  642. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  643. int ret, sel, sel_mask, sel_shift;
  644. switch (dai->driver->id) {
  645. case WM8580_DAI_PAIFRX:
  646. sel_mask = 0x3;
  647. sel_shift = 0;
  648. break;
  649. case WM8580_DAI_PAIFTX:
  650. sel_mask = 0xc;
  651. sel_shift = 2;
  652. break;
  653. default:
  654. WARN(1, "Unknown DAI driver ID\n");
  655. return -EINVAL;
  656. }
  657. switch (clk_id) {
  658. case WM8580_CLKSRC_ADCMCLK:
  659. if (dai->driver->id != WM8580_DAI_PAIFTX)
  660. return -EINVAL;
  661. sel = 0 << sel_shift;
  662. break;
  663. case WM8580_CLKSRC_PLLA:
  664. sel = 1 << sel_shift;
  665. break;
  666. case WM8580_CLKSRC_PLLB:
  667. sel = 2 << sel_shift;
  668. break;
  669. case WM8580_CLKSRC_MCLK:
  670. sel = 3 << sel_shift;
  671. break;
  672. default:
  673. dev_err(component->dev, "Unknown clock %d\n", clk_id);
  674. return -EINVAL;
  675. }
  676. /* We really should validate PLL settings but not yet */
  677. wm8580->sysclk[dai->driver->id] = freq;
  678. ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel);
  679. if (ret < 0)
  680. return ret;
  681. return 0;
  682. }
  683. static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  684. {
  685. struct snd_soc_component *component = codec_dai->component;
  686. unsigned int reg;
  687. reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5);
  688. if (mute)
  689. reg |= WM8580_DAC_CONTROL5_MUTEALL;
  690. else
  691. reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
  692. snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg);
  693. return 0;
  694. }
  695. static int wm8580_set_bias_level(struct snd_soc_component *component,
  696. enum snd_soc_bias_level level)
  697. {
  698. switch (level) {
  699. case SND_SOC_BIAS_ON:
  700. case SND_SOC_BIAS_PREPARE:
  701. break;
  702. case SND_SOC_BIAS_STANDBY:
  703. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  704. /* Power up and get individual control of the DACs */
  705. snd_soc_component_update_bits(component, WM8580_PWRDN1,
  706. WM8580_PWRDN1_PWDN |
  707. WM8580_PWRDN1_ALLDACPD, 0);
  708. /* Make VMID high impedance */
  709. snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1,
  710. 0x100, 0);
  711. }
  712. break;
  713. case SND_SOC_BIAS_OFF:
  714. snd_soc_component_update_bits(component, WM8580_PWRDN1,
  715. WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
  716. break;
  717. }
  718. return 0;
  719. }
  720. static int wm8580_playback_startup(struct snd_pcm_substream *substream,
  721. struct snd_soc_dai *dai)
  722. {
  723. struct snd_soc_component *component = dai->component;
  724. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  725. return snd_pcm_hw_constraint_minmax(substream->runtime,
  726. SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
  727. }
  728. #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  729. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  730. static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
  731. .startup = wm8580_playback_startup,
  732. .set_sysclk = wm8580_set_sysclk,
  733. .hw_params = wm8580_paif_hw_params,
  734. .set_fmt = wm8580_set_paif_dai_fmt,
  735. .set_clkdiv = wm8580_set_dai_clkdiv,
  736. .set_pll = wm8580_set_dai_pll,
  737. .mute_stream = wm8580_mute,
  738. .no_capture_mute = 1,
  739. };
  740. static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
  741. .set_sysclk = wm8580_set_sysclk,
  742. .hw_params = wm8580_paif_hw_params,
  743. .set_fmt = wm8580_set_paif_dai_fmt,
  744. .set_clkdiv = wm8580_set_dai_clkdiv,
  745. .set_pll = wm8580_set_dai_pll,
  746. };
  747. static struct snd_soc_dai_driver wm8580_dai[] = {
  748. {
  749. .name = "wm8580-hifi-playback",
  750. .id = WM8580_DAI_PAIFRX,
  751. .playback = {
  752. .stream_name = "Playback",
  753. .channels_min = 1,
  754. .rates = SNDRV_PCM_RATE_8000_192000,
  755. .formats = WM8580_FORMATS,
  756. },
  757. .ops = &wm8580_dai_ops_playback,
  758. },
  759. {
  760. .name = "wm8580-hifi-capture",
  761. .id = WM8580_DAI_PAIFTX,
  762. .capture = {
  763. .stream_name = "Capture",
  764. .channels_min = 2,
  765. .channels_max = 2,
  766. .rates = SNDRV_PCM_RATE_8000_192000,
  767. .formats = WM8580_FORMATS,
  768. },
  769. .ops = &wm8580_dai_ops_capture,
  770. },
  771. };
  772. static int wm8580_probe(struct snd_soc_component *component)
  773. {
  774. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  775. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  776. int ret = 0;
  777. switch (wm8580->drvdata->num_dacs) {
  778. case 4:
  779. snd_soc_add_component_controls(component, wm8581_snd_controls,
  780. ARRAY_SIZE(wm8581_snd_controls));
  781. snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
  782. ARRAY_SIZE(wm8581_dapm_widgets));
  783. snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
  784. ARRAY_SIZE(wm8581_dapm_routes));
  785. break;
  786. default:
  787. break;
  788. }
  789. ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
  790. wm8580->supplies);
  791. if (ret != 0) {
  792. dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
  793. goto err_regulator_get;
  794. }
  795. /* Get the codec into a known state */
  796. ret = snd_soc_component_write(component, WM8580_RESET, 0);
  797. if (ret != 0) {
  798. dev_err(component->dev, "Failed to reset component: %d\n", ret);
  799. goto err_regulator_enable;
  800. }
  801. return 0;
  802. err_regulator_enable:
  803. regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
  804. err_regulator_get:
  805. return ret;
  806. }
  807. /* power down chip */
  808. static void wm8580_remove(struct snd_soc_component *component)
  809. {
  810. struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
  811. regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
  812. }
  813. static const struct snd_soc_component_driver soc_component_dev_wm8580 = {
  814. .probe = wm8580_probe,
  815. .remove = wm8580_remove,
  816. .set_bias_level = wm8580_set_bias_level,
  817. .controls = wm8580_snd_controls,
  818. .num_controls = ARRAY_SIZE(wm8580_snd_controls),
  819. .dapm_widgets = wm8580_dapm_widgets,
  820. .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
  821. .dapm_routes = wm8580_dapm_routes,
  822. .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
  823. .idle_bias_on = 1,
  824. .use_pmdown_time = 1,
  825. .endianness = 1,
  826. };
  827. static const struct regmap_config wm8580_regmap = {
  828. .reg_bits = 7,
  829. .val_bits = 9,
  830. .max_register = WM8580_MAX_REGISTER,
  831. .reg_defaults = wm8580_reg_defaults,
  832. .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
  833. .cache_type = REGCACHE_RBTREE,
  834. .volatile_reg = wm8580_volatile,
  835. };
  836. static const struct wm8580_driver_data wm8580_data = {
  837. .num_dacs = 3,
  838. };
  839. static const struct wm8580_driver_data wm8581_data = {
  840. .num_dacs = 4,
  841. };
  842. static const struct of_device_id wm8580_of_match[] = {
  843. { .compatible = "wlf,wm8580", .data = &wm8580_data },
  844. { .compatible = "wlf,wm8581", .data = &wm8581_data },
  845. { },
  846. };
  847. MODULE_DEVICE_TABLE(of, wm8580_of_match);
  848. static int wm8580_i2c_probe(struct i2c_client *i2c)
  849. {
  850. const struct of_device_id *of_id;
  851. struct wm8580_priv *wm8580;
  852. int ret, i;
  853. wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
  854. GFP_KERNEL);
  855. if (wm8580 == NULL)
  856. return -ENOMEM;
  857. wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
  858. if (IS_ERR(wm8580->regmap))
  859. return PTR_ERR(wm8580->regmap);
  860. for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
  861. wm8580->supplies[i].supply = wm8580_supply_names[i];
  862. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
  863. wm8580->supplies);
  864. if (ret != 0) {
  865. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  866. return ret;
  867. }
  868. i2c_set_clientdata(i2c, wm8580);
  869. of_id = of_match_device(wm8580_of_match, &i2c->dev);
  870. if (of_id)
  871. wm8580->drvdata = of_id->data;
  872. if (!wm8580->drvdata) {
  873. dev_err(&i2c->dev, "failed to find driver data\n");
  874. return -EINVAL;
  875. }
  876. ret = devm_snd_soc_register_component(&i2c->dev,
  877. &soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
  878. return ret;
  879. }
  880. static const struct i2c_device_id wm8580_i2c_id[] = {
  881. { "wm8580", (kernel_ulong_t)&wm8580_data },
  882. { "wm8581", (kernel_ulong_t)&wm8581_data },
  883. { }
  884. };
  885. MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
  886. static struct i2c_driver wm8580_i2c_driver = {
  887. .driver = {
  888. .name = "wm8580",
  889. .of_match_table = wm8580_of_match,
  890. },
  891. .probe_new = wm8580_i2c_probe,
  892. .id_table = wm8580_i2c_id,
  893. };
  894. module_i2c_driver(wm8580_i2c_driver);
  895. MODULE_DESCRIPTION("ASoC WM8580 driver");
  896. MODULE_AUTHOR("Mark Brown <[email protected]>");
  897. MODULE_AUTHOR("Matt Flax <[email protected]>");
  898. MODULE_LICENSE("GPL");