wm8350.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8350.c -- WM8350 ALSA SoC audio driver
  4. *
  5. * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Liam Girdwood <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mfd/wm8350/audio.h>
  17. #include <linux/mfd/wm8350/core.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <trace/events/asoc.h>
  26. #include "wm8350.h"
  27. #define WM8350_OUTn_0dB 0x39
  28. #define WM8350_RAMP_NONE 0
  29. #define WM8350_RAMP_UP 1
  30. #define WM8350_RAMP_DOWN 2
  31. /* We only include the analogue supplies here; the digital supplies
  32. * need to be available well before this driver can be probed.
  33. */
  34. static const char *supply_names[] = {
  35. "AVDD",
  36. "HPVDD",
  37. };
  38. struct wm8350_output {
  39. u16 active;
  40. u16 left_vol;
  41. u16 right_vol;
  42. u16 ramp;
  43. u16 mute;
  44. };
  45. struct wm8350_jack_data {
  46. struct snd_soc_jack *jack;
  47. struct delayed_work work;
  48. int report;
  49. int short_report;
  50. };
  51. struct wm8350_data {
  52. struct wm8350 *wm8350;
  53. struct wm8350_output out1;
  54. struct wm8350_output out2;
  55. struct wm8350_jack_data hpl;
  56. struct wm8350_jack_data hpr;
  57. struct wm8350_jack_data mic;
  58. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  59. int fll_freq_out;
  60. int fll_freq_in;
  61. struct delayed_work pga_work;
  62. };
  63. /*
  64. * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  65. */
  66. static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
  67. {
  68. struct wm8350_output *out1 = &wm8350_data->out1;
  69. struct wm8350 *wm8350 = wm8350_data->wm8350;
  70. int left_complete = 0, right_complete = 0;
  71. u16 reg, val;
  72. /* left channel */
  73. reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  74. val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  75. if (out1->ramp == WM8350_RAMP_UP) {
  76. /* ramp step up */
  77. if (val < out1->left_vol) {
  78. val++;
  79. reg &= ~WM8350_OUT1L_VOL_MASK;
  80. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  81. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  82. } else
  83. left_complete = 1;
  84. } else if (out1->ramp == WM8350_RAMP_DOWN) {
  85. /* ramp step down */
  86. if (val > 0) {
  87. val--;
  88. reg &= ~WM8350_OUT1L_VOL_MASK;
  89. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  90. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  91. } else
  92. left_complete = 1;
  93. } else
  94. return 1;
  95. /* right channel */
  96. reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
  97. val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  98. if (out1->ramp == WM8350_RAMP_UP) {
  99. /* ramp step up */
  100. if (val < out1->right_vol) {
  101. val++;
  102. reg &= ~WM8350_OUT1R_VOL_MASK;
  103. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
  104. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  105. } else
  106. right_complete = 1;
  107. } else if (out1->ramp == WM8350_RAMP_DOWN) {
  108. /* ramp step down */
  109. if (val > 0) {
  110. val--;
  111. reg &= ~WM8350_OUT1R_VOL_MASK;
  112. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
  113. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  114. } else
  115. right_complete = 1;
  116. }
  117. /* only hit the update bit if either volume has changed this step */
  118. if (!left_complete || !right_complete)
  119. wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
  120. return left_complete & right_complete;
  121. }
  122. /*
  123. * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
  124. */
  125. static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
  126. {
  127. struct wm8350_output *out2 = &wm8350_data->out2;
  128. struct wm8350 *wm8350 = wm8350_data->wm8350;
  129. int left_complete = 0, right_complete = 0;
  130. u16 reg, val;
  131. /* left channel */
  132. reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
  133. val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  134. if (out2->ramp == WM8350_RAMP_UP) {
  135. /* ramp step up */
  136. if (val < out2->left_vol) {
  137. val++;
  138. reg &= ~WM8350_OUT2L_VOL_MASK;
  139. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
  140. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  141. } else
  142. left_complete = 1;
  143. } else if (out2->ramp == WM8350_RAMP_DOWN) {
  144. /* ramp step down */
  145. if (val > 0) {
  146. val--;
  147. reg &= ~WM8350_OUT2L_VOL_MASK;
  148. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
  149. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  150. } else
  151. left_complete = 1;
  152. } else
  153. return 1;
  154. /* right channel */
  155. reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
  156. val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  157. if (out2->ramp == WM8350_RAMP_UP) {
  158. /* ramp step up */
  159. if (val < out2->right_vol) {
  160. val++;
  161. reg &= ~WM8350_OUT2R_VOL_MASK;
  162. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
  163. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  164. } else
  165. right_complete = 1;
  166. } else if (out2->ramp == WM8350_RAMP_DOWN) {
  167. /* ramp step down */
  168. if (val > 0) {
  169. val--;
  170. reg &= ~WM8350_OUT2R_VOL_MASK;
  171. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
  172. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  173. } else
  174. right_complete = 1;
  175. }
  176. /* only hit the update bit if either volume has changed this step */
  177. if (!left_complete || !right_complete)
  178. wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
  179. return left_complete & right_complete;
  180. }
  181. /*
  182. * This work ramps both output PGAs at stream start/stop time to
  183. * minimise pop associated with DAPM power switching.
  184. * It's best to enable Zero Cross when ramping occurs to minimise any
  185. * zipper noises.
  186. */
  187. static void wm8350_pga_work(struct work_struct *work)
  188. {
  189. struct wm8350_data *wm8350_data =
  190. container_of(work, struct wm8350_data, pga_work.work);
  191. struct wm8350_output *out1 = &wm8350_data->out1,
  192. *out2 = &wm8350_data->out2;
  193. int i, out1_complete, out2_complete;
  194. /* do we need to ramp at all ? */
  195. if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
  196. return;
  197. /* PGA volumes have 6 bits of resolution to ramp */
  198. for (i = 0; i <= 63; i++) {
  199. out1_complete = 1;
  200. out2_complete = 1;
  201. if (out1->ramp != WM8350_RAMP_NONE)
  202. out1_complete = wm8350_out1_ramp_step(wm8350_data);
  203. if (out2->ramp != WM8350_RAMP_NONE)
  204. out2_complete = wm8350_out2_ramp_step(wm8350_data);
  205. /* ramp finished ? */
  206. if (out1_complete && out2_complete)
  207. break;
  208. /* we need to delay longer on the up ramp */
  209. if (out1->ramp == WM8350_RAMP_UP ||
  210. out2->ramp == WM8350_RAMP_UP) {
  211. /* delay is longer over 0dB as increases are larger */
  212. if (i >= WM8350_OUTn_0dB)
  213. schedule_timeout_interruptible(msecs_to_jiffies
  214. (2));
  215. else
  216. schedule_timeout_interruptible(msecs_to_jiffies
  217. (1));
  218. } else
  219. udelay(50); /* doesn't matter if we delay longer */
  220. }
  221. out1->ramp = WM8350_RAMP_NONE;
  222. out2->ramp = WM8350_RAMP_NONE;
  223. }
  224. /*
  225. * WM8350 Controls
  226. */
  227. static int pga_event(struct snd_soc_dapm_widget *w,
  228. struct snd_kcontrol *kcontrol, int event)
  229. {
  230. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  231. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  232. struct wm8350_output *out;
  233. switch (w->shift) {
  234. case 0:
  235. case 1:
  236. out = &wm8350_data->out1;
  237. break;
  238. case 2:
  239. case 3:
  240. out = &wm8350_data->out2;
  241. break;
  242. default:
  243. WARN(1, "Invalid shift %d\n", w->shift);
  244. return -1;
  245. }
  246. switch (event) {
  247. case SND_SOC_DAPM_POST_PMU:
  248. out->ramp = WM8350_RAMP_UP;
  249. out->active = 1;
  250. schedule_delayed_work(&wm8350_data->pga_work,
  251. msecs_to_jiffies(1));
  252. break;
  253. case SND_SOC_DAPM_PRE_PMD:
  254. out->ramp = WM8350_RAMP_DOWN;
  255. out->active = 0;
  256. schedule_delayed_work(&wm8350_data->pga_work,
  257. msecs_to_jiffies(1));
  258. break;
  259. }
  260. return 0;
  261. }
  262. static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
  263. struct snd_ctl_elem_value *ucontrol)
  264. {
  265. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  266. struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
  267. struct wm8350_output *out = NULL;
  268. struct soc_mixer_control *mc =
  269. (struct soc_mixer_control *)kcontrol->private_value;
  270. int ret;
  271. unsigned int reg = mc->reg;
  272. u16 val;
  273. /* For OUT1 and OUT2 we shadow the values and only actually write
  274. * them out when active in order to ensure the amplifier comes on
  275. * as quietly as possible. */
  276. switch (reg) {
  277. case WM8350_LOUT1_VOLUME:
  278. out = &wm8350_priv->out1;
  279. break;
  280. case WM8350_LOUT2_VOLUME:
  281. out = &wm8350_priv->out2;
  282. break;
  283. default:
  284. break;
  285. }
  286. if (out) {
  287. out->left_vol = ucontrol->value.integer.value[0];
  288. out->right_vol = ucontrol->value.integer.value[1];
  289. if (!out->active)
  290. return 1;
  291. }
  292. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  293. if (ret < 0)
  294. return ret;
  295. /* now hit the volume update bits (always bit 8) */
  296. val = snd_soc_component_read(component, reg);
  297. snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);
  298. return 1;
  299. }
  300. static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
  301. struct snd_ctl_elem_value *ucontrol)
  302. {
  303. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  304. struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
  305. struct wm8350_output *out1 = &wm8350_priv->out1;
  306. struct wm8350_output *out2 = &wm8350_priv->out2;
  307. struct soc_mixer_control *mc =
  308. (struct soc_mixer_control *)kcontrol->private_value;
  309. unsigned int reg = mc->reg;
  310. /* If these are cached registers use the cache */
  311. switch (reg) {
  312. case WM8350_LOUT1_VOLUME:
  313. ucontrol->value.integer.value[0] = out1->left_vol;
  314. ucontrol->value.integer.value[1] = out1->right_vol;
  315. return 0;
  316. case WM8350_LOUT2_VOLUME:
  317. ucontrol->value.integer.value[0] = out2->left_vol;
  318. ucontrol->value.integer.value[1] = out2->right_vol;
  319. return 0;
  320. default:
  321. break;
  322. }
  323. return snd_soc_get_volsw(kcontrol, ucontrol);
  324. }
  325. static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
  326. static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
  327. static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
  328. static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
  329. static const char *wm8350_adcfilter[] = { "None", "High Pass" };
  330. static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
  331. static const char *wm8350_lr[] = { "Left", "Right" };
  332. static const struct soc_enum wm8350_enum[] = {
  333. SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
  334. SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
  335. SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
  336. SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
  337. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
  338. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
  339. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
  340. SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
  341. };
  342. static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
  343. static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
  344. static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
  345. static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
  346. static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
  347. static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
  348. 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
  349. 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
  350. );
  351. static const struct snd_kcontrol_new wm8350_snd_controls[] = {
  352. SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
  353. SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
  354. SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
  355. WM8350_DAC_DIGITAL_VOLUME_L,
  356. WM8350_DAC_DIGITAL_VOLUME_R,
  357. 0, 255, 0, wm8350_get_volsw_2r,
  358. wm8350_put_volsw_2r_vu, dac_pcm_tlv),
  359. SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
  360. SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
  361. SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
  362. SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
  363. SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
  364. SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
  365. WM8350_ADC_DIGITAL_VOLUME_L,
  366. WM8350_ADC_DIGITAL_VOLUME_R,
  367. 0, 255, 0, wm8350_get_volsw_2r,
  368. wm8350_put_volsw_2r_vu, adc_pcm_tlv),
  369. SOC_DOUBLE_TLV("Capture Sidetone Volume",
  370. WM8350_ADC_DIVIDER,
  371. 8, 4, 15, 1, capture_sd_tlv),
  372. SOC_DOUBLE_R_EXT_TLV("Capture Volume",
  373. WM8350_LEFT_INPUT_VOLUME,
  374. WM8350_RIGHT_INPUT_VOLUME,
  375. 2, 63, 0, wm8350_get_volsw_2r,
  376. wm8350_put_volsw_2r_vu, pre_amp_tlv),
  377. SOC_DOUBLE_R("Capture ZC Switch",
  378. WM8350_LEFT_INPUT_VOLUME,
  379. WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
  380. SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
  381. WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
  382. SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
  383. WM8350_OUTPUT_LEFT_MIXER_VOLUME,
  384. 5, 7, 0, out_mix_tlv),
  385. SOC_SINGLE_TLV("Left Input Bypass Volume",
  386. WM8350_OUTPUT_LEFT_MIXER_VOLUME,
  387. 9, 7, 0, out_mix_tlv),
  388. SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
  389. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  390. 1, 7, 0, out_mix_tlv),
  391. SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
  392. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  393. 5, 7, 0, out_mix_tlv),
  394. SOC_SINGLE_TLV("Right Input Bypass Volume",
  395. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  396. 13, 7, 0, out_mix_tlv),
  397. SOC_SINGLE("Left Input Mixer +20dB Switch",
  398. WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
  399. SOC_SINGLE("Right Input Mixer +20dB Switch",
  400. WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
  401. SOC_SINGLE_TLV("Out4 Capture Volume",
  402. WM8350_INPUT_MIXER_VOLUME,
  403. 1, 7, 0, out_mix_tlv),
  404. SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
  405. WM8350_LOUT1_VOLUME,
  406. WM8350_ROUT1_VOLUME,
  407. 2, 63, 0, wm8350_get_volsw_2r,
  408. wm8350_put_volsw_2r_vu, out_pga_tlv),
  409. SOC_DOUBLE_R("Out1 Playback ZC Switch",
  410. WM8350_LOUT1_VOLUME,
  411. WM8350_ROUT1_VOLUME, 13, 1, 0),
  412. SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
  413. WM8350_LOUT2_VOLUME,
  414. WM8350_ROUT2_VOLUME,
  415. 2, 63, 0, wm8350_get_volsw_2r,
  416. wm8350_put_volsw_2r_vu, out_pga_tlv),
  417. SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
  418. WM8350_ROUT2_VOLUME, 13, 1, 0),
  419. SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
  420. SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
  421. 5, 7, 0, out_mix_tlv),
  422. SOC_DOUBLE_R("Out1 Playback Switch",
  423. WM8350_LOUT1_VOLUME,
  424. WM8350_ROUT1_VOLUME,
  425. 14, 1, 1),
  426. SOC_DOUBLE_R("Out2 Playback Switch",
  427. WM8350_LOUT2_VOLUME,
  428. WM8350_ROUT2_VOLUME,
  429. 14, 1, 1),
  430. };
  431. /*
  432. * DAPM Controls
  433. */
  434. /* Left Playback Mixer */
  435. static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
  436. SOC_DAPM_SINGLE("Playback Switch",
  437. WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
  438. SOC_DAPM_SINGLE("Left Bypass Switch",
  439. WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
  440. SOC_DAPM_SINGLE("Right Playback Switch",
  441. WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
  442. SOC_DAPM_SINGLE("Left Sidetone Switch",
  443. WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
  444. SOC_DAPM_SINGLE("Right Sidetone Switch",
  445. WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
  446. };
  447. /* Right Playback Mixer */
  448. static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
  449. SOC_DAPM_SINGLE("Playback Switch",
  450. WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
  451. SOC_DAPM_SINGLE("Right Bypass Switch",
  452. WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
  453. SOC_DAPM_SINGLE("Left Playback Switch",
  454. WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
  455. SOC_DAPM_SINGLE("Left Sidetone Switch",
  456. WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
  457. SOC_DAPM_SINGLE("Right Sidetone Switch",
  458. WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
  459. };
  460. /* Out4 Mixer */
  461. static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
  462. SOC_DAPM_SINGLE("Right Playback Switch",
  463. WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
  464. SOC_DAPM_SINGLE("Left Playback Switch",
  465. WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
  466. SOC_DAPM_SINGLE("Right Capture Switch",
  467. WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
  468. SOC_DAPM_SINGLE("Out3 Playback Switch",
  469. WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
  470. SOC_DAPM_SINGLE("Right Mixer Switch",
  471. WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
  472. SOC_DAPM_SINGLE("Left Mixer Switch",
  473. WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
  474. };
  475. /* Out3 Mixer */
  476. static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
  477. SOC_DAPM_SINGLE("Left Playback Switch",
  478. WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
  479. SOC_DAPM_SINGLE("Left Capture Switch",
  480. WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
  481. SOC_DAPM_SINGLE("Out4 Playback Switch",
  482. WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
  483. SOC_DAPM_SINGLE("Left Mixer Switch",
  484. WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
  485. };
  486. /* Left Input Mixer */
  487. static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
  488. SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
  489. WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
  490. SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
  491. WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
  492. SOC_DAPM_SINGLE("PGA Capture Switch",
  493. WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
  494. };
  495. /* Right Input Mixer */
  496. static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
  497. SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
  498. WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
  499. SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
  500. WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
  501. SOC_DAPM_SINGLE("PGA Capture Switch",
  502. WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
  503. };
  504. /* Left Mic Mixer */
  505. static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
  506. SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
  507. SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
  508. SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
  509. };
  510. /* Right Mic Mixer */
  511. static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
  512. SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
  513. SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
  514. SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
  515. };
  516. /* Beep Switch */
  517. static const struct snd_kcontrol_new wm8350_beep_switch_controls =
  518. SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
  519. /* Out4 Capture Mux */
  520. static const struct snd_kcontrol_new wm8350_out4_capture_controls =
  521. SOC_DAPM_ENUM("Route", wm8350_enum[7]);
  522. static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
  523. SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
  524. SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
  525. SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
  526. 0, pga_event,
  527. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  528. SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
  529. pga_event,
  530. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  531. SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
  532. 0, pga_event,
  533. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  534. SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
  535. pga_event,
  536. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  537. SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
  538. 7, 0, &wm8350_right_capt_mixer_controls[0],
  539. ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
  540. SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
  541. 6, 0, &wm8350_left_capt_mixer_controls[0],
  542. ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
  543. SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
  544. &wm8350_out4_mixer_controls[0],
  545. ARRAY_SIZE(wm8350_out4_mixer_controls)),
  546. SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
  547. &wm8350_out3_mixer_controls[0],
  548. ARRAY_SIZE(wm8350_out3_mixer_controls)),
  549. SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
  550. &wm8350_right_play_mixer_controls[0],
  551. ARRAY_SIZE(wm8350_right_play_mixer_controls)),
  552. SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
  553. &wm8350_left_play_mixer_controls[0],
  554. ARRAY_SIZE(wm8350_left_play_mixer_controls)),
  555. SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
  556. &wm8350_left_mic_mixer_controls[0],
  557. ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
  558. SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
  559. &wm8350_right_mic_mixer_controls[0],
  560. ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
  561. /* virtual mixer for Beep and Out2R */
  562. SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  563. SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
  564. &wm8350_beep_switch_controls),
  565. SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
  566. WM8350_POWER_MGMT_4, 3, 0),
  567. SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
  568. WM8350_POWER_MGMT_4, 2, 0),
  569. SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
  570. WM8350_POWER_MGMT_4, 5, 0),
  571. SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
  572. WM8350_POWER_MGMT_4, 4, 0),
  573. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
  574. SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
  575. &wm8350_out4_capture_controls),
  576. SND_SOC_DAPM_OUTPUT("OUT1R"),
  577. SND_SOC_DAPM_OUTPUT("OUT1L"),
  578. SND_SOC_DAPM_OUTPUT("OUT2R"),
  579. SND_SOC_DAPM_OUTPUT("OUT2L"),
  580. SND_SOC_DAPM_OUTPUT("OUT3"),
  581. SND_SOC_DAPM_OUTPUT("OUT4"),
  582. SND_SOC_DAPM_INPUT("IN1RN"),
  583. SND_SOC_DAPM_INPUT("IN1RP"),
  584. SND_SOC_DAPM_INPUT("IN2R"),
  585. SND_SOC_DAPM_INPUT("IN1LP"),
  586. SND_SOC_DAPM_INPUT("IN1LN"),
  587. SND_SOC_DAPM_INPUT("IN2L"),
  588. SND_SOC_DAPM_INPUT("IN3R"),
  589. SND_SOC_DAPM_INPUT("IN3L"),
  590. };
  591. static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
  592. /* left playback mixer */
  593. {"Left Playback Mixer", "Playback Switch", "Left DAC"},
  594. {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
  595. {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
  596. {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
  597. {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
  598. /* right playback mixer */
  599. {"Right Playback Mixer", "Playback Switch", "Right DAC"},
  600. {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
  601. {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
  602. {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
  603. {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
  604. /* out4 playback mixer */
  605. {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
  606. {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
  607. {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
  608. {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
  609. {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
  610. {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
  611. {"OUT4", NULL, "Out4 Mixer"},
  612. /* out3 playback mixer */
  613. {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
  614. {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
  615. {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
  616. {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
  617. {"OUT3", NULL, "Out3 Mixer"},
  618. /* out2 */
  619. {"Right Out2 PGA", NULL, "Right Playback Mixer"},
  620. {"Left Out2 PGA", NULL, "Left Playback Mixer"},
  621. {"OUT2L", NULL, "Left Out2 PGA"},
  622. {"OUT2R", NULL, "Right Out2 PGA"},
  623. /* out1 */
  624. {"Right Out1 PGA", NULL, "Right Playback Mixer"},
  625. {"Left Out1 PGA", NULL, "Left Playback Mixer"},
  626. {"OUT1L", NULL, "Left Out1 PGA"},
  627. {"OUT1R", NULL, "Right Out1 PGA"},
  628. /* ADCs */
  629. {"Left ADC", NULL, "Left Capture Mixer"},
  630. {"Right ADC", NULL, "Right Capture Mixer"},
  631. /* Left capture mixer */
  632. {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
  633. {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
  634. {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
  635. {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
  636. /* Right capture mixer */
  637. {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
  638. {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
  639. {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
  640. {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
  641. /* L3 Inputs */
  642. {"IN3L PGA", NULL, "IN3L"},
  643. {"IN3R PGA", NULL, "IN3R"},
  644. /* Left Mic mixer */
  645. {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
  646. {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
  647. {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
  648. /* Right Mic mixer */
  649. {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
  650. {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
  651. {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
  652. /* out 4 capture */
  653. {"Out4 Capture Channel", NULL, "Out4 Mixer"},
  654. /* Beep */
  655. {"Beep", NULL, "IN3R PGA"},
  656. };
  657. static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  658. int clk_id, unsigned int freq, int dir)
  659. {
  660. struct snd_soc_component *component = codec_dai->component;
  661. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  662. struct wm8350 *wm8350 = wm8350_data->wm8350;
  663. u16 fll_4;
  664. switch (clk_id) {
  665. case WM8350_MCLK_SEL_MCLK:
  666. wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
  667. WM8350_MCLK_SEL);
  668. break;
  669. case WM8350_MCLK_SEL_PLL_MCLK:
  670. case WM8350_MCLK_SEL_PLL_DAC:
  671. case WM8350_MCLK_SEL_PLL_ADC:
  672. case WM8350_MCLK_SEL_PLL_32K:
  673. wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
  674. WM8350_MCLK_SEL);
  675. fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
  676. ~WM8350_FLL_CLK_SRC_MASK;
  677. snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
  678. break;
  679. }
  680. /* MCLK direction */
  681. if (dir == SND_SOC_CLOCK_OUT)
  682. wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
  683. WM8350_MCLK_DIR);
  684. else
  685. wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
  686. WM8350_MCLK_DIR);
  687. return 0;
  688. }
  689. static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
  690. {
  691. struct snd_soc_component *component = codec_dai->component;
  692. u16 val;
  693. switch (div_id) {
  694. case WM8350_ADC_CLKDIV:
  695. val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &
  696. ~WM8350_ADC_CLKDIV_MASK;
  697. snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);
  698. break;
  699. case WM8350_DAC_CLKDIV:
  700. val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &
  701. ~WM8350_DAC_CLKDIV_MASK;
  702. snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);
  703. break;
  704. case WM8350_BCLK_CLKDIV:
  705. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  706. ~WM8350_BCLK_DIV_MASK;
  707. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  708. break;
  709. case WM8350_OPCLK_CLKDIV:
  710. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  711. ~WM8350_OPCLK_DIV_MASK;
  712. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  713. break;
  714. case WM8350_SYS_CLKDIV:
  715. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  716. ~WM8350_MCLK_DIV_MASK;
  717. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  718. break;
  719. case WM8350_DACLR_CLKDIV:
  720. val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
  721. ~WM8350_DACLRC_RATE_MASK;
  722. snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);
  723. break;
  724. case WM8350_ADCLR_CLKDIV:
  725. val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
  726. ~WM8350_ADCLRC_RATE_MASK;
  727. snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);
  728. break;
  729. default:
  730. return -EINVAL;
  731. }
  732. return 0;
  733. }
  734. static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  735. {
  736. struct snd_soc_component *component = codec_dai->component;
  737. u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
  738. ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
  739. u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &
  740. ~WM8350_BCLK_MSTR;
  741. u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
  742. ~WM8350_DACLRC_ENA;
  743. u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
  744. ~WM8350_ADCLRC_ENA;
  745. /* set master/slave audio interface */
  746. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  747. case SND_SOC_DAIFMT_CBM_CFM:
  748. master |= WM8350_BCLK_MSTR;
  749. dac_lrc |= WM8350_DACLRC_ENA;
  750. adc_lrc |= WM8350_ADCLRC_ENA;
  751. break;
  752. case SND_SOC_DAIFMT_CBS_CFS:
  753. break;
  754. default:
  755. return -EINVAL;
  756. }
  757. /* interface format */
  758. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  759. case SND_SOC_DAIFMT_I2S:
  760. iface |= 0x2 << 8;
  761. break;
  762. case SND_SOC_DAIFMT_RIGHT_J:
  763. break;
  764. case SND_SOC_DAIFMT_LEFT_J:
  765. iface |= 0x1 << 8;
  766. break;
  767. case SND_SOC_DAIFMT_DSP_A:
  768. iface |= 0x3 << 8;
  769. break;
  770. case SND_SOC_DAIFMT_DSP_B:
  771. iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
  772. break;
  773. default:
  774. return -EINVAL;
  775. }
  776. /* clock inversion */
  777. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  778. case SND_SOC_DAIFMT_NB_NF:
  779. break;
  780. case SND_SOC_DAIFMT_IB_IF:
  781. iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
  782. break;
  783. case SND_SOC_DAIFMT_IB_NF:
  784. iface |= WM8350_AIF_BCLK_INV;
  785. break;
  786. case SND_SOC_DAIFMT_NB_IF:
  787. iface |= WM8350_AIF_LRCLK_INV;
  788. break;
  789. default:
  790. return -EINVAL;
  791. }
  792. snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
  793. snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);
  794. snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);
  795. snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);
  796. return 0;
  797. }
  798. static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
  799. struct snd_pcm_hw_params *params,
  800. struct snd_soc_dai *codec_dai)
  801. {
  802. struct snd_soc_component *component = codec_dai->component;
  803. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  804. struct wm8350 *wm8350 = wm8350_data->wm8350;
  805. u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
  806. ~WM8350_AIF_WL_MASK;
  807. /* bit size */
  808. switch (params_width(params)) {
  809. case 16:
  810. break;
  811. case 20:
  812. iface |= 0x1 << 10;
  813. break;
  814. case 24:
  815. iface |= 0x2 << 10;
  816. break;
  817. case 32:
  818. iface |= 0x3 << 10;
  819. break;
  820. }
  821. snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
  822. /* The sloping stopband filter is recommended for use with
  823. * lower sample rates to improve performance.
  824. */
  825. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  826. if (params_rate(params) < 24000)
  827. wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
  828. WM8350_DAC_SB_FILT);
  829. else
  830. wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
  831. WM8350_DAC_SB_FILT);
  832. }
  833. return 0;
  834. }
  835. static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)
  836. {
  837. struct snd_soc_component *component = dai->component;
  838. unsigned int val;
  839. if (mute)
  840. val = WM8350_DAC_MUTE_ENA;
  841. else
  842. val = 0;
  843. snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
  844. return 0;
  845. }
  846. /* FLL divisors */
  847. struct _fll_div {
  848. int div; /* FLL_OUTDIV */
  849. int n;
  850. int k;
  851. int ratio; /* FLL_FRATIO */
  852. };
  853. /* The size in bits of the fll divide multiplied by 10
  854. * to allow rounding later */
  855. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  856. static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
  857. unsigned int output)
  858. {
  859. u64 Kpart;
  860. unsigned int t1, t2, K, Nmod;
  861. if (output >= 2815250 && output <= 3125000)
  862. fll_div->div = 0x4;
  863. else if (output >= 5625000 && output <= 6250000)
  864. fll_div->div = 0x3;
  865. else if (output >= 11250000 && output <= 12500000)
  866. fll_div->div = 0x2;
  867. else if (output >= 22500000 && output <= 25000000)
  868. fll_div->div = 0x1;
  869. else {
  870. printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
  871. return -EINVAL;
  872. }
  873. if (input > 48000)
  874. fll_div->ratio = 1;
  875. else
  876. fll_div->ratio = 8;
  877. t1 = output * (1 << (fll_div->div + 1));
  878. t2 = input * fll_div->ratio;
  879. fll_div->n = t1 / t2;
  880. Nmod = t1 % t2;
  881. if (Nmod) {
  882. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  883. do_div(Kpart, t2);
  884. K = Kpart & 0xFFFFFFFF;
  885. /* Check if we need to round */
  886. if ((K % 10) >= 5)
  887. K += 5;
  888. /* Move down to proper range now rounding is done */
  889. K /= 10;
  890. fll_div->k = K;
  891. } else
  892. fll_div->k = 0;
  893. return 0;
  894. }
  895. static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
  896. int pll_id, int source, unsigned int freq_in,
  897. unsigned int freq_out)
  898. {
  899. struct snd_soc_component *component = codec_dai->component;
  900. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  901. struct wm8350 *wm8350 = priv->wm8350;
  902. struct _fll_div fll_div;
  903. int ret = 0;
  904. u16 fll_1, fll_4;
  905. if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
  906. return 0;
  907. /* power down FLL - we need to do this for reconfiguration */
  908. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
  909. WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
  910. if (freq_out == 0 || freq_in == 0)
  911. return ret;
  912. ret = fll_factors(&fll_div, freq_in, freq_out);
  913. if (ret < 0)
  914. return ret;
  915. dev_dbg(wm8350->dev,
  916. "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
  917. freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
  918. fll_div.ratio);
  919. /* set up N.K & dividers */
  920. fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &
  921. ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
  922. snd_soc_component_write(component, WM8350_FLL_CONTROL_1,
  923. fll_1 | (fll_div.div << 8) | 0x50);
  924. snd_soc_component_write(component, WM8350_FLL_CONTROL_2,
  925. (fll_div.ratio << 11) | (fll_div.
  926. n & WM8350_FLL_N_MASK));
  927. snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
  928. fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
  929. ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
  930. snd_soc_component_write(component, WM8350_FLL_CONTROL_4,
  931. fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
  932. (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
  933. /* power FLL on */
  934. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
  935. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
  936. priv->fll_freq_out = freq_out;
  937. priv->fll_freq_in = freq_in;
  938. return 0;
  939. }
  940. static int wm8350_set_bias_level(struct snd_soc_component *component,
  941. enum snd_soc_bias_level level)
  942. {
  943. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  944. struct wm8350 *wm8350 = priv->wm8350;
  945. struct wm8350_audio_platform_data *platform =
  946. wm8350->codec.platform_data;
  947. u16 pm1;
  948. int ret;
  949. switch (level) {
  950. case SND_SOC_BIAS_ON:
  951. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  952. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  953. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  954. pm1 | WM8350_VMID_50K |
  955. platform->codec_current_on << 14);
  956. break;
  957. case SND_SOC_BIAS_PREPARE:
  958. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
  959. pm1 &= ~WM8350_VMID_MASK;
  960. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  961. pm1 | WM8350_VMID_50K);
  962. break;
  963. case SND_SOC_BIAS_STANDBY:
  964. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  965. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  966. priv->supplies);
  967. if (ret != 0)
  968. return ret;
  969. /* Enable the system clock */
  970. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
  971. WM8350_SYSCLK_ENA);
  972. /* mute DAC & outputs */
  973. wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
  974. WM8350_DAC_MUTE_ENA);
  975. /* discharge cap memory */
  976. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  977. platform->dis_out1 |
  978. (platform->dis_out2 << 2) |
  979. (platform->dis_out3 << 4) |
  980. (platform->dis_out4 << 6));
  981. /* wait for discharge */
  982. schedule_timeout_interruptible(msecs_to_jiffies
  983. (platform->
  984. cap_discharge_msecs));
  985. /* enable antipop */
  986. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  987. (platform->vmid_s_curve << 8));
  988. /* ramp up vmid */
  989. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  990. (platform->
  991. codec_current_charge << 14) |
  992. WM8350_VMID_5K | WM8350_VMIDEN |
  993. WM8350_VBUFEN);
  994. /* wait for vmid */
  995. schedule_timeout_interruptible(msecs_to_jiffies
  996. (platform->
  997. vmid_charge_msecs));
  998. /* turn on vmid 300k */
  999. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1000. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  1001. pm1 |= WM8350_VMID_300K |
  1002. (platform->codec_current_standby << 14);
  1003. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1004. pm1);
  1005. /* enable analogue bias */
  1006. pm1 |= WM8350_BIASEN;
  1007. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1008. /* disable antipop */
  1009. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
  1010. } else {
  1011. /* turn on vmid 300k and reduce current */
  1012. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1013. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  1014. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1015. pm1 | WM8350_VMID_300K |
  1016. (platform->
  1017. codec_current_standby << 14));
  1018. }
  1019. break;
  1020. case SND_SOC_BIAS_OFF:
  1021. /* mute DAC & enable outputs */
  1022. wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
  1023. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
  1024. WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
  1025. WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
  1026. /* enable anti pop S curve */
  1027. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  1028. (platform->vmid_s_curve << 8));
  1029. /* turn off vmid */
  1030. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1031. ~WM8350_VMIDEN;
  1032. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1033. /* wait */
  1034. schedule_timeout_interruptible(msecs_to_jiffies
  1035. (platform->
  1036. vmid_discharge_msecs));
  1037. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  1038. (platform->vmid_s_curve << 8) |
  1039. platform->dis_out1 |
  1040. (platform->dis_out2 << 2) |
  1041. (platform->dis_out3 << 4) |
  1042. (platform->dis_out4 << 6));
  1043. /* turn off VBuf and drain */
  1044. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1045. ~(WM8350_VBUFEN | WM8350_VMID_MASK);
  1046. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1047. pm1 | WM8350_OUTPUT_DRAIN_EN);
  1048. /* wait */
  1049. schedule_timeout_interruptible(msecs_to_jiffies
  1050. (platform->drain_msecs));
  1051. pm1 &= ~WM8350_BIASEN;
  1052. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1053. /* disable anti-pop */
  1054. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
  1055. wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
  1056. WM8350_OUT1L_ENA);
  1057. wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
  1058. WM8350_OUT1R_ENA);
  1059. wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
  1060. WM8350_OUT2L_ENA);
  1061. wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
  1062. WM8350_OUT2R_ENA);
  1063. /* disable clock gen */
  1064. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
  1065. WM8350_SYSCLK_ENA);
  1066. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  1067. priv->supplies);
  1068. break;
  1069. }
  1070. return 0;
  1071. }
  1072. static void wm8350_hp_work(struct wm8350_data *priv,
  1073. struct wm8350_jack_data *jack,
  1074. u16 mask)
  1075. {
  1076. struct wm8350 *wm8350 = priv->wm8350;
  1077. u16 reg;
  1078. int report;
  1079. reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
  1080. if (reg & mask)
  1081. report = jack->report;
  1082. else
  1083. report = 0;
  1084. snd_soc_jack_report(jack->jack, report, jack->report);
  1085. }
  1086. static void wm8350_hpl_work(struct work_struct *work)
  1087. {
  1088. struct wm8350_data *priv =
  1089. container_of(work, struct wm8350_data, hpl.work.work);
  1090. wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
  1091. }
  1092. static void wm8350_hpr_work(struct work_struct *work)
  1093. {
  1094. struct wm8350_data *priv =
  1095. container_of(work, struct wm8350_data, hpr.work.work);
  1096. wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
  1097. }
  1098. static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
  1099. {
  1100. struct wm8350_data *priv = data;
  1101. struct wm8350 *wm8350 = priv->wm8350;
  1102. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1103. trace_snd_soc_jack_irq("WM8350 HPL");
  1104. #endif
  1105. if (device_may_wakeup(wm8350->dev))
  1106. pm_wakeup_event(wm8350->dev, 250);
  1107. queue_delayed_work(system_power_efficient_wq,
  1108. &priv->hpl.work, msecs_to_jiffies(200));
  1109. return IRQ_HANDLED;
  1110. }
  1111. static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
  1112. {
  1113. struct wm8350_data *priv = data;
  1114. struct wm8350 *wm8350 = priv->wm8350;
  1115. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1116. trace_snd_soc_jack_irq("WM8350 HPR");
  1117. #endif
  1118. if (device_may_wakeup(wm8350->dev))
  1119. pm_wakeup_event(wm8350->dev, 250);
  1120. queue_delayed_work(system_power_efficient_wq,
  1121. &priv->hpr.work, msecs_to_jiffies(200));
  1122. return IRQ_HANDLED;
  1123. }
  1124. /**
  1125. * wm8350_hp_jack_detect - Enable headphone jack detection.
  1126. *
  1127. * @component: WM8350 component
  1128. * @which: left or right jack detect signal
  1129. * @jack: jack to report detection events on
  1130. * @report: value to report
  1131. *
  1132. * Enables the headphone jack detection of the WM8350. If no report
  1133. * is specified then detection is disabled.
  1134. */
  1135. int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,
  1136. struct snd_soc_jack *jack, int report)
  1137. {
  1138. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1139. struct wm8350 *wm8350 = priv->wm8350;
  1140. int ena;
  1141. switch (which) {
  1142. case WM8350_JDL:
  1143. priv->hpl.jack = jack;
  1144. priv->hpl.report = report;
  1145. ena = WM8350_JDL_ENA;
  1146. break;
  1147. case WM8350_JDR:
  1148. priv->hpr.jack = jack;
  1149. priv->hpr.report = report;
  1150. ena = WM8350_JDR_ENA;
  1151. break;
  1152. default:
  1153. return -EINVAL;
  1154. }
  1155. if (report) {
  1156. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1157. wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
  1158. } else {
  1159. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
  1160. }
  1161. /* Sync status */
  1162. switch (which) {
  1163. case WM8350_JDL:
  1164. wm8350_hpl_jack_handler(0, priv);
  1165. break;
  1166. case WM8350_JDR:
  1167. wm8350_hpr_jack_handler(0, priv);
  1168. break;
  1169. }
  1170. return 0;
  1171. }
  1172. EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
  1173. static irqreturn_t wm8350_mic_handler(int irq, void *data)
  1174. {
  1175. struct wm8350_data *priv = data;
  1176. struct wm8350 *wm8350 = priv->wm8350;
  1177. u16 reg;
  1178. int report = 0;
  1179. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1180. trace_snd_soc_jack_irq("WM8350 mic");
  1181. #endif
  1182. reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
  1183. if (reg & WM8350_JACK_MICSCD_LVL)
  1184. report |= priv->mic.short_report;
  1185. if (reg & WM8350_JACK_MICSD_LVL)
  1186. report |= priv->mic.report;
  1187. snd_soc_jack_report(priv->mic.jack, report,
  1188. priv->mic.report | priv->mic.short_report);
  1189. return IRQ_HANDLED;
  1190. }
  1191. /**
  1192. * wm8350_mic_jack_detect - Enable microphone jack detection.
  1193. *
  1194. * @component: WM8350 component
  1195. * @jack: jack to report detection events on
  1196. * @detect_report: value to report when presence detected
  1197. * @short_report: value to report when microphone short detected
  1198. *
  1199. * Enables the microphone jack detection of the WM8350. If both reports
  1200. * are specified as zero then detection is disabled.
  1201. */
  1202. int wm8350_mic_jack_detect(struct snd_soc_component *component,
  1203. struct snd_soc_jack *jack,
  1204. int detect_report, int short_report)
  1205. {
  1206. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1207. struct wm8350 *wm8350 = priv->wm8350;
  1208. priv->mic.jack = jack;
  1209. priv->mic.report = detect_report;
  1210. priv->mic.short_report = short_report;
  1211. if (detect_report || short_report) {
  1212. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1213. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
  1214. WM8350_MIC_DET_ENA);
  1215. } else {
  1216. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
  1217. WM8350_MIC_DET_ENA);
  1218. }
  1219. return 0;
  1220. }
  1221. EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
  1222. #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
  1223. #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1224. SNDRV_PCM_FMTBIT_S20_3LE |\
  1225. SNDRV_PCM_FMTBIT_S24_LE)
  1226. static const struct snd_soc_dai_ops wm8350_dai_ops = {
  1227. .hw_params = wm8350_pcm_hw_params,
  1228. .mute_stream = wm8350_mute,
  1229. .set_fmt = wm8350_set_dai_fmt,
  1230. .set_sysclk = wm8350_set_dai_sysclk,
  1231. .set_pll = wm8350_set_fll,
  1232. .set_clkdiv = wm8350_set_clkdiv,
  1233. .no_capture_mute = 1,
  1234. };
  1235. static struct snd_soc_dai_driver wm8350_dai = {
  1236. .name = "wm8350-hifi",
  1237. .playback = {
  1238. .stream_name = "Playback",
  1239. .channels_min = 1,
  1240. .channels_max = 2,
  1241. .rates = WM8350_RATES,
  1242. .formats = WM8350_FORMATS,
  1243. },
  1244. .capture = {
  1245. .stream_name = "Capture",
  1246. .channels_min = 1,
  1247. .channels_max = 2,
  1248. .rates = WM8350_RATES,
  1249. .formats = WM8350_FORMATS,
  1250. },
  1251. .ops = &wm8350_dai_ops,
  1252. };
  1253. static int wm8350_component_probe(struct snd_soc_component *component)
  1254. {
  1255. struct wm8350 *wm8350 = dev_get_platdata(component->dev);
  1256. struct wm8350_data *priv;
  1257. struct wm8350_output *out1;
  1258. struct wm8350_output *out2;
  1259. int ret, i;
  1260. if (wm8350->codec.platform_data == NULL) {
  1261. dev_err(component->dev, "No audio platform data supplied\n");
  1262. return -EINVAL;
  1263. }
  1264. priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),
  1265. GFP_KERNEL);
  1266. if (priv == NULL)
  1267. return -ENOMEM;
  1268. snd_soc_component_init_regmap(component, wm8350->regmap);
  1269. snd_soc_component_set_drvdata(component, priv);
  1270. priv->wm8350 = wm8350;
  1271. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  1272. priv->supplies[i].supply = supply_names[i];
  1273. ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
  1274. priv->supplies);
  1275. if (ret != 0)
  1276. return ret;
  1277. /* Put the codec into reset if it wasn't already */
  1278. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1279. INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
  1280. INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
  1281. INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
  1282. /* Enable the codec */
  1283. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1284. /* Enable robust clocking mode in ADC */
  1285. snd_soc_component_write(component, WM8350_SECURITY, 0xa7);
  1286. snd_soc_component_write(component, 0xde, 0x13);
  1287. snd_soc_component_write(component, WM8350_SECURITY, 0);
  1288. /* read OUT1 & OUT2 volumes */
  1289. out1 = &priv->out1;
  1290. out2 = &priv->out2;
  1291. out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
  1292. WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  1293. out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
  1294. WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  1295. out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
  1296. WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  1297. out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
  1298. WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  1299. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
  1300. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
  1301. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
  1302. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
  1303. /* Latch VU bits & mute */
  1304. wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
  1305. WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
  1306. wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
  1307. WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
  1308. wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
  1309. WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
  1310. wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
  1311. WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
  1312. /* Make sure AIF tristating is disabled by default */
  1313. wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
  1314. /* Make sure we've got a sane companding setup too */
  1315. wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
  1316. WM8350_DAC_COMP | WM8350_LOOPBACK);
  1317. /* Make sure jack detect is disabled to start off with */
  1318. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
  1319. WM8350_JDL_ENA | WM8350_JDR_ENA);
  1320. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
  1321. wm8350_hpl_jack_handler, 0, "Left jack detect",
  1322. priv);
  1323. if (ret != 0)
  1324. goto err;
  1325. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
  1326. wm8350_hpr_jack_handler, 0, "Right jack detect",
  1327. priv);
  1328. if (ret != 0)
  1329. goto free_jck_det_l;
  1330. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
  1331. wm8350_mic_handler, 0, "Microphone short", priv);
  1332. if (ret != 0)
  1333. goto free_jck_det_r;
  1334. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
  1335. wm8350_mic_handler, 0, "Microphone detect", priv);
  1336. if (ret != 0)
  1337. goto free_micscd;
  1338. return 0;
  1339. free_micscd:
  1340. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
  1341. free_jck_det_r:
  1342. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
  1343. free_jck_det_l:
  1344. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
  1345. err:
  1346. return ret;
  1347. }
  1348. static void wm8350_component_remove(struct snd_soc_component *component)
  1349. {
  1350. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1351. struct wm8350 *wm8350 = dev_get_platdata(component->dev);
  1352. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
  1353. WM8350_JDL_ENA | WM8350_JDR_ENA);
  1354. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1355. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
  1356. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
  1357. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
  1358. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
  1359. priv->hpl.jack = NULL;
  1360. priv->hpr.jack = NULL;
  1361. priv->mic.jack = NULL;
  1362. cancel_delayed_work_sync(&priv->hpl.work);
  1363. cancel_delayed_work_sync(&priv->hpr.work);
  1364. /* if there was any work waiting then we run it now and
  1365. * wait for its completion */
  1366. flush_delayed_work(&priv->pga_work);
  1367. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1368. }
  1369. static const struct snd_soc_component_driver soc_component_dev_wm8350 = {
  1370. .probe = wm8350_component_probe,
  1371. .remove = wm8350_component_remove,
  1372. .set_bias_level = wm8350_set_bias_level,
  1373. .controls = wm8350_snd_controls,
  1374. .num_controls = ARRAY_SIZE(wm8350_snd_controls),
  1375. .dapm_widgets = wm8350_dapm_widgets,
  1376. .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
  1377. .dapm_routes = wm8350_dapm_routes,
  1378. .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
  1379. .suspend_bias_off = 1,
  1380. .idle_bias_on = 1,
  1381. .use_pmdown_time = 1,
  1382. .endianness = 1,
  1383. };
  1384. static int wm8350_probe(struct platform_device *pdev)
  1385. {
  1386. return devm_snd_soc_register_component(&pdev->dev,
  1387. &soc_component_dev_wm8350,
  1388. &wm8350_dai, 1);
  1389. }
  1390. static struct platform_driver wm8350_codec_driver = {
  1391. .driver = {
  1392. .name = "wm8350-codec",
  1393. },
  1394. .probe = wm8350_probe,
  1395. };
  1396. module_platform_driver(wm8350_codec_driver);
  1397. MODULE_DESCRIPTION("ASoC WM8350 driver");
  1398. MODULE_AUTHOR("Liam Girdwood");
  1399. MODULE_LICENSE("GPL");
  1400. MODULE_ALIAS("platform:wm8350-codec");