wm5100.h 282 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * wm5100.h -- WM5100 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <[email protected]>
  8. */
  9. #ifndef WM5100_ASOC_H
  10. #define WM5100_ASOC_H
  11. #include <sound/soc.h>
  12. #include <linux/regmap.h>
  13. int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack);
  14. #define WM5100_CLK_AIF1 1
  15. #define WM5100_CLK_AIF2 2
  16. #define WM5100_CLK_AIF3 3
  17. #define WM5100_CLK_SYSCLK 4
  18. #define WM5100_CLK_ASYNCCLK 5
  19. #define WM5100_CLK_32KHZ 6
  20. #define WM5100_CLK_OPCLK 7
  21. #define WM5100_CLKSRC_MCLK1 0
  22. #define WM5100_CLKSRC_MCLK2 1
  23. #define WM5100_CLKSRC_SYSCLK 2
  24. #define WM5100_CLKSRC_FLL1 4
  25. #define WM5100_CLKSRC_FLL2 5
  26. #define WM5100_CLKSRC_AIF1BCLK 8
  27. #define WM5100_CLKSRC_AIF2BCLK 9
  28. #define WM5100_CLKSRC_AIF3BCLK 10
  29. #define WM5100_CLKSRC_ASYNCCLK 0x100
  30. #define WM5100_FLL1 1
  31. #define WM5100_FLL2 2
  32. #define WM5100_FLL_SRC_MCLK1 0x0
  33. #define WM5100_FLL_SRC_MCLK2 0x1
  34. #define WM5100_FLL_SRC_FLL1 0x4
  35. #define WM5100_FLL_SRC_FLL2 0x5
  36. #define WM5100_FLL_SRC_AIF1BCLK 0x8
  37. #define WM5100_FLL_SRC_AIF2BCLK 0x9
  38. #define WM5100_FLL_SRC_AIF3BCLK 0xa
  39. /*
  40. * Register values.
  41. */
  42. #define WM5100_SOFTWARE_RESET 0x00
  43. #define WM5100_DEVICE_REVISION 0x01
  44. #define WM5100_CTRL_IF_1 0x10
  45. #define WM5100_TONE_GENERATOR_1 0x20
  46. #define WM5100_PWM_DRIVE_1 0x30
  47. #define WM5100_PWM_DRIVE_2 0x31
  48. #define WM5100_PWM_DRIVE_3 0x32
  49. #define WM5100_CLOCKING_1 0x100
  50. #define WM5100_CLOCKING_3 0x101
  51. #define WM5100_CLOCKING_4 0x102
  52. #define WM5100_CLOCKING_5 0x103
  53. #define WM5100_CLOCKING_6 0x104
  54. #define WM5100_CLOCKING_7 0x107
  55. #define WM5100_CLOCKING_8 0x108
  56. #define WM5100_ASRC_ENABLE 0x120
  57. #define WM5100_ASRC_STATUS 0x121
  58. #define WM5100_ASRC_RATE1 0x122
  59. #define WM5100_ISRC_1_CTRL_1 0x141
  60. #define WM5100_ISRC_1_CTRL_2 0x142
  61. #define WM5100_ISRC_2_CTRL1 0x143
  62. #define WM5100_ISRC_2_CTRL_2 0x144
  63. #define WM5100_FLL1_CONTROL_1 0x182
  64. #define WM5100_FLL1_CONTROL_2 0x183
  65. #define WM5100_FLL1_CONTROL_3 0x184
  66. #define WM5100_FLL1_CONTROL_5 0x186
  67. #define WM5100_FLL1_CONTROL_6 0x187
  68. #define WM5100_FLL1_EFS_1 0x188
  69. #define WM5100_FLL2_CONTROL_1 0x1A2
  70. #define WM5100_FLL2_CONTROL_2 0x1A3
  71. #define WM5100_FLL2_CONTROL_3 0x1A4
  72. #define WM5100_FLL2_CONTROL_5 0x1A6
  73. #define WM5100_FLL2_CONTROL_6 0x1A7
  74. #define WM5100_FLL2_EFS_1 0x1A8
  75. #define WM5100_MIC_CHARGE_PUMP_1 0x200
  76. #define WM5100_MIC_CHARGE_PUMP_2 0x201
  77. #define WM5100_HP_CHARGE_PUMP_1 0x202
  78. #define WM5100_LDO1_CONTROL 0x211
  79. #define WM5100_MIC_BIAS_CTRL_1 0x215
  80. #define WM5100_MIC_BIAS_CTRL_2 0x216
  81. #define WM5100_MIC_BIAS_CTRL_3 0x217
  82. #define WM5100_ACCESSORY_DETECT_MODE_1 0x280
  83. #define WM5100_HEADPHONE_DETECT_1 0x288
  84. #define WM5100_HEADPHONE_DETECT_2 0x289
  85. #define WM5100_MIC_DETECT_1 0x290
  86. #define WM5100_MIC_DETECT_2 0x291
  87. #define WM5100_MIC_DETECT_3 0x292
  88. #define WM5100_MISC_CONTROL 0x2BB
  89. #define WM5100_INPUT_ENABLES 0x301
  90. #define WM5100_INPUT_ENABLES_STATUS 0x302
  91. #define WM5100_IN1L_CONTROL 0x310
  92. #define WM5100_IN1R_CONTROL 0x311
  93. #define WM5100_IN2L_CONTROL 0x312
  94. #define WM5100_IN2R_CONTROL 0x313
  95. #define WM5100_IN3L_CONTROL 0x314
  96. #define WM5100_IN3R_CONTROL 0x315
  97. #define WM5100_IN4L_CONTROL 0x316
  98. #define WM5100_IN4R_CONTROL 0x317
  99. #define WM5100_RXANC_SRC 0x318
  100. #define WM5100_INPUT_VOLUME_RAMP 0x319
  101. #define WM5100_ADC_DIGITAL_VOLUME_1L 0x320
  102. #define WM5100_ADC_DIGITAL_VOLUME_1R 0x321
  103. #define WM5100_ADC_DIGITAL_VOLUME_2L 0x322
  104. #define WM5100_ADC_DIGITAL_VOLUME_2R 0x323
  105. #define WM5100_ADC_DIGITAL_VOLUME_3L 0x324
  106. #define WM5100_ADC_DIGITAL_VOLUME_3R 0x325
  107. #define WM5100_ADC_DIGITAL_VOLUME_4L 0x326
  108. #define WM5100_ADC_DIGITAL_VOLUME_4R 0x327
  109. #define WM5100_OUTPUT_ENABLES_2 0x401
  110. #define WM5100_OUTPUT_STATUS_1 0x402
  111. #define WM5100_OUTPUT_STATUS_2 0x403
  112. #define WM5100_CHANNEL_ENABLES_1 0x408
  113. #define WM5100_OUT_VOLUME_1L 0x410
  114. #define WM5100_OUT_VOLUME_1R 0x411
  115. #define WM5100_DAC_VOLUME_LIMIT_1L 0x412
  116. #define WM5100_DAC_VOLUME_LIMIT_1R 0x413
  117. #define WM5100_OUT_VOLUME_2L 0x414
  118. #define WM5100_OUT_VOLUME_2R 0x415
  119. #define WM5100_DAC_VOLUME_LIMIT_2L 0x416
  120. #define WM5100_DAC_VOLUME_LIMIT_2R 0x417
  121. #define WM5100_OUT_VOLUME_3L 0x418
  122. #define WM5100_OUT_VOLUME_3R 0x419
  123. #define WM5100_DAC_VOLUME_LIMIT_3L 0x41A
  124. #define WM5100_DAC_VOLUME_LIMIT_3R 0x41B
  125. #define WM5100_OUT_VOLUME_4L 0x41C
  126. #define WM5100_OUT_VOLUME_4R 0x41D
  127. #define WM5100_DAC_VOLUME_LIMIT_5L 0x41E
  128. #define WM5100_DAC_VOLUME_LIMIT_5R 0x41F
  129. #define WM5100_DAC_VOLUME_LIMIT_6L 0x420
  130. #define WM5100_DAC_VOLUME_LIMIT_6R 0x421
  131. #define WM5100_DAC_AEC_CONTROL_1 0x440
  132. #define WM5100_OUTPUT_VOLUME_RAMP 0x441
  133. #define WM5100_DAC_DIGITAL_VOLUME_1L 0x480
  134. #define WM5100_DAC_DIGITAL_VOLUME_1R 0x481
  135. #define WM5100_DAC_DIGITAL_VOLUME_2L 0x482
  136. #define WM5100_DAC_DIGITAL_VOLUME_2R 0x483
  137. #define WM5100_DAC_DIGITAL_VOLUME_3L 0x484
  138. #define WM5100_DAC_DIGITAL_VOLUME_3R 0x485
  139. #define WM5100_DAC_DIGITAL_VOLUME_4L 0x486
  140. #define WM5100_DAC_DIGITAL_VOLUME_4R 0x487
  141. #define WM5100_DAC_DIGITAL_VOLUME_5L 0x488
  142. #define WM5100_DAC_DIGITAL_VOLUME_5R 0x489
  143. #define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A
  144. #define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B
  145. #define WM5100_PDM_SPK1_CTRL_1 0x4C0
  146. #define WM5100_PDM_SPK1_CTRL_2 0x4C1
  147. #define WM5100_PDM_SPK2_CTRL_1 0x4C2
  148. #define WM5100_PDM_SPK2_CTRL_2 0x4C3
  149. #define WM5100_AUDIO_IF_1_1 0x500
  150. #define WM5100_AUDIO_IF_1_2 0x501
  151. #define WM5100_AUDIO_IF_1_3 0x502
  152. #define WM5100_AUDIO_IF_1_4 0x503
  153. #define WM5100_AUDIO_IF_1_5 0x504
  154. #define WM5100_AUDIO_IF_1_6 0x505
  155. #define WM5100_AUDIO_IF_1_7 0x506
  156. #define WM5100_AUDIO_IF_1_8 0x507
  157. #define WM5100_AUDIO_IF_1_9 0x508
  158. #define WM5100_AUDIO_IF_1_10 0x509
  159. #define WM5100_AUDIO_IF_1_11 0x50A
  160. #define WM5100_AUDIO_IF_1_12 0x50B
  161. #define WM5100_AUDIO_IF_1_13 0x50C
  162. #define WM5100_AUDIO_IF_1_14 0x50D
  163. #define WM5100_AUDIO_IF_1_15 0x50E
  164. #define WM5100_AUDIO_IF_1_16 0x50F
  165. #define WM5100_AUDIO_IF_1_17 0x510
  166. #define WM5100_AUDIO_IF_1_18 0x511
  167. #define WM5100_AUDIO_IF_1_19 0x512
  168. #define WM5100_AUDIO_IF_1_20 0x513
  169. #define WM5100_AUDIO_IF_1_21 0x514
  170. #define WM5100_AUDIO_IF_1_22 0x515
  171. #define WM5100_AUDIO_IF_1_23 0x516
  172. #define WM5100_AUDIO_IF_1_24 0x517
  173. #define WM5100_AUDIO_IF_1_25 0x518
  174. #define WM5100_AUDIO_IF_1_26 0x519
  175. #define WM5100_AUDIO_IF_1_27 0x51A
  176. #define WM5100_AUDIO_IF_2_1 0x540
  177. #define WM5100_AUDIO_IF_2_2 0x541
  178. #define WM5100_AUDIO_IF_2_3 0x542
  179. #define WM5100_AUDIO_IF_2_4 0x543
  180. #define WM5100_AUDIO_IF_2_5 0x544
  181. #define WM5100_AUDIO_IF_2_6 0x545
  182. #define WM5100_AUDIO_IF_2_7 0x546
  183. #define WM5100_AUDIO_IF_2_8 0x547
  184. #define WM5100_AUDIO_IF_2_9 0x548
  185. #define WM5100_AUDIO_IF_2_10 0x549
  186. #define WM5100_AUDIO_IF_2_11 0x54A
  187. #define WM5100_AUDIO_IF_2_18 0x551
  188. #define WM5100_AUDIO_IF_2_19 0x552
  189. #define WM5100_AUDIO_IF_2_26 0x559
  190. #define WM5100_AUDIO_IF_2_27 0x55A
  191. #define WM5100_AUDIO_IF_3_1 0x580
  192. #define WM5100_AUDIO_IF_3_2 0x581
  193. #define WM5100_AUDIO_IF_3_3 0x582
  194. #define WM5100_AUDIO_IF_3_4 0x583
  195. #define WM5100_AUDIO_IF_3_5 0x584
  196. #define WM5100_AUDIO_IF_3_6 0x585
  197. #define WM5100_AUDIO_IF_3_7 0x586
  198. #define WM5100_AUDIO_IF_3_8 0x587
  199. #define WM5100_AUDIO_IF_3_9 0x588
  200. #define WM5100_AUDIO_IF_3_10 0x589
  201. #define WM5100_AUDIO_IF_3_11 0x58A
  202. #define WM5100_AUDIO_IF_3_18 0x591
  203. #define WM5100_AUDIO_IF_3_19 0x592
  204. #define WM5100_AUDIO_IF_3_26 0x599
  205. #define WM5100_AUDIO_IF_3_27 0x59A
  206. #define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640
  207. #define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641
  208. #define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642
  209. #define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643
  210. #define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644
  211. #define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645
  212. #define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646
  213. #define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647
  214. #define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648
  215. #define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649
  216. #define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A
  217. #define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B
  218. #define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C
  219. #define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D
  220. #define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E
  221. #define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F
  222. #define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680
  223. #define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681
  224. #define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682
  225. #define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683
  226. #define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684
  227. #define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685
  228. #define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686
  229. #define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687
  230. #define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688
  231. #define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689
  232. #define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A
  233. #define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B
  234. #define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C
  235. #define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D
  236. #define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E
  237. #define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F
  238. #define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690
  239. #define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691
  240. #define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692
  241. #define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693
  242. #define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694
  243. #define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695
  244. #define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696
  245. #define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697
  246. #define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698
  247. #define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699
  248. #define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A
  249. #define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B
  250. #define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C
  251. #define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D
  252. #define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E
  253. #define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F
  254. #define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0
  255. #define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1
  256. #define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2
  257. #define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3
  258. #define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4
  259. #define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5
  260. #define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6
  261. #define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7
  262. #define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8
  263. #define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9
  264. #define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA
  265. #define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB
  266. #define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC
  267. #define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD
  268. #define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE
  269. #define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF
  270. #define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0
  271. #define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1
  272. #define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2
  273. #define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3
  274. #define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4
  275. #define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5
  276. #define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6
  277. #define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7
  278. #define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8
  279. #define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9
  280. #define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA
  281. #define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB
  282. #define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC
  283. #define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD
  284. #define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE
  285. #define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF
  286. #define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0
  287. #define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1
  288. #define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2
  289. #define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3
  290. #define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4
  291. #define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5
  292. #define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6
  293. #define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7
  294. #define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8
  295. #define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9
  296. #define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA
  297. #define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB
  298. #define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC
  299. #define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD
  300. #define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE
  301. #define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF
  302. #define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0
  303. #define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1
  304. #define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2
  305. #define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3
  306. #define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4
  307. #define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5
  308. #define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6
  309. #define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7
  310. #define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8
  311. #define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9
  312. #define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA
  313. #define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB
  314. #define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC
  315. #define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD
  316. #define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE
  317. #define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF
  318. #define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700
  319. #define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701
  320. #define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702
  321. #define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703
  322. #define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704
  323. #define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705
  324. #define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706
  325. #define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707
  326. #define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708
  327. #define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709
  328. #define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
  329. #define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
  330. #define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
  331. #define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
  332. #define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
  333. #define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
  334. #define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710
  335. #define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711
  336. #define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712
  337. #define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713
  338. #define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714
  339. #define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715
  340. #define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716
  341. #define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717
  342. #define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718
  343. #define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719
  344. #define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
  345. #define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
  346. #define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
  347. #define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
  348. #define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
  349. #define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
  350. #define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720
  351. #define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721
  352. #define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722
  353. #define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723
  354. #define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724
  355. #define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725
  356. #define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726
  357. #define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727
  358. #define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728
  359. #define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729
  360. #define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
  361. #define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
  362. #define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
  363. #define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
  364. #define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
  365. #define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
  366. #define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730
  367. #define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731
  368. #define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732
  369. #define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733
  370. #define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734
  371. #define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735
  372. #define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736
  373. #define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737
  374. #define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738
  375. #define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739
  376. #define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
  377. #define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
  378. #define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
  379. #define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
  380. #define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
  381. #define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
  382. #define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740
  383. #define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741
  384. #define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742
  385. #define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743
  386. #define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744
  387. #define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745
  388. #define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746
  389. #define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747
  390. #define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748
  391. #define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749
  392. #define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
  393. #define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
  394. #define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
  395. #define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
  396. #define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
  397. #define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
  398. #define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780
  399. #define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781
  400. #define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782
  401. #define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783
  402. #define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784
  403. #define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785
  404. #define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786
  405. #define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787
  406. #define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788
  407. #define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789
  408. #define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
  409. #define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
  410. #define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
  411. #define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
  412. #define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
  413. #define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
  414. #define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880
  415. #define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881
  416. #define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882
  417. #define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883
  418. #define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884
  419. #define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885
  420. #define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886
  421. #define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887
  422. #define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888
  423. #define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889
  424. #define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A
  425. #define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B
  426. #define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C
  427. #define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D
  428. #define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E
  429. #define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F
  430. #define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890
  431. #define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891
  432. #define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892
  433. #define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893
  434. #define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894
  435. #define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895
  436. #define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896
  437. #define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897
  438. #define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898
  439. #define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899
  440. #define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A
  441. #define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B
  442. #define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C
  443. #define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D
  444. #define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E
  445. #define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F
  446. #define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0
  447. #define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1
  448. #define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2
  449. #define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3
  450. #define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4
  451. #define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5
  452. #define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6
  453. #define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7
  454. #define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8
  455. #define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9
  456. #define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA
  457. #define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB
  458. #define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC
  459. #define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD
  460. #define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE
  461. #define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF
  462. #define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900
  463. #define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901
  464. #define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902
  465. #define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903
  466. #define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904
  467. #define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905
  468. #define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906
  469. #define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907
  470. #define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908
  471. #define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909
  472. #define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A
  473. #define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B
  474. #define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C
  475. #define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D
  476. #define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E
  477. #define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F
  478. #define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910
  479. #define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911
  480. #define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912
  481. #define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913
  482. #define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914
  483. #define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915
  484. #define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916
  485. #define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917
  486. #define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918
  487. #define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919
  488. #define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A
  489. #define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B
  490. #define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C
  491. #define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D
  492. #define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E
  493. #define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F
  494. #define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940
  495. #define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941
  496. #define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942
  497. #define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943
  498. #define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944
  499. #define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945
  500. #define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946
  501. #define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947
  502. #define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948
  503. #define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949
  504. #define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A
  505. #define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B
  506. #define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C
  507. #define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D
  508. #define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E
  509. #define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F
  510. #define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
  511. #define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
  512. #define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
  513. #define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
  514. #define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
  515. #define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
  516. #define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980
  517. #define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981
  518. #define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982
  519. #define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983
  520. #define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984
  521. #define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985
  522. #define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986
  523. #define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987
  524. #define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988
  525. #define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989
  526. #define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A
  527. #define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B
  528. #define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C
  529. #define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D
  530. #define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E
  531. #define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F
  532. #define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990
  533. #define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998
  534. #define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0
  535. #define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8
  536. #define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0
  537. #define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8
  538. #define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0
  539. #define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1
  540. #define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2
  541. #define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3
  542. #define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4
  543. #define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5
  544. #define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6
  545. #define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7
  546. #define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8
  547. #define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9
  548. #define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA
  549. #define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB
  550. #define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC
  551. #define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD
  552. #define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE
  553. #define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF
  554. #define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0
  555. #define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8
  556. #define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0
  557. #define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8
  558. #define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0
  559. #define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8
  560. #define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80
  561. #define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88
  562. #define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90
  563. #define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98
  564. #define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
  565. #define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
  566. #define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10
  567. #define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18
  568. #define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
  569. #define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
  570. #define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
  571. #define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
  572. #define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
  573. #define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
  574. #define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50
  575. #define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58
  576. #define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
  577. #define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
  578. #define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70
  579. #define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78
  580. #define WM5100_GPIO_CTRL_1 0xC00
  581. #define WM5100_GPIO_CTRL_2 0xC01
  582. #define WM5100_GPIO_CTRL_3 0xC02
  583. #define WM5100_GPIO_CTRL_4 0xC03
  584. #define WM5100_GPIO_CTRL_5 0xC04
  585. #define WM5100_GPIO_CTRL_6 0xC05
  586. #define WM5100_MISC_PAD_CTRL_1 0xC23
  587. #define WM5100_MISC_PAD_CTRL_2 0xC24
  588. #define WM5100_MISC_PAD_CTRL_3 0xC25
  589. #define WM5100_MISC_PAD_CTRL_4 0xC26
  590. #define WM5100_MISC_PAD_CTRL_5 0xC27
  591. #define WM5100_MISC_GPIO_1 0xC28
  592. #define WM5100_INTERRUPT_STATUS_1 0xD00
  593. #define WM5100_INTERRUPT_STATUS_2 0xD01
  594. #define WM5100_INTERRUPT_STATUS_3 0xD02
  595. #define WM5100_INTERRUPT_STATUS_4 0xD03
  596. #define WM5100_INTERRUPT_RAW_STATUS_2 0xD04
  597. #define WM5100_INTERRUPT_RAW_STATUS_3 0xD05
  598. #define WM5100_INTERRUPT_RAW_STATUS_4 0xD06
  599. #define WM5100_INTERRUPT_STATUS_1_MASK 0xD07
  600. #define WM5100_INTERRUPT_STATUS_2_MASK 0xD08
  601. #define WM5100_INTERRUPT_STATUS_3_MASK 0xD09
  602. #define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A
  603. #define WM5100_INTERRUPT_CONTROL 0xD1F
  604. #define WM5100_IRQ_DEBOUNCE_1 0xD20
  605. #define WM5100_IRQ_DEBOUNCE_2 0xD21
  606. #define WM5100_FX_CTRL 0xE00
  607. #define WM5100_EQ1_1 0xE10
  608. #define WM5100_EQ1_2 0xE11
  609. #define WM5100_EQ1_3 0xE12
  610. #define WM5100_EQ1_4 0xE13
  611. #define WM5100_EQ1_5 0xE14
  612. #define WM5100_EQ1_6 0xE15
  613. #define WM5100_EQ1_7 0xE16
  614. #define WM5100_EQ1_8 0xE17
  615. #define WM5100_EQ1_9 0xE18
  616. #define WM5100_EQ1_10 0xE19
  617. #define WM5100_EQ1_11 0xE1A
  618. #define WM5100_EQ1_12 0xE1B
  619. #define WM5100_EQ1_13 0xE1C
  620. #define WM5100_EQ1_14 0xE1D
  621. #define WM5100_EQ1_15 0xE1E
  622. #define WM5100_EQ1_16 0xE1F
  623. #define WM5100_EQ1_17 0xE20
  624. #define WM5100_EQ1_18 0xE21
  625. #define WM5100_EQ1_19 0xE22
  626. #define WM5100_EQ1_20 0xE23
  627. #define WM5100_EQ2_1 0xE26
  628. #define WM5100_EQ2_2 0xE27
  629. #define WM5100_EQ2_3 0xE28
  630. #define WM5100_EQ2_4 0xE29
  631. #define WM5100_EQ2_5 0xE2A
  632. #define WM5100_EQ2_6 0xE2B
  633. #define WM5100_EQ2_7 0xE2C
  634. #define WM5100_EQ2_8 0xE2D
  635. #define WM5100_EQ2_9 0xE2E
  636. #define WM5100_EQ2_10 0xE2F
  637. #define WM5100_EQ2_11 0xE30
  638. #define WM5100_EQ2_12 0xE31
  639. #define WM5100_EQ2_13 0xE32
  640. #define WM5100_EQ2_14 0xE33
  641. #define WM5100_EQ2_15 0xE34
  642. #define WM5100_EQ2_16 0xE35
  643. #define WM5100_EQ2_17 0xE36
  644. #define WM5100_EQ2_18 0xE37
  645. #define WM5100_EQ2_19 0xE38
  646. #define WM5100_EQ2_20 0xE39
  647. #define WM5100_EQ3_1 0xE3C
  648. #define WM5100_EQ3_2 0xE3D
  649. #define WM5100_EQ3_3 0xE3E
  650. #define WM5100_EQ3_4 0xE3F
  651. #define WM5100_EQ3_5 0xE40
  652. #define WM5100_EQ3_6 0xE41
  653. #define WM5100_EQ3_7 0xE42
  654. #define WM5100_EQ3_8 0xE43
  655. #define WM5100_EQ3_9 0xE44
  656. #define WM5100_EQ3_10 0xE45
  657. #define WM5100_EQ3_11 0xE46
  658. #define WM5100_EQ3_12 0xE47
  659. #define WM5100_EQ3_13 0xE48
  660. #define WM5100_EQ3_14 0xE49
  661. #define WM5100_EQ3_15 0xE4A
  662. #define WM5100_EQ3_16 0xE4B
  663. #define WM5100_EQ3_17 0xE4C
  664. #define WM5100_EQ3_18 0xE4D
  665. #define WM5100_EQ3_19 0xE4E
  666. #define WM5100_EQ3_20 0xE4F
  667. #define WM5100_EQ4_1 0xE52
  668. #define WM5100_EQ4_2 0xE53
  669. #define WM5100_EQ4_3 0xE54
  670. #define WM5100_EQ4_4 0xE55
  671. #define WM5100_EQ4_5 0xE56
  672. #define WM5100_EQ4_6 0xE57
  673. #define WM5100_EQ4_7 0xE58
  674. #define WM5100_EQ4_8 0xE59
  675. #define WM5100_EQ4_9 0xE5A
  676. #define WM5100_EQ4_10 0xE5B
  677. #define WM5100_EQ4_11 0xE5C
  678. #define WM5100_EQ4_12 0xE5D
  679. #define WM5100_EQ4_13 0xE5E
  680. #define WM5100_EQ4_14 0xE5F
  681. #define WM5100_EQ4_15 0xE60
  682. #define WM5100_EQ4_16 0xE61
  683. #define WM5100_EQ4_17 0xE62
  684. #define WM5100_EQ4_18 0xE63
  685. #define WM5100_EQ4_19 0xE64
  686. #define WM5100_EQ4_20 0xE65
  687. #define WM5100_DRC1_CTRL1 0xE80
  688. #define WM5100_DRC1_CTRL2 0xE81
  689. #define WM5100_DRC1_CTRL3 0xE82
  690. #define WM5100_DRC1_CTRL4 0xE83
  691. #define WM5100_DRC1_CTRL5 0xE84
  692. #define WM5100_HPLPF1_1 0xEC0
  693. #define WM5100_HPLPF1_2 0xEC1
  694. #define WM5100_HPLPF2_1 0xEC4
  695. #define WM5100_HPLPF2_2 0xEC5
  696. #define WM5100_HPLPF3_1 0xEC8
  697. #define WM5100_HPLPF3_2 0xEC9
  698. #define WM5100_HPLPF4_1 0xECC
  699. #define WM5100_HPLPF4_2 0xECD
  700. #define WM5100_DSP1_CONTROL_1 0xF00
  701. #define WM5100_DSP1_CONTROL_2 0xF02
  702. #define WM5100_DSP1_CONTROL_3 0xF03
  703. #define WM5100_DSP1_CONTROL_4 0xF04
  704. #define WM5100_DSP1_CONTROL_5 0xF06
  705. #define WM5100_DSP1_CONTROL_6 0xF07
  706. #define WM5100_DSP1_CONTROL_7 0xF08
  707. #define WM5100_DSP1_CONTROL_8 0xF09
  708. #define WM5100_DSP1_CONTROL_9 0xF0A
  709. #define WM5100_DSP1_CONTROL_10 0xF0B
  710. #define WM5100_DSP1_CONTROL_11 0xF0C
  711. #define WM5100_DSP1_CONTROL_12 0xF0D
  712. #define WM5100_DSP1_CONTROL_13 0xF0F
  713. #define WM5100_DSP1_CONTROL_14 0xF10
  714. #define WM5100_DSP1_CONTROL_15 0xF11
  715. #define WM5100_DSP1_CONTROL_16 0xF12
  716. #define WM5100_DSP1_CONTROL_17 0xF13
  717. #define WM5100_DSP1_CONTROL_18 0xF14
  718. #define WM5100_DSP1_CONTROL_19 0xF16
  719. #define WM5100_DSP1_CONTROL_20 0xF17
  720. #define WM5100_DSP1_CONTROL_21 0xF18
  721. #define WM5100_DSP1_CONTROL_22 0xF1A
  722. #define WM5100_DSP1_CONTROL_23 0xF1B
  723. #define WM5100_DSP1_CONTROL_24 0xF1C
  724. #define WM5100_DSP1_CONTROL_25 0xF1E
  725. #define WM5100_DSP1_CONTROL_26 0xF20
  726. #define WM5100_DSP1_CONTROL_27 0xF21
  727. #define WM5100_DSP1_CONTROL_28 0xF22
  728. #define WM5100_DSP1_CONTROL_29 0xF23
  729. #define WM5100_DSP1_CONTROL_30 0xF24
  730. #define WM5100_DSP2_CONTROL_1 0x1000
  731. #define WM5100_DSP2_CONTROL_2 0x1002
  732. #define WM5100_DSP2_CONTROL_3 0x1003
  733. #define WM5100_DSP2_CONTROL_4 0x1004
  734. #define WM5100_DSP2_CONTROL_5 0x1006
  735. #define WM5100_DSP2_CONTROL_6 0x1007
  736. #define WM5100_DSP2_CONTROL_7 0x1008
  737. #define WM5100_DSP2_CONTROL_8 0x1009
  738. #define WM5100_DSP2_CONTROL_9 0x100A
  739. #define WM5100_DSP2_CONTROL_10 0x100B
  740. #define WM5100_DSP2_CONTROL_11 0x100C
  741. #define WM5100_DSP2_CONTROL_12 0x100D
  742. #define WM5100_DSP2_CONTROL_13 0x100F
  743. #define WM5100_DSP2_CONTROL_14 0x1010
  744. #define WM5100_DSP2_CONTROL_15 0x1011
  745. #define WM5100_DSP2_CONTROL_16 0x1012
  746. #define WM5100_DSP2_CONTROL_17 0x1013
  747. #define WM5100_DSP2_CONTROL_18 0x1014
  748. #define WM5100_DSP2_CONTROL_19 0x1016
  749. #define WM5100_DSP2_CONTROL_20 0x1017
  750. #define WM5100_DSP2_CONTROL_21 0x1018
  751. #define WM5100_DSP2_CONTROL_22 0x101A
  752. #define WM5100_DSP2_CONTROL_23 0x101B
  753. #define WM5100_DSP2_CONTROL_24 0x101C
  754. #define WM5100_DSP2_CONTROL_25 0x101E
  755. #define WM5100_DSP2_CONTROL_26 0x1020
  756. #define WM5100_DSP2_CONTROL_27 0x1021
  757. #define WM5100_DSP2_CONTROL_28 0x1022
  758. #define WM5100_DSP2_CONTROL_29 0x1023
  759. #define WM5100_DSP2_CONTROL_30 0x1024
  760. #define WM5100_DSP3_CONTROL_1 0x1100
  761. #define WM5100_DSP3_CONTROL_2 0x1102
  762. #define WM5100_DSP3_CONTROL_3 0x1103
  763. #define WM5100_DSP3_CONTROL_4 0x1104
  764. #define WM5100_DSP3_CONTROL_5 0x1106
  765. #define WM5100_DSP3_CONTROL_6 0x1107
  766. #define WM5100_DSP3_CONTROL_7 0x1108
  767. #define WM5100_DSP3_CONTROL_8 0x1109
  768. #define WM5100_DSP3_CONTROL_9 0x110A
  769. #define WM5100_DSP3_CONTROL_10 0x110B
  770. #define WM5100_DSP3_CONTROL_11 0x110C
  771. #define WM5100_DSP3_CONTROL_12 0x110D
  772. #define WM5100_DSP3_CONTROL_13 0x110F
  773. #define WM5100_DSP3_CONTROL_14 0x1110
  774. #define WM5100_DSP3_CONTROL_15 0x1111
  775. #define WM5100_DSP3_CONTROL_16 0x1112
  776. #define WM5100_DSP3_CONTROL_17 0x1113
  777. #define WM5100_DSP3_CONTROL_18 0x1114
  778. #define WM5100_DSP3_CONTROL_19 0x1116
  779. #define WM5100_DSP3_CONTROL_20 0x1117
  780. #define WM5100_DSP3_CONTROL_21 0x1118
  781. #define WM5100_DSP3_CONTROL_22 0x111A
  782. #define WM5100_DSP3_CONTROL_23 0x111B
  783. #define WM5100_DSP3_CONTROL_24 0x111C
  784. #define WM5100_DSP3_CONTROL_25 0x111E
  785. #define WM5100_DSP3_CONTROL_26 0x1120
  786. #define WM5100_DSP3_CONTROL_27 0x1121
  787. #define WM5100_DSP3_CONTROL_28 0x1122
  788. #define WM5100_DSP3_CONTROL_29 0x1123
  789. #define WM5100_DSP3_CONTROL_30 0x1124
  790. #define WM5100_DSP1_DM_0 0x4000
  791. #define WM5100_DSP1_DM_1 0x4001
  792. #define WM5100_DSP1_DM_2 0x4002
  793. #define WM5100_DSP1_DM_3 0x4003
  794. #define WM5100_DSP1_DM_508 0x41FC
  795. #define WM5100_DSP1_DM_509 0x41FD
  796. #define WM5100_DSP1_DM_510 0x41FE
  797. #define WM5100_DSP1_DM_511 0x41FF
  798. #define WM5100_DSP1_PM_0 0x4800
  799. #define WM5100_DSP1_PM_1 0x4801
  800. #define WM5100_DSP1_PM_2 0x4802
  801. #define WM5100_DSP1_PM_3 0x4803
  802. #define WM5100_DSP1_PM_4 0x4804
  803. #define WM5100_DSP1_PM_5 0x4805
  804. #define WM5100_DSP1_PM_1530 0x4DFA
  805. #define WM5100_DSP1_PM_1531 0x4DFB
  806. #define WM5100_DSP1_PM_1532 0x4DFC
  807. #define WM5100_DSP1_PM_1533 0x4DFD
  808. #define WM5100_DSP1_PM_1534 0x4DFE
  809. #define WM5100_DSP1_PM_1535 0x4DFF
  810. #define WM5100_DSP1_ZM_0 0x5000
  811. #define WM5100_DSP1_ZM_1 0x5001
  812. #define WM5100_DSP1_ZM_2 0x5002
  813. #define WM5100_DSP1_ZM_3 0x5003
  814. #define WM5100_DSP1_ZM_2044 0x57FC
  815. #define WM5100_DSP1_ZM_2045 0x57FD
  816. #define WM5100_DSP1_ZM_2046 0x57FE
  817. #define WM5100_DSP1_ZM_2047 0x57FF
  818. #define WM5100_DSP2_DM_0 0x6000
  819. #define WM5100_DSP2_DM_1 0x6001
  820. #define WM5100_DSP2_DM_2 0x6002
  821. #define WM5100_DSP2_DM_3 0x6003
  822. #define WM5100_DSP2_DM_508 0x61FC
  823. #define WM5100_DSP2_DM_509 0x61FD
  824. #define WM5100_DSP2_DM_510 0x61FE
  825. #define WM5100_DSP2_DM_511 0x61FF
  826. #define WM5100_DSP2_PM_0 0x6800
  827. #define WM5100_DSP2_PM_1 0x6801
  828. #define WM5100_DSP2_PM_2 0x6802
  829. #define WM5100_DSP2_PM_3 0x6803
  830. #define WM5100_DSP2_PM_4 0x6804
  831. #define WM5100_DSP2_PM_5 0x6805
  832. #define WM5100_DSP2_PM_1530 0x6DFA
  833. #define WM5100_DSP2_PM_1531 0x6DFB
  834. #define WM5100_DSP2_PM_1532 0x6DFC
  835. #define WM5100_DSP2_PM_1533 0x6DFD
  836. #define WM5100_DSP2_PM_1534 0x6DFE
  837. #define WM5100_DSP2_PM_1535 0x6DFF
  838. #define WM5100_DSP2_ZM_0 0x7000
  839. #define WM5100_DSP2_ZM_1 0x7001
  840. #define WM5100_DSP2_ZM_2 0x7002
  841. #define WM5100_DSP2_ZM_3 0x7003
  842. #define WM5100_DSP2_ZM_2044 0x77FC
  843. #define WM5100_DSP2_ZM_2045 0x77FD
  844. #define WM5100_DSP2_ZM_2046 0x77FE
  845. #define WM5100_DSP2_ZM_2047 0x77FF
  846. #define WM5100_DSP3_DM_0 0x8000
  847. #define WM5100_DSP3_DM_1 0x8001
  848. #define WM5100_DSP3_DM_2 0x8002
  849. #define WM5100_DSP3_DM_3 0x8003
  850. #define WM5100_DSP3_DM_508 0x81FC
  851. #define WM5100_DSP3_DM_509 0x81FD
  852. #define WM5100_DSP3_DM_510 0x81FE
  853. #define WM5100_DSP3_DM_511 0x81FF
  854. #define WM5100_DSP3_PM_0 0x8800
  855. #define WM5100_DSP3_PM_1 0x8801
  856. #define WM5100_DSP3_PM_2 0x8802
  857. #define WM5100_DSP3_PM_3 0x8803
  858. #define WM5100_DSP3_PM_4 0x8804
  859. #define WM5100_DSP3_PM_5 0x8805
  860. #define WM5100_DSP3_PM_1530 0x8DFA
  861. #define WM5100_DSP3_PM_1531 0x8DFB
  862. #define WM5100_DSP3_PM_1532 0x8DFC
  863. #define WM5100_DSP3_PM_1533 0x8DFD
  864. #define WM5100_DSP3_PM_1534 0x8DFE
  865. #define WM5100_DSP3_PM_1535 0x8DFF
  866. #define WM5100_DSP3_ZM_0 0x9000
  867. #define WM5100_DSP3_ZM_1 0x9001
  868. #define WM5100_DSP3_ZM_2 0x9002
  869. #define WM5100_DSP3_ZM_3 0x9003
  870. #define WM5100_DSP3_ZM_2044 0x97FC
  871. #define WM5100_DSP3_ZM_2045 0x97FD
  872. #define WM5100_DSP3_ZM_2046 0x97FE
  873. #define WM5100_DSP3_ZM_2047 0x97FF
  874. #define WM5100_REGISTER_COUNT 1435
  875. #define WM5100_MAX_REGISTER 0x97FF
  876. /*
  877. * Field Definitions.
  878. */
  879. /*
  880. * R0 (0x00) - software reset
  881. */
  882. #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  883. #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  884. #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  885. /*
  886. * R1 (0x01) - Device Revision
  887. */
  888. #define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */
  889. #define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */
  890. #define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */
  891. /*
  892. * R16 (0x10) - Ctrl IF 1
  893. */
  894. #define WM5100_AUTO_INC 0x0001 /* AUTO_INC */
  895. #define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */
  896. #define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */
  897. #define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */
  898. /*
  899. * R32 (0x20) - Tone Generator 1
  900. */
  901. #define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */
  902. #define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */
  903. #define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */
  904. #define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
  905. #define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
  906. #define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
  907. #define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */
  908. #define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
  909. #define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
  910. #define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
  911. #define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */
  912. #define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
  913. #define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
  914. #define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
  915. /*
  916. * R48 (0x30) - PWM Drive 1
  917. */
  918. #define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */
  919. #define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */
  920. #define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */
  921. #define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */
  922. #define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */
  923. #define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */
  924. #define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */
  925. #define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
  926. #define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
  927. #define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
  928. #define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */
  929. #define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
  930. #define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
  931. #define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
  932. #define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */
  933. #define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
  934. #define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
  935. #define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
  936. #define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */
  937. #define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
  938. #define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
  939. #define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
  940. /*
  941. * R49 (0x31) - PWM Drive 2
  942. */
  943. #define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
  944. #define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
  945. #define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
  946. /*
  947. * R50 (0x32) - PWM Drive 3
  948. */
  949. #define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
  950. #define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
  951. #define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
  952. /*
  953. * R256 (0x100) - Clocking 1
  954. */
  955. #define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */
  956. #define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */
  957. #define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */
  958. /*
  959. * R257 (0x101) - Clocking 3
  960. */
  961. #define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
  962. #define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
  963. #define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
  964. #define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
  965. #define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
  966. #define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
  967. #define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
  968. #define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
  969. #define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
  970. #define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
  971. /*
  972. * R258 (0x102) - Clocking 4
  973. */
  974. #define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
  975. #define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
  976. #define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
  977. /*
  978. * R259 (0x103) - Clocking 5
  979. */
  980. #define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
  981. #define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
  982. #define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
  983. /*
  984. * R260 (0x104) - Clocking 6
  985. */
  986. #define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
  987. #define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
  988. #define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
  989. /*
  990. * R263 (0x107) - Clocking 7
  991. */
  992. #define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
  993. #define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
  994. #define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
  995. #define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
  996. #define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
  997. #define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
  998. #define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
  999. #define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
  1000. #define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
  1001. #define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
  1002. /*
  1003. * R264 (0x108) - Clocking 8
  1004. */
  1005. #define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
  1006. #define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
  1007. #define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
  1008. /*
  1009. * R288 (0x120) - ASRC_ENABLE
  1010. */
  1011. #define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
  1012. #define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
  1013. #define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
  1014. #define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
  1015. #define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
  1016. #define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
  1017. #define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
  1018. #define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
  1019. #define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
  1020. #define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
  1021. #define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
  1022. #define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
  1023. #define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
  1024. #define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
  1025. #define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
  1026. #define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
  1027. /*
  1028. * R289 (0x121) - ASRC_STATUS
  1029. */
  1030. #define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */
  1031. #define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */
  1032. #define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */
  1033. #define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */
  1034. #define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */
  1035. #define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */
  1036. #define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */
  1037. #define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */
  1038. #define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */
  1039. #define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */
  1040. #define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */
  1041. #define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */
  1042. #define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */
  1043. #define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */
  1044. #define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */
  1045. #define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */
  1046. /*
  1047. * R290 (0x122) - ASRC_RATE1
  1048. */
  1049. #define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */
  1050. #define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */
  1051. #define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */
  1052. /*
  1053. * R321 (0x141) - ISRC 1 CTRL 1
  1054. */
  1055. #define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */
  1056. #define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */
  1057. #define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */
  1058. #define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */
  1059. #define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */
  1060. #define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */
  1061. #define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */
  1062. #define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */
  1063. #define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */
  1064. #define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */
  1065. #define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */
  1066. #define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */
  1067. #define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */
  1068. /*
  1069. * R322 (0x142) - ISRC 1 CTRL 2
  1070. */
  1071. #define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */
  1072. #define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */
  1073. #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */
  1074. #define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
  1075. #define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */
  1076. #define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */
  1077. #define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */
  1078. #define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
  1079. #define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */
  1080. #define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */
  1081. #define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */
  1082. #define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
  1083. #define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */
  1084. #define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */
  1085. #define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */
  1086. #define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */
  1087. #define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */
  1088. #define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */
  1089. #define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */
  1090. #define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
  1091. #define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */
  1092. #define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */
  1093. #define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */
  1094. #define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
  1095. #define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */
  1096. #define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */
  1097. #define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */
  1098. #define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
  1099. #define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */
  1100. #define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */
  1101. #define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */
  1102. #define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */
  1103. #define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
  1104. #define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
  1105. #define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
  1106. #define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
  1107. /*
  1108. * R323 (0x143) - ISRC 2 CTRL1
  1109. */
  1110. #define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */
  1111. #define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */
  1112. #define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */
  1113. #define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */
  1114. #define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */
  1115. #define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */
  1116. #define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */
  1117. #define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */
  1118. #define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */
  1119. #define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */
  1120. #define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */
  1121. #define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */
  1122. #define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */
  1123. /*
  1124. * R324 (0x144) - ISRC 2 CTRL 2
  1125. */
  1126. #define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */
  1127. #define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */
  1128. #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */
  1129. #define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
  1130. #define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */
  1131. #define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */
  1132. #define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */
  1133. #define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
  1134. #define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */
  1135. #define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */
  1136. #define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */
  1137. #define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
  1138. #define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */
  1139. #define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */
  1140. #define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */
  1141. #define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */
  1142. #define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */
  1143. #define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */
  1144. #define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */
  1145. #define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
  1146. #define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */
  1147. #define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */
  1148. #define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */
  1149. #define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
  1150. #define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */
  1151. #define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */
  1152. #define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */
  1153. #define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
  1154. #define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */
  1155. #define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */
  1156. #define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */
  1157. #define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */
  1158. #define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
  1159. #define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
  1160. #define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
  1161. #define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
  1162. /*
  1163. * R386 (0x182) - FLL1 Control 1
  1164. */
  1165. #define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */
  1166. #define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
  1167. #define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
  1168. #define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
  1169. /*
  1170. * R387 (0x183) - FLL1 Control 2
  1171. */
  1172. #define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
  1173. #define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
  1174. #define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
  1175. #define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
  1176. #define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
  1177. #define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
  1178. /*
  1179. * R388 (0x184) - FLL1 Control 3
  1180. */
  1181. #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
  1182. #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
  1183. #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
  1184. /*
  1185. * R390 (0x186) - FLL1 Control 5
  1186. */
  1187. #define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
  1188. #define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
  1189. #define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
  1190. /*
  1191. * R391 (0x187) - FLL1 Control 6
  1192. */
  1193. #define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */
  1194. #define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */
  1195. #define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */
  1196. #define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */
  1197. #define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */
  1198. #define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */
  1199. /*
  1200. * R392 (0x188) - FLL1 EFS 1
  1201. */
  1202. #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
  1203. #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
  1204. #define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
  1205. /*
  1206. * R418 (0x1A2) - FLL2 Control 1
  1207. */
  1208. #define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */
  1209. #define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
  1210. #define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
  1211. #define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
  1212. /*
  1213. * R419 (0x1A3) - FLL2 Control 2
  1214. */
  1215. #define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
  1216. #define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
  1217. #define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
  1218. #define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
  1219. #define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
  1220. #define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
  1221. /*
  1222. * R420 (0x1A4) - FLL2 Control 3
  1223. */
  1224. #define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
  1225. #define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
  1226. #define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
  1227. /*
  1228. * R422 (0x1A6) - FLL2 Control 5
  1229. */
  1230. #define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
  1231. #define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
  1232. #define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
  1233. /*
  1234. * R423 (0x1A7) - FLL2 Control 6
  1235. */
  1236. #define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */
  1237. #define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */
  1238. #define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */
  1239. #define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */
  1240. #define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */
  1241. #define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */
  1242. /*
  1243. * R424 (0x1A8) - FLL2 EFS 1
  1244. */
  1245. #define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
  1246. #define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
  1247. #define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
  1248. /*
  1249. * R512 (0x200) - Mic Charge Pump 1
  1250. */
  1251. #define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */
  1252. #define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */
  1253. #define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */
  1254. #define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */
  1255. #define WM5100_CP2_ENA 0x0001 /* CP2_ENA */
  1256. #define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */
  1257. #define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */
  1258. #define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */
  1259. /*
  1260. * R513 (0x201) - Mic Charge Pump 2
  1261. */
  1262. #define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */
  1263. #define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */
  1264. #define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */
  1265. /*
  1266. * R514 (0x202) - HP Charge Pump 1
  1267. */
  1268. #define WM5100_CP1_ENA 0x0001 /* CP1_ENA */
  1269. #define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */
  1270. #define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */
  1271. #define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */
  1272. /*
  1273. * R529 (0x211) - LDO1 Control
  1274. */
  1275. #define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
  1276. #define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
  1277. #define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
  1278. #define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
  1279. /*
  1280. * R533 (0x215) - Mic Bias Ctrl 1
  1281. */
  1282. #define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */
  1283. #define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */
  1284. #define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */
  1285. #define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
  1286. #define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */
  1287. #define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
  1288. #define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
  1289. #define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
  1290. #define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */
  1291. #define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */
  1292. #define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */
  1293. #define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
  1294. #define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
  1295. #define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
  1296. #define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
  1297. #define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */
  1298. #define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
  1299. #define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
  1300. #define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
  1301. /*
  1302. * R534 (0x216) - Mic Bias Ctrl 2
  1303. */
  1304. #define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */
  1305. #define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */
  1306. #define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */
  1307. #define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
  1308. #define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */
  1309. #define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
  1310. #define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
  1311. #define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
  1312. #define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */
  1313. #define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */
  1314. #define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */
  1315. #define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
  1316. #define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
  1317. #define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
  1318. #define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
  1319. #define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */
  1320. #define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
  1321. #define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
  1322. #define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
  1323. /*
  1324. * R535 (0x217) - Mic Bias Ctrl 3
  1325. */
  1326. #define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */
  1327. #define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */
  1328. #define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */
  1329. #define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
  1330. #define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */
  1331. #define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */
  1332. #define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */
  1333. #define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
  1334. #define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */
  1335. #define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */
  1336. #define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */
  1337. #define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
  1338. #define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
  1339. #define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
  1340. #define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
  1341. #define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */
  1342. #define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
  1343. #define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
  1344. #define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
  1345. /*
  1346. * R640 (0x280) - Accessory Detect Mode 1
  1347. */
  1348. #define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */
  1349. #define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */
  1350. #define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */
  1351. #define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */
  1352. #define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
  1353. #define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
  1354. #define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
  1355. #define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
  1356. #define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
  1357. #define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
  1358. /*
  1359. * R648 (0x288) - Headphone Detect 1
  1360. */
  1361. #define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
  1362. #define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
  1363. #define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
  1364. #define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
  1365. #define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
  1366. #define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
  1367. #define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */
  1368. #define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */
  1369. #define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */
  1370. #define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
  1371. #define WM5100_HP_POLL 0x0001 /* HP_POLL */
  1372. #define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */
  1373. #define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */
  1374. #define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */
  1375. /*
  1376. * R649 (0x289) - Headphone Detect 2
  1377. */
  1378. #define WM5100_HP_DONE 0x0080 /* HP_DONE */
  1379. #define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */
  1380. #define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */
  1381. #define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */
  1382. #define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
  1383. #define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
  1384. #define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
  1385. /*
  1386. * R656 (0x290) - Mic Detect 1
  1387. */
  1388. #define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */
  1389. #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */
  1390. #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */
  1391. #define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */
  1392. #define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */
  1393. #define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */
  1394. #define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */
  1395. #define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */
  1396. #define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */
  1397. #define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */
  1398. #define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */
  1399. #define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */
  1400. #define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */
  1401. #define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */
  1402. /*
  1403. * R657 (0x291) - Mic Detect 2
  1404. */
  1405. #define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */
  1406. #define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */
  1407. #define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */
  1408. /*
  1409. * R658 (0x292) - Mic Detect 3
  1410. */
  1411. #define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */
  1412. #define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */
  1413. #define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */
  1414. #define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */
  1415. #define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */
  1416. #define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */
  1417. #define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */
  1418. #define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */
  1419. #define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */
  1420. #define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */
  1421. #define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */
  1422. /*
  1423. * R699 (0x2BB) - Misc Control
  1424. */
  1425. #define WM5100_HPCOM_SRC 0x200 /* HPCOM_SRC */
  1426. #define WM5100_HPCOM_SRC_SHIFT 9 /* HPCOM_SRC */
  1427. /*
  1428. * R769 (0x301) - Input Enables
  1429. */
  1430. #define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */
  1431. #define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */
  1432. #define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */
  1433. #define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */
  1434. #define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */
  1435. #define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */
  1436. #define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */
  1437. #define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */
  1438. #define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */
  1439. #define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
  1440. #define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
  1441. #define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
  1442. #define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */
  1443. #define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
  1444. #define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
  1445. #define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
  1446. #define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */
  1447. #define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
  1448. #define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
  1449. #define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
  1450. #define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */
  1451. #define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
  1452. #define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
  1453. #define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
  1454. #define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */
  1455. #define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
  1456. #define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
  1457. #define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
  1458. #define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */
  1459. #define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
  1460. #define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
  1461. #define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
  1462. /*
  1463. * R770 (0x302) - Input Enables Status
  1464. */
  1465. #define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */
  1466. #define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */
  1467. #define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */
  1468. #define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */
  1469. #define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */
  1470. #define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */
  1471. #define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */
  1472. #define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */
  1473. #define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */
  1474. #define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */
  1475. #define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */
  1476. #define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */
  1477. #define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */
  1478. #define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */
  1479. #define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */
  1480. #define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */
  1481. #define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */
  1482. #define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */
  1483. #define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */
  1484. #define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */
  1485. #define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */
  1486. #define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */
  1487. #define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */
  1488. #define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */
  1489. #define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */
  1490. #define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */
  1491. #define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */
  1492. #define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */
  1493. #define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */
  1494. #define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */
  1495. #define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */
  1496. #define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */
  1497. /*
  1498. * R784 (0x310) - IN1L Control
  1499. */
  1500. #define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */
  1501. #define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */
  1502. #define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */
  1503. #define WM5100_IN1_OSR 0x2000 /* IN1_OSR */
  1504. #define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */
  1505. #define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */
  1506. #define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */
  1507. #define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
  1508. #define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
  1509. #define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
  1510. #define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
  1511. #define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
  1512. #define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
  1513. #define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
  1514. #define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
  1515. #define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
  1516. /*
  1517. * R785 (0x311) - IN1R Control
  1518. */
  1519. #define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
  1520. #define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
  1521. #define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
  1522. /*
  1523. * R786 (0x312) - IN2L Control
  1524. */
  1525. #define WM5100_IN2_OSR 0x2000 /* IN2_OSR */
  1526. #define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */
  1527. #define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */
  1528. #define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */
  1529. #define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
  1530. #define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
  1531. #define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
  1532. #define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
  1533. #define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
  1534. #define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
  1535. #define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
  1536. #define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
  1537. #define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
  1538. /*
  1539. * R787 (0x313) - IN2R Control
  1540. */
  1541. #define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
  1542. #define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
  1543. #define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
  1544. /*
  1545. * R788 (0x314) - IN3L Control
  1546. */
  1547. #define WM5100_IN3_OSR 0x2000 /* IN3_OSR */
  1548. #define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */
  1549. #define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */
  1550. #define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */
  1551. #define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
  1552. #define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
  1553. #define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
  1554. #define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
  1555. #define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
  1556. #define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
  1557. #define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
  1558. #define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
  1559. #define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
  1560. /*
  1561. * R789 (0x315) - IN3R Control
  1562. */
  1563. #define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
  1564. #define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
  1565. #define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
  1566. /*
  1567. * R790 (0x316) - IN4L Control
  1568. */
  1569. #define WM5100_IN4_OSR 0x2000 /* IN4_OSR */
  1570. #define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */
  1571. #define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */
  1572. #define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */
  1573. #define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */
  1574. #define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */
  1575. #define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */
  1576. #define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */
  1577. #define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */
  1578. #define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */
  1579. #define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */
  1580. #define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */
  1581. #define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */
  1582. /*
  1583. * R791 (0x317) - IN4R Control
  1584. */
  1585. #define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */
  1586. #define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */
  1587. #define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */
  1588. /*
  1589. * R792 (0x318) - RXANC_SRC
  1590. */
  1591. #define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */
  1592. #define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */
  1593. #define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */
  1594. /*
  1595. * R793 (0x319) - Input Volume Ramp
  1596. */
  1597. #define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
  1598. #define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
  1599. #define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
  1600. #define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
  1601. #define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
  1602. #define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
  1603. /*
  1604. * R800 (0x320) - ADC Digital Volume 1L
  1605. */
  1606. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1607. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1608. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1609. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1610. #define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */
  1611. #define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
  1612. #define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
  1613. #define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
  1614. #define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */
  1615. #define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */
  1616. #define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */
  1617. /*
  1618. * R801 (0x321) - ADC Digital Volume 1R
  1619. */
  1620. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1621. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1622. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1623. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1624. #define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */
  1625. #define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
  1626. #define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
  1627. #define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
  1628. #define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */
  1629. #define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */
  1630. #define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */
  1631. /*
  1632. * R802 (0x322) - ADC Digital Volume 2L
  1633. */
  1634. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1635. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1636. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1637. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1638. #define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */
  1639. #define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
  1640. #define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
  1641. #define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
  1642. #define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */
  1643. #define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */
  1644. #define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */
  1645. /*
  1646. * R803 (0x323) - ADC Digital Volume 2R
  1647. */
  1648. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1649. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1650. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1651. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1652. #define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */
  1653. #define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
  1654. #define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
  1655. #define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
  1656. #define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */
  1657. #define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */
  1658. #define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */
  1659. /*
  1660. * R804 (0x324) - ADC Digital Volume 3L
  1661. */
  1662. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1663. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1664. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1665. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1666. #define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */
  1667. #define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
  1668. #define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
  1669. #define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
  1670. #define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */
  1671. #define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */
  1672. #define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */
  1673. /*
  1674. * R805 (0x325) - ADC Digital Volume 3R
  1675. */
  1676. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1677. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1678. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1679. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1680. #define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */
  1681. #define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
  1682. #define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
  1683. #define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
  1684. #define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */
  1685. #define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */
  1686. #define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */
  1687. /*
  1688. * R806 (0x326) - ADC Digital Volume 4L
  1689. */
  1690. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1691. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1692. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1693. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1694. #define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */
  1695. #define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */
  1696. #define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */
  1697. #define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */
  1698. #define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */
  1699. #define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */
  1700. #define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */
  1701. /*
  1702. * R807 (0x327) - ADC Digital Volume 4R
  1703. */
  1704. #define WM5100_IN_VU 0x0200 /* IN_VU */
  1705. #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */
  1706. #define WM5100_IN_VU_SHIFT 9 /* IN_VU */
  1707. #define WM5100_IN_VU_WIDTH 1 /* IN_VU */
  1708. #define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */
  1709. #define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */
  1710. #define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */
  1711. #define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */
  1712. #define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */
  1713. #define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */
  1714. #define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */
  1715. /*
  1716. * R1025 (0x401) - Output Enables 2
  1717. */
  1718. #define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */
  1719. #define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */
  1720. #define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */
  1721. #define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */
  1722. #define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */
  1723. #define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */
  1724. #define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */
  1725. #define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */
  1726. #define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */
  1727. #define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
  1728. #define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
  1729. #define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
  1730. #define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */
  1731. #define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
  1732. #define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
  1733. #define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
  1734. #define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */
  1735. #define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
  1736. #define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
  1737. #define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
  1738. #define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */
  1739. #define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
  1740. #define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
  1741. #define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
  1742. /*
  1743. * R1026 (0x402) - Output Status 1
  1744. */
  1745. #define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */
  1746. #define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */
  1747. #define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */
  1748. #define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */
  1749. #define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */
  1750. #define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */
  1751. #define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */
  1752. #define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */
  1753. #define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */
  1754. #define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */
  1755. #define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */
  1756. #define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */
  1757. #define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */
  1758. #define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */
  1759. #define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */
  1760. #define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */
  1761. #define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */
  1762. #define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */
  1763. #define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */
  1764. #define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */
  1765. #define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */
  1766. #define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */
  1767. #define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */
  1768. #define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */
  1769. /*
  1770. * R1027 (0x403) - Output Status 2
  1771. */
  1772. #define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
  1773. #define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
  1774. #define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
  1775. #define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
  1776. #define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
  1777. #define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
  1778. #define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
  1779. #define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
  1780. #define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
  1781. #define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
  1782. #define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
  1783. #define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
  1784. #define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
  1785. #define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
  1786. #define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
  1787. #define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
  1788. #define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
  1789. #define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
  1790. #define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
  1791. #define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
  1792. #define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
  1793. #define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
  1794. #define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
  1795. #define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
  1796. /*
  1797. * R1032 (0x408) - Channel Enables 1
  1798. */
  1799. #define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */
  1800. #define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */
  1801. #define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */
  1802. #define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */
  1803. #define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */
  1804. #define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */
  1805. #define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */
  1806. #define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */
  1807. #define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */
  1808. #define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */
  1809. #define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */
  1810. #define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */
  1811. #define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */
  1812. #define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */
  1813. #define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */
  1814. #define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */
  1815. #define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */
  1816. #define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */
  1817. #define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */
  1818. #define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */
  1819. #define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */
  1820. #define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */
  1821. #define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */
  1822. #define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */
  1823. /*
  1824. * R1040 (0x410) - Out Volume 1L
  1825. */
  1826. #define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */
  1827. #define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */
  1828. #define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */
  1829. #define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */
  1830. #define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
  1831. #define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
  1832. #define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
  1833. #define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */
  1834. #define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
  1835. #define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
  1836. #define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
  1837. #define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */
  1838. #define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */
  1839. #define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */
  1840. #define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */
  1841. #define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
  1842. #define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
  1843. #define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
  1844. /*
  1845. * R1041 (0x411) - Out Volume 1R
  1846. */
  1847. #define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */
  1848. #define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */
  1849. #define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */
  1850. #define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */
  1851. #define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
  1852. #define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
  1853. #define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
  1854. /*
  1855. * R1042 (0x412) - DAC Volume Limit 1L
  1856. */
  1857. #define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
  1858. #define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
  1859. #define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
  1860. /*
  1861. * R1043 (0x413) - DAC Volume Limit 1R
  1862. */
  1863. #define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
  1864. #define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
  1865. #define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
  1866. /*
  1867. * R1044 (0x414) - Out Volume 2L
  1868. */
  1869. #define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */
  1870. #define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
  1871. #define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
  1872. #define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
  1873. #define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */
  1874. #define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
  1875. #define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
  1876. #define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
  1877. #define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */
  1878. #define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */
  1879. #define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */
  1880. #define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */
  1881. #define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
  1882. #define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
  1883. #define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
  1884. /*
  1885. * R1045 (0x415) - Out Volume 2R
  1886. */
  1887. #define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */
  1888. #define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */
  1889. #define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */
  1890. #define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */
  1891. #define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
  1892. #define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
  1893. #define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
  1894. /*
  1895. * R1046 (0x416) - DAC Volume Limit 2L
  1896. */
  1897. #define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
  1898. #define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
  1899. #define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
  1900. /*
  1901. * R1047 (0x417) - DAC Volume Limit 2R
  1902. */
  1903. #define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
  1904. #define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
  1905. #define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
  1906. /*
  1907. * R1048 (0x418) - Out Volume 3L
  1908. */
  1909. #define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */
  1910. #define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
  1911. #define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
  1912. #define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
  1913. #define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */
  1914. #define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
  1915. #define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
  1916. #define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
  1917. #define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */
  1918. #define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */
  1919. #define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */
  1920. #define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */
  1921. #define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
  1922. #define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
  1923. #define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
  1924. /*
  1925. * R1049 (0x419) - Out Volume 3R
  1926. */
  1927. #define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */
  1928. #define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */
  1929. #define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */
  1930. #define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */
  1931. #define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
  1932. #define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
  1933. #define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
  1934. /*
  1935. * R1050 (0x41A) - DAC Volume Limit 3L
  1936. */
  1937. #define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
  1938. #define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
  1939. #define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
  1940. /*
  1941. * R1051 (0x41B) - DAC Volume Limit 3R
  1942. */
  1943. #define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
  1944. #define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
  1945. #define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
  1946. /*
  1947. * R1052 (0x41C) - Out Volume 4L
  1948. */
  1949. #define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */
  1950. #define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
  1951. #define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
  1952. #define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
  1953. #define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */
  1954. #define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */
  1955. #define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */
  1956. #define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */
  1957. #define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
  1958. #define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
  1959. #define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
  1960. /*
  1961. * R1053 (0x41D) - Out Volume 4R
  1962. */
  1963. #define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */
  1964. #define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */
  1965. #define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */
  1966. #define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */
  1967. #define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
  1968. #define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
  1969. #define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
  1970. /*
  1971. * R1054 (0x41E) - DAC Volume Limit 5L
  1972. */
  1973. #define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */
  1974. #define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
  1975. #define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
  1976. #define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
  1977. #define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */
  1978. #define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */
  1979. #define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */
  1980. #define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */
  1981. #define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
  1982. #define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
  1983. #define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
  1984. /*
  1985. * R1055 (0x41F) - DAC Volume Limit 5R
  1986. */
  1987. #define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */
  1988. #define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */
  1989. #define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */
  1990. #define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */
  1991. #define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
  1992. #define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
  1993. #define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
  1994. /*
  1995. * R1056 (0x420) - DAC Volume Limit 6L
  1996. */
  1997. #define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */
  1998. #define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */
  1999. #define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */
  2000. #define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */
  2001. #define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */
  2002. #define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */
  2003. #define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */
  2004. #define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */
  2005. #define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */
  2006. #define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */
  2007. #define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */
  2008. /*
  2009. * R1057 (0x421) - DAC Volume Limit 6R
  2010. */
  2011. #define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */
  2012. #define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */
  2013. #define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */
  2014. #define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */
  2015. #define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */
  2016. #define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */
  2017. #define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */
  2018. /*
  2019. * R1088 (0x440) - DAC AEC Control 1
  2020. */
  2021. #define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
  2022. #define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
  2023. #define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
  2024. #define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
  2025. #define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
  2026. #define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
  2027. #define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
  2028. #define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
  2029. #define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
  2030. #define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
  2031. #define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
  2032. /*
  2033. * R1089 (0x441) - Output Volume Ramp
  2034. */
  2035. #define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
  2036. #define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
  2037. #define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
  2038. #define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
  2039. #define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
  2040. #define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
  2041. /*
  2042. * R1152 (0x480) - DAC Digital Volume 1L
  2043. */
  2044. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2045. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2046. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2047. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2048. #define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
  2049. #define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
  2050. #define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
  2051. #define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
  2052. #define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
  2053. #define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
  2054. #define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
  2055. /*
  2056. * R1153 (0x481) - DAC Digital Volume 1R
  2057. */
  2058. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2059. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2060. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2061. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2062. #define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
  2063. #define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
  2064. #define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
  2065. #define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
  2066. #define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
  2067. #define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
  2068. #define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
  2069. /*
  2070. * R1154 (0x482) - DAC Digital Volume 2L
  2071. */
  2072. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2073. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2074. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2075. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2076. #define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
  2077. #define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
  2078. #define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
  2079. #define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
  2080. #define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
  2081. #define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
  2082. #define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
  2083. /*
  2084. * R1155 (0x483) - DAC Digital Volume 2R
  2085. */
  2086. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2087. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2088. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2089. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2090. #define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
  2091. #define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
  2092. #define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
  2093. #define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
  2094. #define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
  2095. #define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
  2096. #define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
  2097. /*
  2098. * R1156 (0x484) - DAC Digital Volume 3L
  2099. */
  2100. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2101. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2102. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2103. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2104. #define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
  2105. #define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
  2106. #define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
  2107. #define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
  2108. #define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
  2109. #define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
  2110. #define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
  2111. /*
  2112. * R1157 (0x485) - DAC Digital Volume 3R
  2113. */
  2114. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2115. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2116. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2117. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2118. #define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
  2119. #define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
  2120. #define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
  2121. #define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
  2122. #define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
  2123. #define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
  2124. #define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
  2125. /*
  2126. * R1158 (0x486) - DAC Digital Volume 4L
  2127. */
  2128. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2129. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2130. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2131. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2132. #define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
  2133. #define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
  2134. #define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
  2135. #define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
  2136. #define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
  2137. #define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
  2138. #define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
  2139. /*
  2140. * R1159 (0x487) - DAC Digital Volume 4R
  2141. */
  2142. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2143. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2144. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2145. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2146. #define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
  2147. #define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
  2148. #define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
  2149. #define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
  2150. #define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
  2151. #define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
  2152. #define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
  2153. /*
  2154. * R1160 (0x488) - DAC Digital Volume 5L
  2155. */
  2156. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2157. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2158. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2159. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2160. #define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
  2161. #define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
  2162. #define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
  2163. #define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
  2164. #define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
  2165. #define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
  2166. #define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
  2167. /*
  2168. * R1161 (0x489) - DAC Digital Volume 5R
  2169. */
  2170. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2171. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2172. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2173. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2174. #define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
  2175. #define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
  2176. #define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
  2177. #define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
  2178. #define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
  2179. #define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
  2180. #define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
  2181. /*
  2182. * R1162 (0x48A) - DAC Digital Volume 6L
  2183. */
  2184. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2185. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2186. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2187. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2188. #define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */
  2189. #define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */
  2190. #define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */
  2191. #define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */
  2192. #define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */
  2193. #define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */
  2194. #define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */
  2195. /*
  2196. * R1163 (0x48B) - DAC Digital Volume 6R
  2197. */
  2198. #define WM5100_OUT_VU 0x0200 /* OUT_VU */
  2199. #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */
  2200. #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */
  2201. #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */
  2202. #define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */
  2203. #define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */
  2204. #define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */
  2205. #define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */
  2206. #define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */
  2207. #define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */
  2208. #define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */
  2209. /*
  2210. * R1216 (0x4C0) - PDM SPK1 CTRL 1
  2211. */
  2212. #define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
  2213. #define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
  2214. #define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
  2215. #define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
  2216. #define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
  2217. #define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
  2218. #define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
  2219. #define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
  2220. #define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
  2221. #define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
  2222. #define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
  2223. #define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
  2224. #define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
  2225. #define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
  2226. #define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
  2227. /*
  2228. * R1217 (0x4C1) - PDM SPK1 CTRL 2
  2229. */
  2230. #define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */
  2231. #define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
  2232. #define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
  2233. #define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
  2234. /*
  2235. * R1218 (0x4C2) - PDM SPK2 CTRL 1
  2236. */
  2237. #define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */
  2238. #define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */
  2239. #define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */
  2240. #define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
  2241. #define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */
  2242. #define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */
  2243. #define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */
  2244. #define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
  2245. #define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */
  2246. #define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */
  2247. #define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */
  2248. #define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */
  2249. #define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
  2250. #define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
  2251. #define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
  2252. /*
  2253. * R1219 (0x4C3) - PDM SPK2 CTRL 2
  2254. */
  2255. #define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */
  2256. #define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */
  2257. #define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */
  2258. #define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */
  2259. /*
  2260. * R1280 (0x500) - Audio IF 1_1
  2261. */
  2262. #define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
  2263. #define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
  2264. #define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
  2265. #define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
  2266. #define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
  2267. #define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
  2268. #define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
  2269. #define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
  2270. #define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
  2271. #define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
  2272. #define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
  2273. #define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
  2274. #define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
  2275. #define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
  2276. #define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
  2277. /*
  2278. * R1281 (0x501) - Audio IF 1_2
  2279. */
  2280. #define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
  2281. #define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
  2282. #define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
  2283. #define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
  2284. #define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
  2285. #define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
  2286. #define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
  2287. #define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
  2288. #define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
  2289. #define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
  2290. #define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
  2291. #define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
  2292. #define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
  2293. #define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
  2294. #define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
  2295. #define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
  2296. #define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
  2297. #define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
  2298. #define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
  2299. #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
  2300. /*
  2301. * R1282 (0x502) - Audio IF 1_3
  2302. */
  2303. #define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
  2304. #define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
  2305. #define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
  2306. #define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
  2307. #define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
  2308. #define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
  2309. #define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
  2310. #define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
  2311. #define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
  2312. #define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
  2313. #define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
  2314. #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
  2315. /*
  2316. * R1283 (0x503) - Audio IF 1_4
  2317. */
  2318. #define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */
  2319. #define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
  2320. #define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
  2321. #define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
  2322. #define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */
  2323. #define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */
  2324. #define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */
  2325. /*
  2326. * R1284 (0x504) - Audio IF 1_5
  2327. */
  2328. #define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
  2329. #define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
  2330. #define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
  2331. /*
  2332. * R1285 (0x505) - Audio IF 1_6
  2333. */
  2334. #define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
  2335. #define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
  2336. #define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
  2337. /*
  2338. * R1286 (0x506) - Audio IF 1_7
  2339. */
  2340. #define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
  2341. #define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
  2342. #define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
  2343. /*
  2344. * R1287 (0x507) - Audio IF 1_8
  2345. */
  2346. #define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
  2347. #define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
  2348. #define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
  2349. #define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
  2350. #define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
  2351. #define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
  2352. /*
  2353. * R1288 (0x508) - Audio IF 1_9
  2354. */
  2355. #define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
  2356. #define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
  2357. #define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
  2358. #define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
  2359. #define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
  2360. #define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
  2361. /*
  2362. * R1289 (0x509) - Audio IF 1_10
  2363. */
  2364. #define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
  2365. #define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
  2366. #define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
  2367. /*
  2368. * R1290 (0x50A) - Audio IF 1_11
  2369. */
  2370. #define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
  2371. #define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
  2372. #define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
  2373. /*
  2374. * R1291 (0x50B) - Audio IF 1_12
  2375. */
  2376. #define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
  2377. #define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
  2378. #define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
  2379. /*
  2380. * R1292 (0x50C) - Audio IF 1_13
  2381. */
  2382. #define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
  2383. #define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
  2384. #define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
  2385. /*
  2386. * R1293 (0x50D) - Audio IF 1_14
  2387. */
  2388. #define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
  2389. #define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
  2390. #define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
  2391. /*
  2392. * R1294 (0x50E) - Audio IF 1_15
  2393. */
  2394. #define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
  2395. #define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
  2396. #define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
  2397. /*
  2398. * R1295 (0x50F) - Audio IF 1_16
  2399. */
  2400. #define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
  2401. #define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
  2402. #define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
  2403. /*
  2404. * R1296 (0x510) - Audio IF 1_17
  2405. */
  2406. #define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
  2407. #define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
  2408. #define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
  2409. /*
  2410. * R1297 (0x511) - Audio IF 1_18
  2411. */
  2412. #define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
  2413. #define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
  2414. #define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
  2415. /*
  2416. * R1298 (0x512) - Audio IF 1_19
  2417. */
  2418. #define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
  2419. #define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
  2420. #define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
  2421. /*
  2422. * R1299 (0x513) - Audio IF 1_20
  2423. */
  2424. #define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
  2425. #define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
  2426. #define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
  2427. /*
  2428. * R1300 (0x514) - Audio IF 1_21
  2429. */
  2430. #define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
  2431. #define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
  2432. #define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
  2433. /*
  2434. * R1301 (0x515) - Audio IF 1_22
  2435. */
  2436. #define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
  2437. #define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
  2438. #define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
  2439. /*
  2440. * R1302 (0x516) - Audio IF 1_23
  2441. */
  2442. #define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
  2443. #define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
  2444. #define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
  2445. /*
  2446. * R1303 (0x517) - Audio IF 1_24
  2447. */
  2448. #define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
  2449. #define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
  2450. #define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
  2451. /*
  2452. * R1304 (0x518) - Audio IF 1_25
  2453. */
  2454. #define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
  2455. #define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
  2456. #define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
  2457. /*
  2458. * R1305 (0x519) - Audio IF 1_26
  2459. */
  2460. #define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
  2461. #define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
  2462. #define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
  2463. #define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
  2464. #define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
  2465. #define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
  2466. #define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
  2467. #define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
  2468. #define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
  2469. #define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
  2470. #define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
  2471. #define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
  2472. #define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
  2473. #define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
  2474. #define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
  2475. #define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
  2476. #define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
  2477. #define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
  2478. #define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
  2479. #define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
  2480. #define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
  2481. #define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
  2482. #define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
  2483. #define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
  2484. #define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
  2485. #define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
  2486. #define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
  2487. #define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
  2488. #define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
  2489. #define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
  2490. #define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
  2491. #define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
  2492. /*
  2493. * R1306 (0x51A) - Audio IF 1_27
  2494. */
  2495. #define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
  2496. #define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
  2497. #define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
  2498. #define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
  2499. #define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
  2500. #define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
  2501. #define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
  2502. #define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
  2503. #define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
  2504. #define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
  2505. #define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
  2506. #define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
  2507. #define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
  2508. #define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
  2509. #define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
  2510. #define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
  2511. #define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
  2512. #define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
  2513. #define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
  2514. #define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
  2515. #define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
  2516. #define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
  2517. #define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
  2518. #define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
  2519. #define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
  2520. #define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
  2521. #define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
  2522. #define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
  2523. #define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
  2524. #define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
  2525. #define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
  2526. #define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
  2527. /*
  2528. * R1344 (0x540) - Audio IF 2_1
  2529. */
  2530. #define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
  2531. #define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
  2532. #define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
  2533. #define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
  2534. #define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
  2535. #define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
  2536. #define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
  2537. #define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
  2538. #define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
  2539. #define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
  2540. #define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
  2541. #define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
  2542. #define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
  2543. #define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
  2544. #define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
  2545. /*
  2546. * R1345 (0x541) - Audio IF 2_2
  2547. */
  2548. #define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
  2549. #define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
  2550. #define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
  2551. #define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
  2552. #define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
  2553. #define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
  2554. #define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
  2555. #define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
  2556. #define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
  2557. #define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
  2558. #define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
  2559. #define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
  2560. #define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
  2561. #define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
  2562. #define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
  2563. #define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
  2564. #define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
  2565. #define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
  2566. #define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
  2567. #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
  2568. /*
  2569. * R1346 (0x542) - Audio IF 2_3
  2570. */
  2571. #define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
  2572. #define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
  2573. #define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
  2574. #define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
  2575. #define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
  2576. #define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
  2577. #define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
  2578. #define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
  2579. #define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
  2580. #define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
  2581. #define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
  2582. #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
  2583. /*
  2584. * R1347 (0x543) - Audio IF 2_4
  2585. */
  2586. #define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */
  2587. #define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
  2588. #define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
  2589. #define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
  2590. #define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */
  2591. #define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */
  2592. #define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */
  2593. /*
  2594. * R1348 (0x544) - Audio IF 2_5
  2595. */
  2596. #define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
  2597. #define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
  2598. #define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
  2599. /*
  2600. * R1349 (0x545) - Audio IF 2_6
  2601. */
  2602. #define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
  2603. #define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
  2604. #define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
  2605. /*
  2606. * R1350 (0x546) - Audio IF 2_7
  2607. */
  2608. #define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
  2609. #define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
  2610. #define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
  2611. /*
  2612. * R1351 (0x547) - Audio IF 2_8
  2613. */
  2614. #define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
  2615. #define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
  2616. #define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
  2617. #define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
  2618. #define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
  2619. #define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
  2620. /*
  2621. * R1352 (0x548) - Audio IF 2_9
  2622. */
  2623. #define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
  2624. #define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
  2625. #define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
  2626. #define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
  2627. #define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
  2628. #define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
  2629. /*
  2630. * R1353 (0x549) - Audio IF 2_10
  2631. */
  2632. #define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
  2633. #define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
  2634. #define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
  2635. /*
  2636. * R1354 (0x54A) - Audio IF 2_11
  2637. */
  2638. #define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
  2639. #define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
  2640. #define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
  2641. /*
  2642. * R1361 (0x551) - Audio IF 2_18
  2643. */
  2644. #define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
  2645. #define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
  2646. #define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
  2647. /*
  2648. * R1362 (0x552) - Audio IF 2_19
  2649. */
  2650. #define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
  2651. #define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
  2652. #define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
  2653. /*
  2654. * R1369 (0x559) - Audio IF 2_26
  2655. */
  2656. #define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
  2657. #define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
  2658. #define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
  2659. #define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
  2660. #define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
  2661. #define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
  2662. #define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
  2663. #define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
  2664. /*
  2665. * R1370 (0x55A) - Audio IF 2_27
  2666. */
  2667. #define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
  2668. #define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
  2669. #define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
  2670. #define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
  2671. #define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
  2672. #define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
  2673. #define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
  2674. #define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
  2675. /*
  2676. * R1408 (0x580) - Audio IF 3_1
  2677. */
  2678. #define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
  2679. #define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
  2680. #define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
  2681. #define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
  2682. #define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
  2683. #define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
  2684. #define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
  2685. #define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
  2686. #define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
  2687. #define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
  2688. #define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
  2689. #define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
  2690. #define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
  2691. #define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
  2692. #define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
  2693. /*
  2694. * R1409 (0x581) - Audio IF 3_2
  2695. */
  2696. #define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
  2697. #define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
  2698. #define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
  2699. #define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
  2700. #define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
  2701. #define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
  2702. #define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
  2703. #define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
  2704. #define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
  2705. #define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
  2706. #define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
  2707. #define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
  2708. #define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
  2709. #define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
  2710. #define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
  2711. #define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
  2712. #define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
  2713. #define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
  2714. #define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
  2715. #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
  2716. /*
  2717. * R1410 (0x582) - Audio IF 3_3
  2718. */
  2719. #define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
  2720. #define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
  2721. #define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
  2722. #define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
  2723. #define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
  2724. #define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
  2725. #define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
  2726. #define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
  2727. #define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
  2728. #define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
  2729. #define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
  2730. #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
  2731. /*
  2732. * R1411 (0x583) - Audio IF 3_4
  2733. */
  2734. #define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */
  2735. #define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
  2736. #define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
  2737. #define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
  2738. #define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */
  2739. #define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */
  2740. #define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */
  2741. /*
  2742. * R1412 (0x584) - Audio IF 3_5
  2743. */
  2744. #define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
  2745. #define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
  2746. #define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
  2747. /*
  2748. * R1413 (0x585) - Audio IF 3_6
  2749. */
  2750. #define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
  2751. #define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
  2752. #define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
  2753. /*
  2754. * R1414 (0x586) - Audio IF 3_7
  2755. */
  2756. #define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
  2757. #define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
  2758. #define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
  2759. /*
  2760. * R1415 (0x587) - Audio IF 3_8
  2761. */
  2762. #define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
  2763. #define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
  2764. #define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
  2765. #define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
  2766. #define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
  2767. #define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
  2768. /*
  2769. * R1416 (0x588) - Audio IF 3_9
  2770. */
  2771. #define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
  2772. #define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
  2773. #define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
  2774. #define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
  2775. #define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
  2776. #define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
  2777. /*
  2778. * R1417 (0x589) - Audio IF 3_10
  2779. */
  2780. #define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
  2781. #define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
  2782. #define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
  2783. /*
  2784. * R1418 (0x58A) - Audio IF 3_11
  2785. */
  2786. #define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
  2787. #define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
  2788. #define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
  2789. /*
  2790. * R1425 (0x591) - Audio IF 3_18
  2791. */
  2792. #define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
  2793. #define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
  2794. #define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
  2795. /*
  2796. * R1426 (0x592) - Audio IF 3_19
  2797. */
  2798. #define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
  2799. #define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
  2800. #define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
  2801. /*
  2802. * R1433 (0x599) - Audio IF 3_26
  2803. */
  2804. #define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
  2805. #define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
  2806. #define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
  2807. #define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
  2808. #define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
  2809. #define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
  2810. #define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
  2811. #define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
  2812. /*
  2813. * R1434 (0x59A) - Audio IF 3_27
  2814. */
  2815. #define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
  2816. #define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
  2817. #define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
  2818. #define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
  2819. #define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
  2820. #define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
  2821. #define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
  2822. #define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
  2823. #define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */
  2824. #define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */
  2825. #define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */
  2826. /*
  2827. * R3072 (0xC00) - GPIO CTRL 1
  2828. */
  2829. #define WM5100_GP1_DIR 0x8000 /* GP1_DIR */
  2830. #define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */
  2831. #define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */
  2832. #define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */
  2833. #define WM5100_GP1_PU 0x4000 /* GP1_PU */
  2834. #define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */
  2835. #define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */
  2836. #define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */
  2837. #define WM5100_GP1_PD 0x2000 /* GP1_PD */
  2838. #define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */
  2839. #define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */
  2840. #define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */
  2841. #define WM5100_GP1_POL 0x0400 /* GP1_POL */
  2842. #define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */
  2843. #define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */
  2844. #define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */
  2845. #define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
  2846. #define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
  2847. #define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
  2848. #define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
  2849. #define WM5100_GP1_DB 0x0100 /* GP1_DB */
  2850. #define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */
  2851. #define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */
  2852. #define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */
  2853. #define WM5100_GP1_LVL 0x0040 /* GP1_LVL */
  2854. #define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */
  2855. #define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */
  2856. #define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */
  2857. #define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */
  2858. #define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */
  2859. #define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */
  2860. /*
  2861. * R3073 (0xC01) - GPIO CTRL 2
  2862. */
  2863. #define WM5100_GP2_DIR 0x8000 /* GP2_DIR */
  2864. #define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */
  2865. #define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */
  2866. #define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */
  2867. #define WM5100_GP2_PU 0x4000 /* GP2_PU */
  2868. #define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */
  2869. #define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */
  2870. #define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */
  2871. #define WM5100_GP2_PD 0x2000 /* GP2_PD */
  2872. #define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */
  2873. #define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */
  2874. #define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */
  2875. #define WM5100_GP2_POL 0x0400 /* GP2_POL */
  2876. #define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */
  2877. #define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */
  2878. #define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */
  2879. #define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
  2880. #define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
  2881. #define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
  2882. #define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
  2883. #define WM5100_GP2_DB 0x0100 /* GP2_DB */
  2884. #define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */
  2885. #define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */
  2886. #define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */
  2887. #define WM5100_GP2_LVL 0x0040 /* GP2_LVL */
  2888. #define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */
  2889. #define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */
  2890. #define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */
  2891. #define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */
  2892. #define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */
  2893. #define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */
  2894. /*
  2895. * R3074 (0xC02) - GPIO CTRL 3
  2896. */
  2897. #define WM5100_GP3_DIR 0x8000 /* GP3_DIR */
  2898. #define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */
  2899. #define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */
  2900. #define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */
  2901. #define WM5100_GP3_PU 0x4000 /* GP3_PU */
  2902. #define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */
  2903. #define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */
  2904. #define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */
  2905. #define WM5100_GP3_PD 0x2000 /* GP3_PD */
  2906. #define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */
  2907. #define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */
  2908. #define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */
  2909. #define WM5100_GP3_POL 0x0400 /* GP3_POL */
  2910. #define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */
  2911. #define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */
  2912. #define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */
  2913. #define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
  2914. #define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
  2915. #define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
  2916. #define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
  2917. #define WM5100_GP3_DB 0x0100 /* GP3_DB */
  2918. #define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */
  2919. #define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */
  2920. #define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */
  2921. #define WM5100_GP3_LVL 0x0040 /* GP3_LVL */
  2922. #define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */
  2923. #define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */
  2924. #define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */
  2925. #define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */
  2926. #define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */
  2927. #define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */
  2928. /*
  2929. * R3075 (0xC03) - GPIO CTRL 4
  2930. */
  2931. #define WM5100_GP4_DIR 0x8000 /* GP4_DIR */
  2932. #define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */
  2933. #define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */
  2934. #define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */
  2935. #define WM5100_GP4_PU 0x4000 /* GP4_PU */
  2936. #define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */
  2937. #define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */
  2938. #define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */
  2939. #define WM5100_GP4_PD 0x2000 /* GP4_PD */
  2940. #define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */
  2941. #define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */
  2942. #define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */
  2943. #define WM5100_GP4_POL 0x0400 /* GP4_POL */
  2944. #define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */
  2945. #define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */
  2946. #define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */
  2947. #define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
  2948. #define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
  2949. #define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
  2950. #define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
  2951. #define WM5100_GP4_DB 0x0100 /* GP4_DB */
  2952. #define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */
  2953. #define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */
  2954. #define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */
  2955. #define WM5100_GP4_LVL 0x0040 /* GP4_LVL */
  2956. #define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */
  2957. #define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */
  2958. #define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */
  2959. #define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */
  2960. #define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */
  2961. #define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */
  2962. /*
  2963. * R3076 (0xC04) - GPIO CTRL 5
  2964. */
  2965. #define WM5100_GP5_DIR 0x8000 /* GP5_DIR */
  2966. #define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */
  2967. #define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */
  2968. #define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */
  2969. #define WM5100_GP5_PU 0x4000 /* GP5_PU */
  2970. #define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */
  2971. #define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */
  2972. #define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */
  2973. #define WM5100_GP5_PD 0x2000 /* GP5_PD */
  2974. #define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */
  2975. #define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */
  2976. #define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */
  2977. #define WM5100_GP5_POL 0x0400 /* GP5_POL */
  2978. #define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */
  2979. #define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */
  2980. #define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */
  2981. #define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
  2982. #define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
  2983. #define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
  2984. #define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
  2985. #define WM5100_GP5_DB 0x0100 /* GP5_DB */
  2986. #define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */
  2987. #define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */
  2988. #define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */
  2989. #define WM5100_GP5_LVL 0x0040 /* GP5_LVL */
  2990. #define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */
  2991. #define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */
  2992. #define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */
  2993. #define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */
  2994. #define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */
  2995. #define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */
  2996. /*
  2997. * R3077 (0xC05) - GPIO CTRL 6
  2998. */
  2999. #define WM5100_GP6_DIR 0x8000 /* GP6_DIR */
  3000. #define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */
  3001. #define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */
  3002. #define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */
  3003. #define WM5100_GP6_PU 0x4000 /* GP6_PU */
  3004. #define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */
  3005. #define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */
  3006. #define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */
  3007. #define WM5100_GP6_PD 0x2000 /* GP6_PD */
  3008. #define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */
  3009. #define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */
  3010. #define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */
  3011. #define WM5100_GP6_POL 0x0400 /* GP6_POL */
  3012. #define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */
  3013. #define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */
  3014. #define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */
  3015. #define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
  3016. #define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
  3017. #define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
  3018. #define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
  3019. #define WM5100_GP6_DB 0x0100 /* GP6_DB */
  3020. #define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */
  3021. #define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */
  3022. #define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */
  3023. #define WM5100_GP6_LVL 0x0040 /* GP6_LVL */
  3024. #define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */
  3025. #define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */
  3026. #define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */
  3027. #define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */
  3028. #define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */
  3029. #define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */
  3030. /*
  3031. * R3107 (0xC23) - Misc Pad Ctrl 1
  3032. */
  3033. #define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
  3034. #define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
  3035. #define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
  3036. #define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
  3037. #define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */
  3038. #define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
  3039. #define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
  3040. #define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
  3041. #define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */
  3042. #define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
  3043. #define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
  3044. #define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
  3045. #define WM5100_RESET_PU 0x0002 /* RESET_PU */
  3046. #define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */
  3047. #define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */
  3048. #define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */
  3049. #define WM5100_ADDR_PD 0x0001 /* ADDR_PD */
  3050. #define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */
  3051. #define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */
  3052. #define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */
  3053. /*
  3054. * R3108 (0xC24) - Misc Pad Ctrl 2
  3055. */
  3056. #define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
  3057. #define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
  3058. #define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
  3059. #define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
  3060. #define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
  3061. #define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
  3062. #define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
  3063. #define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
  3064. #define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
  3065. #define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
  3066. #define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
  3067. #define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
  3068. #define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
  3069. #define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
  3070. #define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
  3071. #define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
  3072. /*
  3073. * R3109 (0xC25) - Misc Pad Ctrl 3
  3074. */
  3075. #define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
  3076. #define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
  3077. #define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
  3078. #define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
  3079. #define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
  3080. #define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
  3081. #define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
  3082. #define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
  3083. #define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
  3084. #define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
  3085. #define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
  3086. #define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
  3087. #define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
  3088. #define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
  3089. #define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
  3090. #define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
  3091. #define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
  3092. #define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
  3093. #define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
  3094. #define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
  3095. #define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
  3096. #define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
  3097. #define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
  3098. #define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
  3099. /*
  3100. * R3110 (0xC26) - Misc Pad Ctrl 4
  3101. */
  3102. #define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
  3103. #define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
  3104. #define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
  3105. #define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
  3106. #define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
  3107. #define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
  3108. #define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
  3109. #define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
  3110. #define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
  3111. #define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
  3112. #define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
  3113. #define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
  3114. #define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
  3115. #define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
  3116. #define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
  3117. #define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
  3118. #define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
  3119. #define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
  3120. #define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
  3121. #define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
  3122. #define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
  3123. #define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
  3124. #define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
  3125. #define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
  3126. /*
  3127. * R3111 (0xC27) - Misc Pad Ctrl 5
  3128. */
  3129. #define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
  3130. #define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
  3131. #define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
  3132. #define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
  3133. #define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
  3134. #define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
  3135. #define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
  3136. #define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
  3137. #define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
  3138. #define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
  3139. #define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
  3140. #define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
  3141. #define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
  3142. #define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
  3143. #define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
  3144. #define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
  3145. #define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
  3146. #define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
  3147. #define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
  3148. #define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
  3149. #define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
  3150. #define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
  3151. #define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
  3152. #define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
  3153. /*
  3154. * R3112 (0xC28) - Misc GPIO 1
  3155. */
  3156. #define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */
  3157. #define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */
  3158. #define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */
  3159. /*
  3160. * R3328 (0xD00) - Interrupt Status 1
  3161. */
  3162. #define WM5100_GP6_EINT 0x0020 /* GP6_EINT */
  3163. #define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */
  3164. #define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */
  3165. #define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */
  3166. #define WM5100_GP5_EINT 0x0010 /* GP5_EINT */
  3167. #define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */
  3168. #define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */
  3169. #define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */
  3170. #define WM5100_GP4_EINT 0x0008 /* GP4_EINT */
  3171. #define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */
  3172. #define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */
  3173. #define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */
  3174. #define WM5100_GP3_EINT 0x0004 /* GP3_EINT */
  3175. #define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */
  3176. #define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */
  3177. #define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */
  3178. #define WM5100_GP2_EINT 0x0002 /* GP2_EINT */
  3179. #define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */
  3180. #define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */
  3181. #define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */
  3182. #define WM5100_GP1_EINT 0x0001 /* GP1_EINT */
  3183. #define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */
  3184. #define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */
  3185. #define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */
  3186. /*
  3187. * R3329 (0xD01) - Interrupt Status 2
  3188. */
  3189. #define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */
  3190. #define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */
  3191. #define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */
  3192. #define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */
  3193. #define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */
  3194. #define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */
  3195. #define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */
  3196. #define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */
  3197. #define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */
  3198. #define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */
  3199. #define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */
  3200. #define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */
  3201. #define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */
  3202. #define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */
  3203. #define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */
  3204. #define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */
  3205. #define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */
  3206. #define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */
  3207. #define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */
  3208. #define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */
  3209. #define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */
  3210. #define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */
  3211. #define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */
  3212. #define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */
  3213. /*
  3214. * R3330 (0xD02) - Interrupt Status 3
  3215. */
  3216. #define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */
  3217. #define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */
  3218. #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */
  3219. #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */
  3220. #define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */
  3221. #define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */
  3222. #define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */
  3223. #define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */
  3224. #define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */
  3225. #define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */
  3226. #define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */
  3227. #define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */
  3228. #define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */
  3229. #define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */
  3230. #define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */
  3231. #define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */
  3232. #define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */
  3233. #define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */
  3234. #define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */
  3235. #define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */
  3236. #define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */
  3237. #define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */
  3238. #define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */
  3239. #define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */
  3240. #define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */
  3241. #define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */
  3242. #define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */
  3243. #define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */
  3244. #define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */
  3245. #define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */
  3246. #define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */
  3247. #define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
  3248. #define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */
  3249. #define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */
  3250. #define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */
  3251. #define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
  3252. #define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */
  3253. #define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */
  3254. #define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */
  3255. #define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */
  3256. #define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */
  3257. #define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */
  3258. #define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */
  3259. #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */
  3260. /*
  3261. * R3331 (0xD03) - Interrupt Status 4
  3262. */
  3263. #define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */
  3264. #define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */
  3265. #define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */
  3266. #define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */
  3267. #define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */
  3268. #define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */
  3269. #define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */
  3270. #define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */
  3271. #define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */
  3272. #define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */
  3273. #define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */
  3274. #define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */
  3275. #define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */
  3276. #define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */
  3277. #define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */
  3278. #define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */
  3279. #define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */
  3280. #define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */
  3281. #define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */
  3282. #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */
  3283. #define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */
  3284. #define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */
  3285. #define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */
  3286. #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */
  3287. #define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */
  3288. #define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */
  3289. #define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */
  3290. #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */
  3291. #define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */
  3292. #define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */
  3293. #define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */
  3294. #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */
  3295. #define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */
  3296. #define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */
  3297. #define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */
  3298. #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */
  3299. #define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */
  3300. #define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */
  3301. #define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */
  3302. #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */
  3303. #define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */
  3304. #define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */
  3305. #define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */
  3306. #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */
  3307. #define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */
  3308. #define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */
  3309. #define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */
  3310. #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */
  3311. #define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */
  3312. #define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */
  3313. #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */
  3314. #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */
  3315. #define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */
  3316. #define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */
  3317. #define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */
  3318. #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */
  3319. /*
  3320. * R3332 (0xD04) - Interrupt Raw Status 2
  3321. */
  3322. #define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */
  3323. #define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */
  3324. #define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */
  3325. #define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */
  3326. #define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */
  3327. #define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */
  3328. #define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */
  3329. #define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */
  3330. #define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */
  3331. #define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */
  3332. #define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */
  3333. #define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */
  3334. #define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */
  3335. #define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */
  3336. #define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */
  3337. #define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */
  3338. #define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
  3339. #define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
  3340. #define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
  3341. #define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
  3342. #define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
  3343. #define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
  3344. #define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
  3345. #define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
  3346. /*
  3347. * R3333 (0xD05) - Interrupt Raw Status 3
  3348. */
  3349. #define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  3350. #define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  3351. #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
  3352. #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
  3353. #define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
  3354. #define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
  3355. #define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
  3356. #define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
  3357. #define WM5100_HPDET_STS 0x2000 /* HPDET_STS */
  3358. #define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */
  3359. #define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */
  3360. #define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */
  3361. #define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */
  3362. #define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */
  3363. #define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */
  3364. #define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */
  3365. #define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
  3366. #define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
  3367. #define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
  3368. #define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
  3369. #define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
  3370. #define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
  3371. #define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
  3372. #define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
  3373. #define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
  3374. #define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
  3375. #define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
  3376. #define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
  3377. #define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
  3378. #define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
  3379. #define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
  3380. #define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
  3381. #define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
  3382. #define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
  3383. #define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
  3384. #define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
  3385. #define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  3386. #define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  3387. #define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
  3388. #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
  3389. /*
  3390. * R3334 (0xD06) - Interrupt Raw Status 4
  3391. */
  3392. #define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */
  3393. #define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */
  3394. #define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */
  3395. #define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
  3396. #define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */
  3397. #define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */
  3398. #define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */
  3399. #define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
  3400. #define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */
  3401. #define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */
  3402. #define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */
  3403. #define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
  3404. #define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */
  3405. #define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */
  3406. #define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */
  3407. #define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
  3408. #define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */
  3409. #define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */
  3410. #define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */
  3411. #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
  3412. #define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */
  3413. #define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */
  3414. #define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */
  3415. #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
  3416. #define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */
  3417. #define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */
  3418. #define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */
  3419. #define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
  3420. #define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */
  3421. #define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */
  3422. #define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */
  3423. #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
  3424. #define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */
  3425. #define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */
  3426. #define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */
  3427. #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
  3428. #define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */
  3429. #define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */
  3430. #define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */
  3431. #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
  3432. #define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
  3433. #define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
  3434. #define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
  3435. #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
  3436. #define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
  3437. #define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
  3438. #define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
  3439. #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
  3440. #define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
  3441. #define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
  3442. #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
  3443. #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
  3444. #define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
  3445. #define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
  3446. #define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
  3447. #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
  3448. /*
  3449. * R3335 (0xD07) - Interrupt Status 1 Mask
  3450. */
  3451. #define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
  3452. #define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
  3453. #define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
  3454. #define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
  3455. #define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
  3456. #define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
  3457. #define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
  3458. #define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
  3459. #define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
  3460. #define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
  3461. #define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
  3462. #define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
  3463. #define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
  3464. #define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
  3465. #define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
  3466. #define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
  3467. #define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
  3468. #define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
  3469. #define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
  3470. #define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
  3471. #define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
  3472. #define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
  3473. #define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
  3474. #define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
  3475. /*
  3476. * R3336 (0xD08) - Interrupt Status 2 Mask
  3477. */
  3478. #define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */
  3479. #define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */
  3480. #define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */
  3481. #define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */
  3482. #define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */
  3483. #define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */
  3484. #define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */
  3485. #define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */
  3486. #define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */
  3487. #define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */
  3488. #define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */
  3489. #define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */
  3490. #define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */
  3491. #define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */
  3492. #define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */
  3493. #define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */
  3494. #define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */
  3495. #define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */
  3496. #define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */
  3497. #define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */
  3498. #define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */
  3499. #define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */
  3500. #define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */
  3501. #define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */
  3502. /*
  3503. * R3337 (0xD09) - Interrupt Status 3 Mask
  3504. */
  3505. #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */
  3506. #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */
  3507. #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */
  3508. #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */
  3509. #define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */
  3510. #define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */
  3511. #define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */
  3512. #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */
  3513. #define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */
  3514. #define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */
  3515. #define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */
  3516. #define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */
  3517. #define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */
  3518. #define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */
  3519. #define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */
  3520. #define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */
  3521. #define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */
  3522. #define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */
  3523. #define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */
  3524. #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */
  3525. #define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */
  3526. #define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */
  3527. #define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */
  3528. #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */
  3529. #define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */
  3530. #define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */
  3531. #define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */
  3532. #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */
  3533. #define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */
  3534. #define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */
  3535. #define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */
  3536. #define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
  3537. #define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */
  3538. #define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */
  3539. #define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */
  3540. #define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
  3541. #define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */
  3542. #define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */
  3543. #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */
  3544. #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */
  3545. #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */
  3546. #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */
  3547. #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */
  3548. #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */
  3549. /*
  3550. * R3338 (0xD0A) - Interrupt Status 4 Mask
  3551. */
  3552. #define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */
  3553. #define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */
  3554. #define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */
  3555. #define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */
  3556. #define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */
  3557. #define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */
  3558. #define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */
  3559. #define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */
  3560. #define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */
  3561. #define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */
  3562. #define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */
  3563. #define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */
  3564. #define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */
  3565. #define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */
  3566. #define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */
  3567. #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */
  3568. #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */
  3569. #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */
  3570. #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */
  3571. #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */
  3572. #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */
  3573. #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */
  3574. #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */
  3575. #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */
  3576. #define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */
  3577. #define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */
  3578. #define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */
  3579. #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */
  3580. #define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */
  3581. #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */
  3582. #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */
  3583. #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */
  3584. #define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */
  3585. #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */
  3586. #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */
  3587. #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */
  3588. #define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */
  3589. #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */
  3590. #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */
  3591. #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */
  3592. #define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */
  3593. #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */
  3594. #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */
  3595. #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */
  3596. #define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */
  3597. #define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */
  3598. #define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */
  3599. #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */
  3600. #define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */
  3601. #define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */
  3602. #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */
  3603. #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */
  3604. #define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */
  3605. #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */
  3606. #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */
  3607. #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */
  3608. /*
  3609. * R3359 (0xD1F) - Interrupt Control
  3610. */
  3611. #define WM5100_IM_IRQ 0x0001 /* IM_IRQ */
  3612. #define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */
  3613. #define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */
  3614. #define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */
  3615. /*
  3616. * R3360 (0xD20) - IRQ Debounce 1
  3617. */
  3618. #define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */
  3619. #define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */
  3620. #define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */
  3621. #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */
  3622. #define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */
  3623. #define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */
  3624. #define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */
  3625. #define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */
  3626. #define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */
  3627. #define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */
  3628. #define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */
  3629. #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */
  3630. #define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */
  3631. #define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */
  3632. #define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */
  3633. #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */
  3634. #define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */
  3635. #define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */
  3636. #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */
  3637. #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */
  3638. #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */
  3639. #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */
  3640. #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */
  3641. #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */
  3642. /*
  3643. * R3361 (0xD21) - IRQ Debounce 2
  3644. */
  3645. #define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */
  3646. #define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */
  3647. #define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */
  3648. #define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */
  3649. /*
  3650. * R3584 (0xE00) - FX_Ctrl
  3651. */
  3652. #define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */
  3653. #define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */
  3654. #define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */
  3655. #define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */
  3656. #define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */
  3657. #define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */
  3658. /*
  3659. * R3600 (0xE10) - EQ1_1
  3660. */
  3661. #define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
  3662. #define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
  3663. #define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
  3664. #define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
  3665. #define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
  3666. #define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
  3667. #define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
  3668. #define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
  3669. #define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
  3670. #define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */
  3671. #define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
  3672. #define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
  3673. #define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
  3674. /*
  3675. * R3601 (0xE11) - EQ1_2
  3676. */
  3677. #define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
  3678. #define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
  3679. #define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
  3680. #define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
  3681. #define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
  3682. #define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
  3683. /*
  3684. * R3602 (0xE12) - EQ1_3
  3685. */
  3686. #define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
  3687. #define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
  3688. #define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
  3689. /*
  3690. * R3603 (0xE13) - EQ1_4
  3691. */
  3692. #define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
  3693. #define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
  3694. #define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
  3695. /*
  3696. * R3604 (0xE14) - EQ1_5
  3697. */
  3698. #define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
  3699. #define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
  3700. #define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
  3701. /*
  3702. * R3605 (0xE15) - EQ1_6
  3703. */
  3704. #define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
  3705. #define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
  3706. #define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
  3707. /*
  3708. * R3606 (0xE16) - EQ1_7
  3709. */
  3710. #define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
  3711. #define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
  3712. #define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
  3713. /*
  3714. * R3607 (0xE17) - EQ1_8
  3715. */
  3716. #define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
  3717. #define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
  3718. #define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
  3719. /*
  3720. * R3608 (0xE18) - EQ1_9
  3721. */
  3722. #define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
  3723. #define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
  3724. #define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
  3725. /*
  3726. * R3609 (0xE19) - EQ1_10
  3727. */
  3728. #define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
  3729. #define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
  3730. #define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
  3731. /*
  3732. * R3610 (0xE1A) - EQ1_11
  3733. */
  3734. #define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
  3735. #define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
  3736. #define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
  3737. /*
  3738. * R3611 (0xE1B) - EQ1_12
  3739. */
  3740. #define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
  3741. #define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
  3742. #define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
  3743. /*
  3744. * R3612 (0xE1C) - EQ1_13
  3745. */
  3746. #define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
  3747. #define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
  3748. #define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
  3749. /*
  3750. * R3613 (0xE1D) - EQ1_14
  3751. */
  3752. #define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
  3753. #define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
  3754. #define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
  3755. /*
  3756. * R3614 (0xE1E) - EQ1_15
  3757. */
  3758. #define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
  3759. #define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
  3760. #define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
  3761. /*
  3762. * R3615 (0xE1F) - EQ1_16
  3763. */
  3764. #define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
  3765. #define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
  3766. #define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
  3767. /*
  3768. * R3616 (0xE20) - EQ1_17
  3769. */
  3770. #define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
  3771. #define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
  3772. #define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
  3773. /*
  3774. * R3617 (0xE21) - EQ1_18
  3775. */
  3776. #define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
  3777. #define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
  3778. #define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
  3779. /*
  3780. * R3618 (0xE22) - EQ1_19
  3781. */
  3782. #define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
  3783. #define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
  3784. #define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
  3785. /*
  3786. * R3619 (0xE23) - EQ1_20
  3787. */
  3788. #define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
  3789. #define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
  3790. #define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
  3791. /*
  3792. * R3622 (0xE26) - EQ2_1
  3793. */
  3794. #define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
  3795. #define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
  3796. #define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
  3797. #define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
  3798. #define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
  3799. #define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
  3800. #define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
  3801. #define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
  3802. #define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
  3803. #define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */
  3804. #define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
  3805. #define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
  3806. #define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
  3807. /*
  3808. * R3623 (0xE27) - EQ2_2
  3809. */
  3810. #define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
  3811. #define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
  3812. #define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
  3813. #define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
  3814. #define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
  3815. #define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
  3816. /*
  3817. * R3624 (0xE28) - EQ2_3
  3818. */
  3819. #define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
  3820. #define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
  3821. #define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
  3822. /*
  3823. * R3625 (0xE29) - EQ2_4
  3824. */
  3825. #define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
  3826. #define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
  3827. #define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
  3828. /*
  3829. * R3626 (0xE2A) - EQ2_5
  3830. */
  3831. #define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
  3832. #define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
  3833. #define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
  3834. /*
  3835. * R3627 (0xE2B) - EQ2_6
  3836. */
  3837. #define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
  3838. #define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
  3839. #define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
  3840. /*
  3841. * R3628 (0xE2C) - EQ2_7
  3842. */
  3843. #define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
  3844. #define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
  3845. #define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
  3846. /*
  3847. * R3629 (0xE2D) - EQ2_8
  3848. */
  3849. #define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
  3850. #define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
  3851. #define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
  3852. /*
  3853. * R3630 (0xE2E) - EQ2_9
  3854. */
  3855. #define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
  3856. #define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
  3857. #define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
  3858. /*
  3859. * R3631 (0xE2F) - EQ2_10
  3860. */
  3861. #define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
  3862. #define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
  3863. #define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
  3864. /*
  3865. * R3632 (0xE30) - EQ2_11
  3866. */
  3867. #define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
  3868. #define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
  3869. #define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
  3870. /*
  3871. * R3633 (0xE31) - EQ2_12
  3872. */
  3873. #define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
  3874. #define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
  3875. #define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
  3876. /*
  3877. * R3634 (0xE32) - EQ2_13
  3878. */
  3879. #define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
  3880. #define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
  3881. #define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
  3882. /*
  3883. * R3635 (0xE33) - EQ2_14
  3884. */
  3885. #define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
  3886. #define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
  3887. #define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
  3888. /*
  3889. * R3636 (0xE34) - EQ2_15
  3890. */
  3891. #define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
  3892. #define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
  3893. #define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
  3894. /*
  3895. * R3637 (0xE35) - EQ2_16
  3896. */
  3897. #define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
  3898. #define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
  3899. #define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
  3900. /*
  3901. * R3638 (0xE36) - EQ2_17
  3902. */
  3903. #define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
  3904. #define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
  3905. #define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
  3906. /*
  3907. * R3639 (0xE37) - EQ2_18
  3908. */
  3909. #define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
  3910. #define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
  3911. #define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
  3912. /*
  3913. * R3640 (0xE38) - EQ2_19
  3914. */
  3915. #define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
  3916. #define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
  3917. #define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
  3918. /*
  3919. * R3641 (0xE39) - EQ2_20
  3920. */
  3921. #define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
  3922. #define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
  3923. #define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
  3924. /*
  3925. * R3644 (0xE3C) - EQ3_1
  3926. */
  3927. #define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
  3928. #define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
  3929. #define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
  3930. #define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
  3931. #define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
  3932. #define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
  3933. #define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
  3934. #define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
  3935. #define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
  3936. #define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */
  3937. #define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
  3938. #define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
  3939. #define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
  3940. /*
  3941. * R3645 (0xE3D) - EQ3_2
  3942. */
  3943. #define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
  3944. #define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
  3945. #define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
  3946. #define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
  3947. #define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
  3948. #define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
  3949. /*
  3950. * R3646 (0xE3E) - EQ3_3
  3951. */
  3952. #define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
  3953. #define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
  3954. #define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
  3955. /*
  3956. * R3647 (0xE3F) - EQ3_4
  3957. */
  3958. #define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
  3959. #define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
  3960. #define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
  3961. /*
  3962. * R3648 (0xE40) - EQ3_5
  3963. */
  3964. #define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
  3965. #define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
  3966. #define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
  3967. /*
  3968. * R3649 (0xE41) - EQ3_6
  3969. */
  3970. #define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
  3971. #define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
  3972. #define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
  3973. /*
  3974. * R3650 (0xE42) - EQ3_7
  3975. */
  3976. #define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
  3977. #define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
  3978. #define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
  3979. /*
  3980. * R3651 (0xE43) - EQ3_8
  3981. */
  3982. #define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
  3983. #define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
  3984. #define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
  3985. /*
  3986. * R3652 (0xE44) - EQ3_9
  3987. */
  3988. #define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
  3989. #define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
  3990. #define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
  3991. /*
  3992. * R3653 (0xE45) - EQ3_10
  3993. */
  3994. #define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
  3995. #define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
  3996. #define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
  3997. /*
  3998. * R3654 (0xE46) - EQ3_11
  3999. */
  4000. #define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
  4001. #define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
  4002. #define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
  4003. /*
  4004. * R3655 (0xE47) - EQ3_12
  4005. */
  4006. #define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
  4007. #define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
  4008. #define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
  4009. /*
  4010. * R3656 (0xE48) - EQ3_13
  4011. */
  4012. #define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
  4013. #define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
  4014. #define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
  4015. /*
  4016. * R3657 (0xE49) - EQ3_14
  4017. */
  4018. #define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
  4019. #define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
  4020. #define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
  4021. /*
  4022. * R3658 (0xE4A) - EQ3_15
  4023. */
  4024. #define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
  4025. #define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
  4026. #define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
  4027. /*
  4028. * R3659 (0xE4B) - EQ3_16
  4029. */
  4030. #define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
  4031. #define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
  4032. #define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
  4033. /*
  4034. * R3660 (0xE4C) - EQ3_17
  4035. */
  4036. #define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
  4037. #define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
  4038. #define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
  4039. /*
  4040. * R3661 (0xE4D) - EQ3_18
  4041. */
  4042. #define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
  4043. #define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
  4044. #define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
  4045. /*
  4046. * R3662 (0xE4E) - EQ3_19
  4047. */
  4048. #define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
  4049. #define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
  4050. #define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
  4051. /*
  4052. * R3663 (0xE4F) - EQ3_20
  4053. */
  4054. #define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
  4055. #define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
  4056. #define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
  4057. /*
  4058. * R3666 (0xE52) - EQ4_1
  4059. */
  4060. #define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
  4061. #define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
  4062. #define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
  4063. #define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
  4064. #define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
  4065. #define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
  4066. #define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
  4067. #define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
  4068. #define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
  4069. #define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */
  4070. #define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
  4071. #define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
  4072. #define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
  4073. /*
  4074. * R3667 (0xE53) - EQ4_2
  4075. */
  4076. #define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
  4077. #define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
  4078. #define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
  4079. #define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
  4080. #define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
  4081. #define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
  4082. /*
  4083. * R3668 (0xE54) - EQ4_3
  4084. */
  4085. #define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
  4086. #define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
  4087. #define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
  4088. /*
  4089. * R3669 (0xE55) - EQ4_4
  4090. */
  4091. #define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
  4092. #define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
  4093. #define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
  4094. /*
  4095. * R3670 (0xE56) - EQ4_5
  4096. */
  4097. #define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
  4098. #define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
  4099. #define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
  4100. /*
  4101. * R3671 (0xE57) - EQ4_6
  4102. */
  4103. #define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
  4104. #define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
  4105. #define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
  4106. /*
  4107. * R3672 (0xE58) - EQ4_7
  4108. */
  4109. #define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
  4110. #define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
  4111. #define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
  4112. /*
  4113. * R3673 (0xE59) - EQ4_8
  4114. */
  4115. #define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
  4116. #define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
  4117. #define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
  4118. /*
  4119. * R3674 (0xE5A) - EQ4_9
  4120. */
  4121. #define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
  4122. #define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
  4123. #define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
  4124. /*
  4125. * R3675 (0xE5B) - EQ4_10
  4126. */
  4127. #define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
  4128. #define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
  4129. #define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
  4130. /*
  4131. * R3676 (0xE5C) - EQ4_11
  4132. */
  4133. #define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
  4134. #define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
  4135. #define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
  4136. /*
  4137. * R3677 (0xE5D) - EQ4_12
  4138. */
  4139. #define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
  4140. #define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
  4141. #define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
  4142. /*
  4143. * R3678 (0xE5E) - EQ4_13
  4144. */
  4145. #define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
  4146. #define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
  4147. #define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
  4148. /*
  4149. * R3679 (0xE5F) - EQ4_14
  4150. */
  4151. #define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
  4152. #define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
  4153. #define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
  4154. /*
  4155. * R3680 (0xE60) - EQ4_15
  4156. */
  4157. #define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
  4158. #define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
  4159. #define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
  4160. /*
  4161. * R3681 (0xE61) - EQ4_16
  4162. */
  4163. #define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
  4164. #define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
  4165. #define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
  4166. /*
  4167. * R3682 (0xE62) - EQ4_17
  4168. */
  4169. #define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
  4170. #define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
  4171. #define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
  4172. /*
  4173. * R3683 (0xE63) - EQ4_18
  4174. */
  4175. #define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
  4176. #define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
  4177. #define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
  4178. /*
  4179. * R3684 (0xE64) - EQ4_19
  4180. */
  4181. #define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
  4182. #define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
  4183. #define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
  4184. /*
  4185. * R3685 (0xE65) - EQ4_20
  4186. */
  4187. #define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
  4188. #define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
  4189. #define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
  4190. /*
  4191. * R3712 (0xE80) - DRC1 ctrl1
  4192. */
  4193. #define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */
  4194. #define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */
  4195. #define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */
  4196. #define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */
  4197. #define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */
  4198. #define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */
  4199. #define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */
  4200. #define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */
  4201. #define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */
  4202. #define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */
  4203. #define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */
  4204. #define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */
  4205. #define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */
  4206. #define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */
  4207. #define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */
  4208. #define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */
  4209. #define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */
  4210. #define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */
  4211. #define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */
  4212. #define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */
  4213. #define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */
  4214. #define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */
  4215. #define WM5100_DRC_QR 0x0010 /* DRC_QR */
  4216. #define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */
  4217. #define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */
  4218. #define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */
  4219. #define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */
  4220. #define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */
  4221. #define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */
  4222. #define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
  4223. #define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */
  4224. #define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */
  4225. #define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */
  4226. #define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */
  4227. #define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */
  4228. #define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */
  4229. #define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */
  4230. #define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */
  4231. /*
  4232. * R3713 (0xE81) - DRC1 ctrl2
  4233. */
  4234. #define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */
  4235. #define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */
  4236. #define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */
  4237. #define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */
  4238. #define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */
  4239. #define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */
  4240. #define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */
  4241. #define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */
  4242. #define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */
  4243. #define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
  4244. #define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
  4245. #define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
  4246. /*
  4247. * R3714 (0xE82) - DRC1 ctrl3
  4248. */
  4249. #define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */
  4250. #define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */
  4251. #define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */
  4252. #define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */
  4253. #define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */
  4254. #define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */
  4255. #define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */
  4256. #define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */
  4257. #define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */
  4258. #define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */
  4259. #define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */
  4260. #define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */
  4261. #define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
  4262. #define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
  4263. #define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
  4264. #define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
  4265. #define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
  4266. #define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
  4267. /*
  4268. * R3715 (0xE83) - DRC1 ctrl4
  4269. */
  4270. #define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
  4271. #define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
  4272. #define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
  4273. #define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
  4274. #define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
  4275. #define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
  4276. /*
  4277. * R3716 (0xE84) - DRC1 ctrl5
  4278. */
  4279. #define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */
  4280. #define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */
  4281. #define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */
  4282. #define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */
  4283. #define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */
  4284. #define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */
  4285. /*
  4286. * R3776 (0xEC0) - HPLPF1_1
  4287. */
  4288. #define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */
  4289. #define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
  4290. #define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
  4291. #define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
  4292. #define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */
  4293. #define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
  4294. #define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
  4295. #define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
  4296. /*
  4297. * R3777 (0xEC1) - HPLPF1_2
  4298. */
  4299. #define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
  4300. #define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
  4301. #define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
  4302. /*
  4303. * R3780 (0xEC4) - HPLPF2_1
  4304. */
  4305. #define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */
  4306. #define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
  4307. #define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
  4308. #define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
  4309. #define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */
  4310. #define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
  4311. #define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
  4312. #define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
  4313. /*
  4314. * R3781 (0xEC5) - HPLPF2_2
  4315. */
  4316. #define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
  4317. #define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
  4318. #define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
  4319. /*
  4320. * R3784 (0xEC8) - HPLPF3_1
  4321. */
  4322. #define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */
  4323. #define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
  4324. #define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
  4325. #define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
  4326. #define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */
  4327. #define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
  4328. #define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
  4329. #define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
  4330. /*
  4331. * R3785 (0xEC9) - HPLPF3_2
  4332. */
  4333. #define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
  4334. #define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
  4335. #define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
  4336. /*
  4337. * R3788 (0xECC) - HPLPF4_1
  4338. */
  4339. #define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */
  4340. #define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
  4341. #define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
  4342. #define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
  4343. #define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */
  4344. #define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
  4345. #define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
  4346. #define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
  4347. /*
  4348. * R3789 (0xECD) - HPLPF4_2
  4349. */
  4350. #define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
  4351. #define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
  4352. #define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
  4353. /*
  4354. * R4132 (0x1024) - DSP2 Control 30
  4355. */
  4356. #define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */
  4357. #define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */
  4358. #define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */
  4359. #define WM5100_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
  4360. #define WM5100_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
  4361. #define WM5100_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */
  4362. #define WM5100_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */
  4363. #define WM5100_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
  4364. #define WM5100_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
  4365. #define WM5100_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */
  4366. #define WM5100_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */
  4367. #define WM5100_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
  4368. #define WM5100_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
  4369. #define WM5100_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */
  4370. #define WM5100_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */
  4371. #define WM5100_DSP2_START 0x0001 /* DSP2_START */
  4372. #define WM5100_DSP2_START_MASK 0x0001 /* DSP2_START */
  4373. #define WM5100_DSP2_START_SHIFT 0 /* DSP2_START */
  4374. #define WM5100_DSP2_START_WIDTH 1 /* DSP2_START */
  4375. /*
  4376. * R3876 (0xF24) - DSP1 Control 30
  4377. */
  4378. #define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */
  4379. #define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */
  4380. #define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */
  4381. #define WM5100_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
  4382. #define WM5100_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
  4383. #define WM5100_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
  4384. #define WM5100_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
  4385. #define WM5100_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  4386. #define WM5100_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  4387. #define WM5100_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  4388. #define WM5100_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  4389. #define WM5100_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  4390. #define WM5100_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  4391. #define WM5100_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  4392. #define WM5100_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  4393. #define WM5100_DSP1_START 0x0001 /* DSP1_START */
  4394. #define WM5100_DSP1_START_MASK 0x0001 /* DSP1_START */
  4395. #define WM5100_DSP1_START_SHIFT 0 /* DSP1_START */
  4396. #define WM5100_DSP1_START_WIDTH 1 /* DSP1_START */
  4397. /*
  4398. * R4388 (0x1124) - DSP3 Control 30
  4399. */
  4400. #define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */
  4401. #define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */
  4402. #define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */
  4403. #define WM5100_DSP3_DBG_CLK_ENA 0x0008 /* DSP3_DBG_CLK_ENA */
  4404. #define WM5100_DSP3_DBG_CLK_ENA_MASK 0x0008 /* DSP3_DBG_CLK_ENA */
  4405. #define WM5100_DSP3_DBG_CLK_ENA_SHIFT 3 /* DSP3_DBG_CLK_ENA */
  4406. #define WM5100_DSP3_DBG_CLK_ENA_WIDTH 1 /* DSP3_DBG_CLK_ENA */
  4407. #define WM5100_DSP3_SYS_ENA 0x0004 /* DSP3_SYS_ENA */
  4408. #define WM5100_DSP3_SYS_ENA_MASK 0x0004 /* DSP3_SYS_ENA */
  4409. #define WM5100_DSP3_SYS_ENA_SHIFT 2 /* DSP3_SYS_ENA */
  4410. #define WM5100_DSP3_SYS_ENA_WIDTH 1 /* DSP3_SYS_ENA */
  4411. #define WM5100_DSP3_CORE_ENA 0x0002 /* DSP3_CORE_ENA */
  4412. #define WM5100_DSP3_CORE_ENA_MASK 0x0002 /* DSP3_CORE_ENA */
  4413. #define WM5100_DSP3_CORE_ENA_SHIFT 1 /* DSP3_CORE_ENA */
  4414. #define WM5100_DSP3_CORE_ENA_WIDTH 1 /* DSP3_CORE_ENA */
  4415. #define WM5100_DSP3_START 0x0001 /* DSP3_START */
  4416. #define WM5100_DSP3_START_MASK 0x0001 /* DSP3_START */
  4417. #define WM5100_DSP3_START_SHIFT 0 /* DSP3_START */
  4418. #define WM5100_DSP3_START_WIDTH 1 /* DSP3_START */
  4419. /*
  4420. * R16384 (0x4000) - DSP1 DM 0
  4421. */
  4422. #define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */
  4423. #define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */
  4424. #define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */
  4425. /*
  4426. * R16385 (0x4001) - DSP1 DM 1
  4427. */
  4428. #define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */
  4429. #define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */
  4430. #define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */
  4431. /*
  4432. * R16386 (0x4002) - DSP1 DM 2
  4433. */
  4434. #define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */
  4435. #define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */
  4436. #define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */
  4437. /*
  4438. * R16387 (0x4003) - DSP1 DM 3
  4439. */
  4440. #define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */
  4441. #define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */
  4442. #define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */
  4443. /*
  4444. * R16892 (0x41FC) - DSP1 DM 508
  4445. */
  4446. #define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */
  4447. #define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */
  4448. #define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */
  4449. /*
  4450. * R16893 (0x41FD) - DSP1 DM 509
  4451. */
  4452. #define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */
  4453. #define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */
  4454. #define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */
  4455. /*
  4456. * R16894 (0x41FE) - DSP1 DM 510
  4457. */
  4458. #define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */
  4459. #define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */
  4460. #define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */
  4461. /*
  4462. * R16895 (0x41FF) - DSP1 DM 511
  4463. */
  4464. #define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */
  4465. #define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */
  4466. #define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */
  4467. /*
  4468. * R18432 (0x4800) - DSP1 PM 0
  4469. */
  4470. #define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */
  4471. #define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */
  4472. #define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */
  4473. /*
  4474. * R18433 (0x4801) - DSP1 PM 1
  4475. */
  4476. #define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
  4477. #define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */
  4478. #define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */
  4479. /*
  4480. * R18434 (0x4802) - DSP1 PM 2
  4481. */
  4482. #define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */
  4483. #define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */
  4484. #define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */
  4485. /*
  4486. * R18435 (0x4803) - DSP1 PM 3
  4487. */
  4488. #define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */
  4489. #define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */
  4490. #define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */
  4491. /*
  4492. * R18436 (0x4804) - DSP1 PM 4
  4493. */
  4494. #define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
  4495. #define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
  4496. #define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
  4497. /*
  4498. * R18437 (0x4805) - DSP1 PM 5
  4499. */
  4500. #define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */
  4501. #define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */
  4502. #define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */
  4503. /*
  4504. * R19962 (0x4DFA) - DSP1 PM 1530
  4505. */
  4506. #define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */
  4507. #define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */
  4508. #define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */
  4509. /*
  4510. * R19963 (0x4DFB) - DSP1 PM 1531
  4511. */
  4512. #define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
  4513. #define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */
  4514. #define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */
  4515. /*
  4516. * R19964 (0x4DFC) - DSP1 PM 1532
  4517. */
  4518. #define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */
  4519. #define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */
  4520. #define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */
  4521. /*
  4522. * R19965 (0x4DFD) - DSP1 PM 1533
  4523. */
  4524. #define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */
  4525. #define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */
  4526. #define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */
  4527. /*
  4528. * R19966 (0x4DFE) - DSP1 PM 1534
  4529. */
  4530. #define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
  4531. #define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */
  4532. #define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */
  4533. /*
  4534. * R19967 (0x4DFF) - DSP1 PM 1535
  4535. */
  4536. #define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */
  4537. #define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */
  4538. #define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */
  4539. /*
  4540. * R20480 (0x5000) - DSP1 ZM 0
  4541. */
  4542. #define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */
  4543. #define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */
  4544. #define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */
  4545. /*
  4546. * R20481 (0x5001) - DSP1 ZM 1
  4547. */
  4548. #define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */
  4549. #define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */
  4550. #define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */
  4551. /*
  4552. * R20482 (0x5002) - DSP1 ZM 2
  4553. */
  4554. #define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */
  4555. #define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */
  4556. #define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */
  4557. /*
  4558. * R20483 (0x5003) - DSP1 ZM 3
  4559. */
  4560. #define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */
  4561. #define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */
  4562. #define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */
  4563. /*
  4564. * R22524 (0x57FC) - DSP1 ZM 2044
  4565. */
  4566. #define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */
  4567. #define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */
  4568. #define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */
  4569. /*
  4570. * R22525 (0x57FD) - DSP1 ZM 2045
  4571. */
  4572. #define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */
  4573. #define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */
  4574. #define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */
  4575. /*
  4576. * R22526 (0x57FE) - DSP1 ZM 2046
  4577. */
  4578. #define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */
  4579. #define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */
  4580. #define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */
  4581. /*
  4582. * R22527 (0x57FF) - DSP1 ZM 2047
  4583. */
  4584. #define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */
  4585. #define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */
  4586. #define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */
  4587. /*
  4588. * R24576 (0x6000) - DSP2 DM 0
  4589. */
  4590. #define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */
  4591. #define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */
  4592. #define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */
  4593. /*
  4594. * R24577 (0x6001) - DSP2 DM 1
  4595. */
  4596. #define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */
  4597. #define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */
  4598. #define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */
  4599. /*
  4600. * R24578 (0x6002) - DSP2 DM 2
  4601. */
  4602. #define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */
  4603. #define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */
  4604. #define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */
  4605. /*
  4606. * R24579 (0x6003) - DSP2 DM 3
  4607. */
  4608. #define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */
  4609. #define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */
  4610. #define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */
  4611. /*
  4612. * R25084 (0x61FC) - DSP2 DM 508
  4613. */
  4614. #define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */
  4615. #define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */
  4616. #define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */
  4617. /*
  4618. * R25085 (0x61FD) - DSP2 DM 509
  4619. */
  4620. #define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */
  4621. #define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */
  4622. #define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */
  4623. /*
  4624. * R25086 (0x61FE) - DSP2 DM 510
  4625. */
  4626. #define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */
  4627. #define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */
  4628. #define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */
  4629. /*
  4630. * R25087 (0x61FF) - DSP2 DM 511
  4631. */
  4632. #define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */
  4633. #define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */
  4634. #define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */
  4635. /*
  4636. * R26624 (0x6800) - DSP2 PM 0
  4637. */
  4638. #define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */
  4639. #define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */
  4640. #define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */
  4641. /*
  4642. * R26625 (0x6801) - DSP2 PM 1
  4643. */
  4644. #define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
  4645. #define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */
  4646. #define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */
  4647. /*
  4648. * R26626 (0x6802) - DSP2 PM 2
  4649. */
  4650. #define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */
  4651. #define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */
  4652. #define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */
  4653. /*
  4654. * R26627 (0x6803) - DSP2 PM 3
  4655. */
  4656. #define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */
  4657. #define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */
  4658. #define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */
  4659. /*
  4660. * R26628 (0x6804) - DSP2 PM 4
  4661. */
  4662. #define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
  4663. #define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
  4664. #define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
  4665. /*
  4666. * R26629 (0x6805) - DSP2 PM 5
  4667. */
  4668. #define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */
  4669. #define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */
  4670. #define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */
  4671. /*
  4672. * R28154 (0x6DFA) - DSP2 PM 1530
  4673. */
  4674. #define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */
  4675. #define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */
  4676. #define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */
  4677. /*
  4678. * R28155 (0x6DFB) - DSP2 PM 1531
  4679. */
  4680. #define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
  4681. #define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */
  4682. #define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */
  4683. /*
  4684. * R28156 (0x6DFC) - DSP2 PM 1532
  4685. */
  4686. #define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */
  4687. #define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */
  4688. #define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */
  4689. /*
  4690. * R28157 (0x6DFD) - DSP2 PM 1533
  4691. */
  4692. #define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */
  4693. #define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */
  4694. #define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */
  4695. /*
  4696. * R28158 (0x6DFE) - DSP2 PM 1534
  4697. */
  4698. #define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
  4699. #define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */
  4700. #define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */
  4701. /*
  4702. * R28159 (0x6DFF) - DSP2 PM 1535
  4703. */
  4704. #define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */
  4705. #define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */
  4706. #define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */
  4707. /*
  4708. * R28672 (0x7000) - DSP2 ZM 0
  4709. */
  4710. #define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */
  4711. #define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */
  4712. #define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */
  4713. /*
  4714. * R28673 (0x7001) - DSP2 ZM 1
  4715. */
  4716. #define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */
  4717. #define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */
  4718. #define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */
  4719. /*
  4720. * R28674 (0x7002) - DSP2 ZM 2
  4721. */
  4722. #define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */
  4723. #define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */
  4724. #define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */
  4725. /*
  4726. * R28675 (0x7003) - DSP2 ZM 3
  4727. */
  4728. #define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */
  4729. #define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */
  4730. #define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */
  4731. /*
  4732. * R30716 (0x77FC) - DSP2 ZM 2044
  4733. */
  4734. #define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */
  4735. #define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */
  4736. #define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */
  4737. /*
  4738. * R30717 (0x77FD) - DSP2 ZM 2045
  4739. */
  4740. #define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */
  4741. #define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */
  4742. #define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */
  4743. /*
  4744. * R30718 (0x77FE) - DSP2 ZM 2046
  4745. */
  4746. #define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */
  4747. #define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */
  4748. #define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */
  4749. /*
  4750. * R30719 (0x77FF) - DSP2 ZM 2047
  4751. */
  4752. #define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */
  4753. #define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */
  4754. #define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */
  4755. /*
  4756. * R32768 (0x8000) - DSP3 DM 0
  4757. */
  4758. #define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */
  4759. #define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */
  4760. #define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */
  4761. /*
  4762. * R32769 (0x8001) - DSP3 DM 1
  4763. */
  4764. #define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */
  4765. #define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */
  4766. #define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */
  4767. /*
  4768. * R32770 (0x8002) - DSP3 DM 2
  4769. */
  4770. #define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */
  4771. #define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */
  4772. #define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */
  4773. /*
  4774. * R32771 (0x8003) - DSP3 DM 3
  4775. */
  4776. #define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */
  4777. #define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */
  4778. #define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */
  4779. /*
  4780. * R33276 (0x81FC) - DSP3 DM 508
  4781. */
  4782. #define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */
  4783. #define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */
  4784. #define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */
  4785. /*
  4786. * R33277 (0x81FD) - DSP3 DM 509
  4787. */
  4788. #define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */
  4789. #define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */
  4790. #define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */
  4791. /*
  4792. * R33278 (0x81FE) - DSP3 DM 510
  4793. */
  4794. #define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */
  4795. #define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */
  4796. #define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */
  4797. /*
  4798. * R33279 (0x81FF) - DSP3 DM 511
  4799. */
  4800. #define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */
  4801. #define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */
  4802. #define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */
  4803. /*
  4804. * R34816 (0x8800) - DSP3 PM 0
  4805. */
  4806. #define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */
  4807. #define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */
  4808. #define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */
  4809. /*
  4810. * R34817 (0x8801) - DSP3 PM 1
  4811. */
  4812. #define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
  4813. #define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */
  4814. #define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */
  4815. /*
  4816. * R34818 (0x8802) - DSP3 PM 2
  4817. */
  4818. #define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */
  4819. #define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */
  4820. #define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */
  4821. /*
  4822. * R34819 (0x8803) - DSP3 PM 3
  4823. */
  4824. #define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */
  4825. #define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */
  4826. #define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */
  4827. /*
  4828. * R34820 (0x8804) - DSP3 PM 4
  4829. */
  4830. #define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
  4831. #define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
  4832. #define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
  4833. /*
  4834. * R34821 (0x8805) - DSP3 PM 5
  4835. */
  4836. #define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */
  4837. #define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */
  4838. #define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */
  4839. /*
  4840. * R36346 (0x8DFA) - DSP3 PM 1530
  4841. */
  4842. #define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */
  4843. #define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */
  4844. #define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */
  4845. /*
  4846. * R36347 (0x8DFB) - DSP3 PM 1531
  4847. */
  4848. #define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
  4849. #define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */
  4850. #define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */
  4851. /*
  4852. * R36348 (0x8DFC) - DSP3 PM 1532
  4853. */
  4854. #define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */
  4855. #define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */
  4856. #define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */
  4857. /*
  4858. * R36349 (0x8DFD) - DSP3 PM 1533
  4859. */
  4860. #define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */
  4861. #define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */
  4862. #define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */
  4863. /*
  4864. * R36350 (0x8DFE) - DSP3 PM 1534
  4865. */
  4866. #define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
  4867. #define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */
  4868. #define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */
  4869. /*
  4870. * R36351 (0x8DFF) - DSP3 PM 1535
  4871. */
  4872. #define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */
  4873. #define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */
  4874. #define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */
  4875. /*
  4876. * R36864 (0x9000) - DSP3 ZM 0
  4877. */
  4878. #define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */
  4879. #define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */
  4880. #define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */
  4881. /*
  4882. * R36865 (0x9001) - DSP3 ZM 1
  4883. */
  4884. #define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */
  4885. #define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */
  4886. #define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */
  4887. /*
  4888. * R36866 (0x9002) - DSP3 ZM 2
  4889. */
  4890. #define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */
  4891. #define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */
  4892. #define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */
  4893. /*
  4894. * R36867 (0x9003) - DSP3 ZM 3
  4895. */
  4896. #define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */
  4897. #define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */
  4898. #define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */
  4899. /*
  4900. * R38908 (0x97FC) - DSP3 ZM 2044
  4901. */
  4902. #define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */
  4903. #define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */
  4904. #define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */
  4905. /*
  4906. * R38909 (0x97FD) - DSP3 ZM 2045
  4907. */
  4908. #define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */
  4909. #define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */
  4910. #define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */
  4911. /*
  4912. * R38910 (0x97FE) - DSP3 ZM 2046
  4913. */
  4914. #define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */
  4915. #define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */
  4916. #define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */
  4917. /*
  4918. * R38911 (0x97FF) - DSP3 ZM 2047
  4919. */
  4920. #define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */
  4921. #define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */
  4922. #define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */
  4923. bool wm5100_readable_register(struct device *dev, unsigned int reg);
  4924. bool wm5100_volatile_register(struct device *dev, unsigned int reg);
  4925. extern struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT];
  4926. #endif