rt5682.c 90 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // rt5682.c -- RT5682 ALSA SoC audio component driver
  4. //
  5. // Copyright 2018 Realtek Semiconductor Corp.
  6. // Author: Bard Liao <[email protected]>
  7. //
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/acpi.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/mutex.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/jack.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/rt5682.h>
  29. #include "rl6231.h"
  30. #include "rt5682.h"
  31. const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  32. "AVDD",
  33. "MICVDD",
  34. "VBAT",
  35. };
  36. EXPORT_SYMBOL_GPL(rt5682_supply_names);
  37. static const struct reg_sequence patch_list[] = {
  38. {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  39. {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  40. {RT5682_I2C_CTRL, 0x000f},
  41. {RT5682_PLL2_INTERNAL, 0x8266},
  42. {RT5682_SAR_IL_CMD_1, 0x22b7},
  43. {RT5682_SAR_IL_CMD_3, 0x0365},
  44. {RT5682_SAR_IL_CMD_6, 0x0110},
  45. {RT5682_CHARGE_PUMP_1, 0x0210},
  46. {RT5682_HP_LOGIC_CTRL_2, 0x0007},
  47. {RT5682_SAR_IL_CMD_2, 0xac00},
  48. {RT5682_CBJ_CTRL_7, 0x0104},
  49. };
  50. void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  51. {
  52. int ret;
  53. ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  54. ARRAY_SIZE(patch_list));
  55. if (ret)
  56. dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  57. }
  58. EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  59. const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  60. {0x0002, 0x8080},
  61. {0x0003, 0x8000},
  62. {0x0005, 0x0000},
  63. {0x0006, 0x0000},
  64. {0x0008, 0x800f},
  65. {0x000b, 0x0000},
  66. {0x0010, 0x4040},
  67. {0x0011, 0x0000},
  68. {0x0012, 0x1404},
  69. {0x0013, 0x1000},
  70. {0x0014, 0xa00a},
  71. {0x0015, 0x0404},
  72. {0x0016, 0x0404},
  73. {0x0019, 0xafaf},
  74. {0x001c, 0x2f2f},
  75. {0x001f, 0x0000},
  76. {0x0022, 0x5757},
  77. {0x0023, 0x0039},
  78. {0x0024, 0x000b},
  79. {0x0026, 0xc0c4},
  80. {0x0029, 0x8080},
  81. {0x002a, 0xa0a0},
  82. {0x002b, 0x0300},
  83. {0x0030, 0x0000},
  84. {0x003c, 0x0080},
  85. {0x0044, 0x0c0c},
  86. {0x0049, 0x0000},
  87. {0x0061, 0x0000},
  88. {0x0062, 0x0000},
  89. {0x0063, 0x003f},
  90. {0x0064, 0x0000},
  91. {0x0065, 0x0000},
  92. {0x0066, 0x0030},
  93. {0x0067, 0x0000},
  94. {0x006b, 0x0000},
  95. {0x006c, 0x0000},
  96. {0x006d, 0x2200},
  97. {0x006e, 0x0a10},
  98. {0x0070, 0x8000},
  99. {0x0071, 0x8000},
  100. {0x0073, 0x0000},
  101. {0x0074, 0x0000},
  102. {0x0075, 0x0002},
  103. {0x0076, 0x0001},
  104. {0x0079, 0x0000},
  105. {0x007a, 0x0000},
  106. {0x007b, 0x0000},
  107. {0x007c, 0x0100},
  108. {0x007e, 0x0000},
  109. {0x0080, 0x0000},
  110. {0x0081, 0x0000},
  111. {0x0082, 0x0000},
  112. {0x0083, 0x0000},
  113. {0x0084, 0x0000},
  114. {0x0085, 0x0000},
  115. {0x0086, 0x0005},
  116. {0x0087, 0x0000},
  117. {0x0088, 0x0000},
  118. {0x008c, 0x0003},
  119. {0x008d, 0x0000},
  120. {0x008e, 0x0060},
  121. {0x008f, 0x1000},
  122. {0x0091, 0x0c26},
  123. {0x0092, 0x0073},
  124. {0x0093, 0x0000},
  125. {0x0094, 0x0080},
  126. {0x0098, 0x0000},
  127. {0x009a, 0x0000},
  128. {0x009b, 0x0000},
  129. {0x009c, 0x0000},
  130. {0x009d, 0x0000},
  131. {0x009e, 0x100c},
  132. {0x009f, 0x0000},
  133. {0x00a0, 0x0000},
  134. {0x00a3, 0x0002},
  135. {0x00a4, 0x0001},
  136. {0x00ae, 0x2040},
  137. {0x00af, 0x0000},
  138. {0x00b6, 0x0000},
  139. {0x00b7, 0x0000},
  140. {0x00b8, 0x0000},
  141. {0x00b9, 0x0002},
  142. {0x00be, 0x0000},
  143. {0x00c0, 0x0160},
  144. {0x00c1, 0x82a0},
  145. {0x00c2, 0x0000},
  146. {0x00d0, 0x0000},
  147. {0x00d1, 0x2244},
  148. {0x00d2, 0x3300},
  149. {0x00d3, 0x2200},
  150. {0x00d4, 0x0000},
  151. {0x00d9, 0x0009},
  152. {0x00da, 0x0000},
  153. {0x00db, 0x0000},
  154. {0x00dc, 0x00c0},
  155. {0x00dd, 0x2220},
  156. {0x00de, 0x3131},
  157. {0x00df, 0x3131},
  158. {0x00e0, 0x3131},
  159. {0x00e2, 0x0000},
  160. {0x00e3, 0x4000},
  161. {0x00e4, 0x0aa0},
  162. {0x00e5, 0x3131},
  163. {0x00e6, 0x3131},
  164. {0x00e7, 0x3131},
  165. {0x00e8, 0x3131},
  166. {0x00ea, 0xb320},
  167. {0x00eb, 0x0000},
  168. {0x00f0, 0x0000},
  169. {0x00f1, 0x00d0},
  170. {0x00f2, 0x00d0},
  171. {0x00f6, 0x0000},
  172. {0x00fa, 0x0000},
  173. {0x00fb, 0x0000},
  174. {0x00fc, 0x0000},
  175. {0x00fd, 0x0000},
  176. {0x00fe, 0x10ec},
  177. {0x00ff, 0x6530},
  178. {0x0100, 0xa0a0},
  179. {0x010b, 0x0000},
  180. {0x010c, 0xae00},
  181. {0x010d, 0xaaa0},
  182. {0x010e, 0x8aa2},
  183. {0x010f, 0x02a2},
  184. {0x0110, 0xc000},
  185. {0x0111, 0x04a2},
  186. {0x0112, 0x2800},
  187. {0x0113, 0x0000},
  188. {0x0117, 0x0100},
  189. {0x0125, 0x0410},
  190. {0x0132, 0x6026},
  191. {0x0136, 0x5555},
  192. {0x0138, 0x3700},
  193. {0x013a, 0x2000},
  194. {0x013b, 0x2000},
  195. {0x013c, 0x2005},
  196. {0x013f, 0x0000},
  197. {0x0142, 0x0000},
  198. {0x0145, 0x0002},
  199. {0x0146, 0x0000},
  200. {0x0147, 0x0000},
  201. {0x0148, 0x0000},
  202. {0x0149, 0x0000},
  203. {0x0150, 0x79a1},
  204. {0x0156, 0xaaaa},
  205. {0x0160, 0x4ec0},
  206. {0x0161, 0x0080},
  207. {0x0162, 0x0200},
  208. {0x0163, 0x0800},
  209. {0x0164, 0x0000},
  210. {0x0165, 0x0000},
  211. {0x0166, 0x0000},
  212. {0x0167, 0x000f},
  213. {0x0168, 0x000f},
  214. {0x0169, 0x0021},
  215. {0x0190, 0x413d},
  216. {0x0194, 0x0000},
  217. {0x0195, 0x0000},
  218. {0x0197, 0x0022},
  219. {0x0198, 0x0000},
  220. {0x0199, 0x0000},
  221. {0x01af, 0x0000},
  222. {0x01b0, 0x0400},
  223. {0x01b1, 0x0000},
  224. {0x01b2, 0x0000},
  225. {0x01b3, 0x0000},
  226. {0x01b4, 0x0000},
  227. {0x01b5, 0x0000},
  228. {0x01b6, 0x01c3},
  229. {0x01b7, 0x02a0},
  230. {0x01b8, 0x03e9},
  231. {0x01b9, 0x1389},
  232. {0x01ba, 0xc351},
  233. {0x01bb, 0x0009},
  234. {0x01bc, 0x0018},
  235. {0x01bd, 0x002a},
  236. {0x01be, 0x004c},
  237. {0x01bf, 0x0097},
  238. {0x01c0, 0x433d},
  239. {0x01c2, 0x0000},
  240. {0x01c3, 0x0000},
  241. {0x01c4, 0x0000},
  242. {0x01c5, 0x0000},
  243. {0x01c6, 0x0000},
  244. {0x01c7, 0x0000},
  245. {0x01c8, 0x40af},
  246. {0x01c9, 0x0702},
  247. {0x01ca, 0x0000},
  248. {0x01cb, 0x0000},
  249. {0x01cc, 0x5757},
  250. {0x01cd, 0x5757},
  251. {0x01ce, 0x5757},
  252. {0x01cf, 0x5757},
  253. {0x01d0, 0x5757},
  254. {0x01d1, 0x5757},
  255. {0x01d2, 0x5757},
  256. {0x01d3, 0x5757},
  257. {0x01d4, 0x5757},
  258. {0x01d5, 0x5757},
  259. {0x01d6, 0x0000},
  260. {0x01d7, 0x0008},
  261. {0x01d8, 0x0029},
  262. {0x01d9, 0x3333},
  263. {0x01da, 0x0000},
  264. {0x01db, 0x0004},
  265. {0x01dc, 0x0000},
  266. {0x01de, 0x7c00},
  267. {0x01df, 0x0320},
  268. {0x01e0, 0x06a1},
  269. {0x01e1, 0x0000},
  270. {0x01e2, 0x0000},
  271. {0x01e3, 0x0000},
  272. {0x01e4, 0x0000},
  273. {0x01e6, 0x0001},
  274. {0x01e7, 0x0000},
  275. {0x01e8, 0x0000},
  276. {0x01ea, 0x0000},
  277. {0x01eb, 0x0000},
  278. {0x01ec, 0x0000},
  279. {0x01ed, 0x0000},
  280. {0x01ee, 0x0000},
  281. {0x01ef, 0x0000},
  282. {0x01f0, 0x0000},
  283. {0x01f1, 0x0000},
  284. {0x01f2, 0x0000},
  285. {0x01f3, 0x0000},
  286. {0x01f4, 0x0000},
  287. {0x0210, 0x6297},
  288. {0x0211, 0xa005},
  289. {0x0212, 0x824c},
  290. {0x0213, 0xf7ff},
  291. {0x0214, 0xf24c},
  292. {0x0215, 0x0102},
  293. {0x0216, 0x00a3},
  294. {0x0217, 0x0048},
  295. {0x0218, 0xa2c0},
  296. {0x0219, 0x0400},
  297. {0x021a, 0x00c8},
  298. {0x021b, 0x00c0},
  299. {0x021c, 0x0000},
  300. {0x0250, 0x4500},
  301. {0x0251, 0x40b3},
  302. {0x0252, 0x0000},
  303. {0x0253, 0x0000},
  304. {0x0254, 0x0000},
  305. {0x0255, 0x0000},
  306. {0x0256, 0x0000},
  307. {0x0257, 0x0000},
  308. {0x0258, 0x0000},
  309. {0x0259, 0x0000},
  310. {0x025a, 0x0005},
  311. {0x0270, 0x0000},
  312. {0x02ff, 0x0110},
  313. {0x0300, 0x001f},
  314. {0x0301, 0x032c},
  315. {0x0302, 0x5f21},
  316. {0x0303, 0x4000},
  317. {0x0304, 0x4000},
  318. {0x0305, 0x06d5},
  319. {0x0306, 0x8000},
  320. {0x0307, 0x0700},
  321. {0x0310, 0x4560},
  322. {0x0311, 0xa4a8},
  323. {0x0312, 0x7418},
  324. {0x0313, 0x0000},
  325. {0x0314, 0x0006},
  326. {0x0315, 0xffff},
  327. {0x0316, 0xc400},
  328. {0x0317, 0x0000},
  329. {0x03c0, 0x7e00},
  330. {0x03c1, 0x8000},
  331. {0x03c2, 0x8000},
  332. {0x03c3, 0x8000},
  333. {0x03c4, 0x8000},
  334. {0x03c5, 0x8000},
  335. {0x03c6, 0x8000},
  336. {0x03c7, 0x8000},
  337. {0x03c8, 0x8000},
  338. {0x03c9, 0x8000},
  339. {0x03ca, 0x8000},
  340. {0x03cb, 0x8000},
  341. {0x03cc, 0x8000},
  342. {0x03d0, 0x0000},
  343. {0x03d1, 0x0000},
  344. {0x03d2, 0x0000},
  345. {0x03d3, 0x0000},
  346. {0x03d4, 0x2000},
  347. {0x03d5, 0x2000},
  348. {0x03d6, 0x0000},
  349. {0x03d7, 0x0000},
  350. {0x03d8, 0x2000},
  351. {0x03d9, 0x2000},
  352. {0x03da, 0x2000},
  353. {0x03db, 0x2000},
  354. {0x03dc, 0x0000},
  355. {0x03dd, 0x0000},
  356. {0x03de, 0x0000},
  357. {0x03df, 0x2000},
  358. {0x03e0, 0x0000},
  359. {0x03e1, 0x0000},
  360. {0x03e2, 0x0000},
  361. {0x03e3, 0x0000},
  362. {0x03e4, 0x0000},
  363. {0x03e5, 0x0000},
  364. {0x03e6, 0x0000},
  365. {0x03e7, 0x0000},
  366. {0x03e8, 0x0000},
  367. {0x03e9, 0x0000},
  368. {0x03ea, 0x0000},
  369. {0x03eb, 0x0000},
  370. {0x03ec, 0x0000},
  371. {0x03ed, 0x0000},
  372. {0x03ee, 0x0000},
  373. {0x03ef, 0x0000},
  374. {0x03f0, 0x0800},
  375. {0x03f1, 0x0800},
  376. {0x03f2, 0x0800},
  377. {0x03f3, 0x0800},
  378. };
  379. EXPORT_SYMBOL_GPL(rt5682_reg);
  380. bool rt5682_volatile_register(struct device *dev, unsigned int reg)
  381. {
  382. switch (reg) {
  383. case RT5682_RESET:
  384. case RT5682_CBJ_CTRL_2:
  385. case RT5682_INT_ST_1:
  386. case RT5682_4BTN_IL_CMD_1:
  387. case RT5682_AJD1_CTRL:
  388. case RT5682_HP_CALIB_CTRL_1:
  389. case RT5682_DEVICE_ID:
  390. case RT5682_I2C_MODE:
  391. case RT5682_HP_CALIB_CTRL_10:
  392. case RT5682_EFUSE_CTRL_2:
  393. case RT5682_JD_TOP_VC_VTRL:
  394. case RT5682_HP_IMP_SENS_CTRL_19:
  395. case RT5682_IL_CMD_1:
  396. case RT5682_SAR_IL_CMD_2:
  397. case RT5682_SAR_IL_CMD_4:
  398. case RT5682_SAR_IL_CMD_10:
  399. case RT5682_SAR_IL_CMD_11:
  400. case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
  401. case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
  402. return true;
  403. default:
  404. return false;
  405. }
  406. }
  407. EXPORT_SYMBOL_GPL(rt5682_volatile_register);
  408. bool rt5682_readable_register(struct device *dev, unsigned int reg)
  409. {
  410. switch (reg) {
  411. case RT5682_RESET:
  412. case RT5682_VERSION_ID:
  413. case RT5682_VENDOR_ID:
  414. case RT5682_DEVICE_ID:
  415. case RT5682_HP_CTRL_1:
  416. case RT5682_HP_CTRL_2:
  417. case RT5682_HPL_GAIN:
  418. case RT5682_HPR_GAIN:
  419. case RT5682_I2C_CTRL:
  420. case RT5682_CBJ_BST_CTRL:
  421. case RT5682_CBJ_CTRL_1:
  422. case RT5682_CBJ_CTRL_2:
  423. case RT5682_CBJ_CTRL_3:
  424. case RT5682_CBJ_CTRL_4:
  425. case RT5682_CBJ_CTRL_5:
  426. case RT5682_CBJ_CTRL_6:
  427. case RT5682_CBJ_CTRL_7:
  428. case RT5682_DAC1_DIG_VOL:
  429. case RT5682_STO1_ADC_DIG_VOL:
  430. case RT5682_STO1_ADC_BOOST:
  431. case RT5682_HP_IMP_GAIN_1:
  432. case RT5682_HP_IMP_GAIN_2:
  433. case RT5682_SIDETONE_CTRL:
  434. case RT5682_STO1_ADC_MIXER:
  435. case RT5682_AD_DA_MIXER:
  436. case RT5682_STO1_DAC_MIXER:
  437. case RT5682_A_DAC1_MUX:
  438. case RT5682_DIG_INF2_DATA:
  439. case RT5682_REC_MIXER:
  440. case RT5682_CAL_REC:
  441. case RT5682_ALC_BACK_GAIN:
  442. case RT5682_PWR_DIG_1:
  443. case RT5682_PWR_DIG_2:
  444. case RT5682_PWR_ANLG_1:
  445. case RT5682_PWR_ANLG_2:
  446. case RT5682_PWR_ANLG_3:
  447. case RT5682_PWR_MIXER:
  448. case RT5682_PWR_VOL:
  449. case RT5682_CLK_DET:
  450. case RT5682_RESET_LPF_CTRL:
  451. case RT5682_RESET_HPF_CTRL:
  452. case RT5682_DMIC_CTRL_1:
  453. case RT5682_I2S1_SDP:
  454. case RT5682_I2S2_SDP:
  455. case RT5682_ADDA_CLK_1:
  456. case RT5682_ADDA_CLK_2:
  457. case RT5682_I2S1_F_DIV_CTRL_1:
  458. case RT5682_I2S1_F_DIV_CTRL_2:
  459. case RT5682_TDM_CTRL:
  460. case RT5682_TDM_ADDA_CTRL_1:
  461. case RT5682_TDM_ADDA_CTRL_2:
  462. case RT5682_DATA_SEL_CTRL_1:
  463. case RT5682_TDM_TCON_CTRL:
  464. case RT5682_GLB_CLK:
  465. case RT5682_PLL_CTRL_1:
  466. case RT5682_PLL_CTRL_2:
  467. case RT5682_PLL_TRACK_1:
  468. case RT5682_PLL_TRACK_2:
  469. case RT5682_PLL_TRACK_3:
  470. case RT5682_PLL_TRACK_4:
  471. case RT5682_PLL_TRACK_5:
  472. case RT5682_PLL_TRACK_6:
  473. case RT5682_PLL_TRACK_11:
  474. case RT5682_SDW_REF_CLK:
  475. case RT5682_DEPOP_1:
  476. case RT5682_DEPOP_2:
  477. case RT5682_HP_CHARGE_PUMP_1:
  478. case RT5682_HP_CHARGE_PUMP_2:
  479. case RT5682_MICBIAS_1:
  480. case RT5682_MICBIAS_2:
  481. case RT5682_PLL_TRACK_12:
  482. case RT5682_PLL_TRACK_14:
  483. case RT5682_PLL2_CTRL_1:
  484. case RT5682_PLL2_CTRL_2:
  485. case RT5682_PLL2_CTRL_3:
  486. case RT5682_PLL2_CTRL_4:
  487. case RT5682_RC_CLK_CTRL:
  488. case RT5682_I2S_M_CLK_CTRL_1:
  489. case RT5682_I2S2_F_DIV_CTRL_1:
  490. case RT5682_I2S2_F_DIV_CTRL_2:
  491. case RT5682_EQ_CTRL_1:
  492. case RT5682_EQ_CTRL_2:
  493. case RT5682_IRQ_CTRL_1:
  494. case RT5682_IRQ_CTRL_2:
  495. case RT5682_IRQ_CTRL_3:
  496. case RT5682_IRQ_CTRL_4:
  497. case RT5682_INT_ST_1:
  498. case RT5682_GPIO_CTRL_1:
  499. case RT5682_GPIO_CTRL_2:
  500. case RT5682_GPIO_CTRL_3:
  501. case RT5682_HP_AMP_DET_CTRL_1:
  502. case RT5682_HP_AMP_DET_CTRL_2:
  503. case RT5682_MID_HP_AMP_DET:
  504. case RT5682_LOW_HP_AMP_DET:
  505. case RT5682_DELAY_BUF_CTRL:
  506. case RT5682_SV_ZCD_1:
  507. case RT5682_SV_ZCD_2:
  508. case RT5682_IL_CMD_1:
  509. case RT5682_IL_CMD_2:
  510. case RT5682_IL_CMD_3:
  511. case RT5682_IL_CMD_4:
  512. case RT5682_IL_CMD_5:
  513. case RT5682_IL_CMD_6:
  514. case RT5682_4BTN_IL_CMD_1:
  515. case RT5682_4BTN_IL_CMD_2:
  516. case RT5682_4BTN_IL_CMD_3:
  517. case RT5682_4BTN_IL_CMD_4:
  518. case RT5682_4BTN_IL_CMD_5:
  519. case RT5682_4BTN_IL_CMD_6:
  520. case RT5682_4BTN_IL_CMD_7:
  521. case RT5682_ADC_STO1_HP_CTRL_1:
  522. case RT5682_ADC_STO1_HP_CTRL_2:
  523. case RT5682_AJD1_CTRL:
  524. case RT5682_JD1_THD:
  525. case RT5682_JD2_THD:
  526. case RT5682_JD_CTRL_1:
  527. case RT5682_DUMMY_1:
  528. case RT5682_DUMMY_2:
  529. case RT5682_DUMMY_3:
  530. case RT5682_DAC_ADC_DIG_VOL1:
  531. case RT5682_BIAS_CUR_CTRL_2:
  532. case RT5682_BIAS_CUR_CTRL_3:
  533. case RT5682_BIAS_CUR_CTRL_4:
  534. case RT5682_BIAS_CUR_CTRL_5:
  535. case RT5682_BIAS_CUR_CTRL_6:
  536. case RT5682_BIAS_CUR_CTRL_7:
  537. case RT5682_BIAS_CUR_CTRL_8:
  538. case RT5682_BIAS_CUR_CTRL_9:
  539. case RT5682_BIAS_CUR_CTRL_10:
  540. case RT5682_VREF_REC_OP_FB_CAP_CTRL:
  541. case RT5682_CHARGE_PUMP_1:
  542. case RT5682_DIG_IN_CTRL_1:
  543. case RT5682_PAD_DRIVING_CTRL:
  544. case RT5682_SOFT_RAMP_DEPOP:
  545. case RT5682_CHOP_DAC:
  546. case RT5682_CHOP_ADC:
  547. case RT5682_CALIB_ADC_CTRL:
  548. case RT5682_VOL_TEST:
  549. case RT5682_SPKVDD_DET_STA:
  550. case RT5682_TEST_MODE_CTRL_1:
  551. case RT5682_TEST_MODE_CTRL_2:
  552. case RT5682_TEST_MODE_CTRL_3:
  553. case RT5682_TEST_MODE_CTRL_4:
  554. case RT5682_TEST_MODE_CTRL_5:
  555. case RT5682_PLL1_INTERNAL:
  556. case RT5682_PLL2_INTERNAL:
  557. case RT5682_STO_NG2_CTRL_1:
  558. case RT5682_STO_NG2_CTRL_2:
  559. case RT5682_STO_NG2_CTRL_3:
  560. case RT5682_STO_NG2_CTRL_4:
  561. case RT5682_STO_NG2_CTRL_5:
  562. case RT5682_STO_NG2_CTRL_6:
  563. case RT5682_STO_NG2_CTRL_7:
  564. case RT5682_STO_NG2_CTRL_8:
  565. case RT5682_STO_NG2_CTRL_9:
  566. case RT5682_STO_NG2_CTRL_10:
  567. case RT5682_STO1_DAC_SIL_DET:
  568. case RT5682_SIL_PSV_CTRL1:
  569. case RT5682_SIL_PSV_CTRL2:
  570. case RT5682_SIL_PSV_CTRL3:
  571. case RT5682_SIL_PSV_CTRL4:
  572. case RT5682_SIL_PSV_CTRL5:
  573. case RT5682_HP_IMP_SENS_CTRL_01:
  574. case RT5682_HP_IMP_SENS_CTRL_02:
  575. case RT5682_HP_IMP_SENS_CTRL_03:
  576. case RT5682_HP_IMP_SENS_CTRL_04:
  577. case RT5682_HP_IMP_SENS_CTRL_05:
  578. case RT5682_HP_IMP_SENS_CTRL_06:
  579. case RT5682_HP_IMP_SENS_CTRL_07:
  580. case RT5682_HP_IMP_SENS_CTRL_08:
  581. case RT5682_HP_IMP_SENS_CTRL_09:
  582. case RT5682_HP_IMP_SENS_CTRL_10:
  583. case RT5682_HP_IMP_SENS_CTRL_11:
  584. case RT5682_HP_IMP_SENS_CTRL_12:
  585. case RT5682_HP_IMP_SENS_CTRL_13:
  586. case RT5682_HP_IMP_SENS_CTRL_14:
  587. case RT5682_HP_IMP_SENS_CTRL_15:
  588. case RT5682_HP_IMP_SENS_CTRL_16:
  589. case RT5682_HP_IMP_SENS_CTRL_17:
  590. case RT5682_HP_IMP_SENS_CTRL_18:
  591. case RT5682_HP_IMP_SENS_CTRL_19:
  592. case RT5682_HP_IMP_SENS_CTRL_20:
  593. case RT5682_HP_IMP_SENS_CTRL_21:
  594. case RT5682_HP_IMP_SENS_CTRL_22:
  595. case RT5682_HP_IMP_SENS_CTRL_23:
  596. case RT5682_HP_IMP_SENS_CTRL_24:
  597. case RT5682_HP_IMP_SENS_CTRL_25:
  598. case RT5682_HP_IMP_SENS_CTRL_26:
  599. case RT5682_HP_IMP_SENS_CTRL_27:
  600. case RT5682_HP_IMP_SENS_CTRL_28:
  601. case RT5682_HP_IMP_SENS_CTRL_29:
  602. case RT5682_HP_IMP_SENS_CTRL_30:
  603. case RT5682_HP_IMP_SENS_CTRL_31:
  604. case RT5682_HP_IMP_SENS_CTRL_32:
  605. case RT5682_HP_IMP_SENS_CTRL_33:
  606. case RT5682_HP_IMP_SENS_CTRL_34:
  607. case RT5682_HP_IMP_SENS_CTRL_35:
  608. case RT5682_HP_IMP_SENS_CTRL_36:
  609. case RT5682_HP_IMP_SENS_CTRL_37:
  610. case RT5682_HP_IMP_SENS_CTRL_38:
  611. case RT5682_HP_IMP_SENS_CTRL_39:
  612. case RT5682_HP_IMP_SENS_CTRL_40:
  613. case RT5682_HP_IMP_SENS_CTRL_41:
  614. case RT5682_HP_IMP_SENS_CTRL_42:
  615. case RT5682_HP_IMP_SENS_CTRL_43:
  616. case RT5682_HP_LOGIC_CTRL_1:
  617. case RT5682_HP_LOGIC_CTRL_2:
  618. case RT5682_HP_LOGIC_CTRL_3:
  619. case RT5682_HP_CALIB_CTRL_1:
  620. case RT5682_HP_CALIB_CTRL_2:
  621. case RT5682_HP_CALIB_CTRL_3:
  622. case RT5682_HP_CALIB_CTRL_4:
  623. case RT5682_HP_CALIB_CTRL_5:
  624. case RT5682_HP_CALIB_CTRL_6:
  625. case RT5682_HP_CALIB_CTRL_7:
  626. case RT5682_HP_CALIB_CTRL_9:
  627. case RT5682_HP_CALIB_CTRL_10:
  628. case RT5682_HP_CALIB_CTRL_11:
  629. case RT5682_HP_CALIB_STA_1:
  630. case RT5682_HP_CALIB_STA_2:
  631. case RT5682_HP_CALIB_STA_3:
  632. case RT5682_HP_CALIB_STA_4:
  633. case RT5682_HP_CALIB_STA_5:
  634. case RT5682_HP_CALIB_STA_6:
  635. case RT5682_HP_CALIB_STA_7:
  636. case RT5682_HP_CALIB_STA_8:
  637. case RT5682_HP_CALIB_STA_9:
  638. case RT5682_HP_CALIB_STA_10:
  639. case RT5682_HP_CALIB_STA_11:
  640. case RT5682_SAR_IL_CMD_1:
  641. case RT5682_SAR_IL_CMD_2:
  642. case RT5682_SAR_IL_CMD_3:
  643. case RT5682_SAR_IL_CMD_4:
  644. case RT5682_SAR_IL_CMD_5:
  645. case RT5682_SAR_IL_CMD_6:
  646. case RT5682_SAR_IL_CMD_7:
  647. case RT5682_SAR_IL_CMD_8:
  648. case RT5682_SAR_IL_CMD_9:
  649. case RT5682_SAR_IL_CMD_10:
  650. case RT5682_SAR_IL_CMD_11:
  651. case RT5682_SAR_IL_CMD_12:
  652. case RT5682_SAR_IL_CMD_13:
  653. case RT5682_EFUSE_CTRL_1:
  654. case RT5682_EFUSE_CTRL_2:
  655. case RT5682_EFUSE_CTRL_3:
  656. case RT5682_EFUSE_CTRL_4:
  657. case RT5682_EFUSE_CTRL_5:
  658. case RT5682_EFUSE_CTRL_6:
  659. case RT5682_EFUSE_CTRL_7:
  660. case RT5682_EFUSE_CTRL_8:
  661. case RT5682_EFUSE_CTRL_9:
  662. case RT5682_EFUSE_CTRL_10:
  663. case RT5682_EFUSE_CTRL_11:
  664. case RT5682_JD_TOP_VC_VTRL:
  665. case RT5682_DRC1_CTRL_0:
  666. case RT5682_DRC1_CTRL_1:
  667. case RT5682_DRC1_CTRL_2:
  668. case RT5682_DRC1_CTRL_3:
  669. case RT5682_DRC1_CTRL_4:
  670. case RT5682_DRC1_CTRL_5:
  671. case RT5682_DRC1_CTRL_6:
  672. case RT5682_DRC1_HARD_LMT_CTRL_1:
  673. case RT5682_DRC1_HARD_LMT_CTRL_2:
  674. case RT5682_DRC1_PRIV_1:
  675. case RT5682_DRC1_PRIV_2:
  676. case RT5682_DRC1_PRIV_3:
  677. case RT5682_DRC1_PRIV_4:
  678. case RT5682_DRC1_PRIV_5:
  679. case RT5682_DRC1_PRIV_6:
  680. case RT5682_DRC1_PRIV_7:
  681. case RT5682_DRC1_PRIV_8:
  682. case RT5682_EQ_AUTO_RCV_CTRL1:
  683. case RT5682_EQ_AUTO_RCV_CTRL2:
  684. case RT5682_EQ_AUTO_RCV_CTRL3:
  685. case RT5682_EQ_AUTO_RCV_CTRL4:
  686. case RT5682_EQ_AUTO_RCV_CTRL5:
  687. case RT5682_EQ_AUTO_RCV_CTRL6:
  688. case RT5682_EQ_AUTO_RCV_CTRL7:
  689. case RT5682_EQ_AUTO_RCV_CTRL8:
  690. case RT5682_EQ_AUTO_RCV_CTRL9:
  691. case RT5682_EQ_AUTO_RCV_CTRL10:
  692. case RT5682_EQ_AUTO_RCV_CTRL11:
  693. case RT5682_EQ_AUTO_RCV_CTRL12:
  694. case RT5682_EQ_AUTO_RCV_CTRL13:
  695. case RT5682_ADC_L_EQ_LPF1_A1:
  696. case RT5682_R_EQ_LPF1_A1:
  697. case RT5682_L_EQ_LPF1_H0:
  698. case RT5682_R_EQ_LPF1_H0:
  699. case RT5682_L_EQ_BPF1_A1:
  700. case RT5682_R_EQ_BPF1_A1:
  701. case RT5682_L_EQ_BPF1_A2:
  702. case RT5682_R_EQ_BPF1_A2:
  703. case RT5682_L_EQ_BPF1_H0:
  704. case RT5682_R_EQ_BPF1_H0:
  705. case RT5682_L_EQ_BPF2_A1:
  706. case RT5682_R_EQ_BPF2_A1:
  707. case RT5682_L_EQ_BPF2_A2:
  708. case RT5682_R_EQ_BPF2_A2:
  709. case RT5682_L_EQ_BPF2_H0:
  710. case RT5682_R_EQ_BPF2_H0:
  711. case RT5682_L_EQ_BPF3_A1:
  712. case RT5682_R_EQ_BPF3_A1:
  713. case RT5682_L_EQ_BPF3_A2:
  714. case RT5682_R_EQ_BPF3_A2:
  715. case RT5682_L_EQ_BPF3_H0:
  716. case RT5682_R_EQ_BPF3_H0:
  717. case RT5682_L_EQ_BPF4_A1:
  718. case RT5682_R_EQ_BPF4_A1:
  719. case RT5682_L_EQ_BPF4_A2:
  720. case RT5682_R_EQ_BPF4_A2:
  721. case RT5682_L_EQ_BPF4_H0:
  722. case RT5682_R_EQ_BPF4_H0:
  723. case RT5682_L_EQ_HPF1_A1:
  724. case RT5682_R_EQ_HPF1_A1:
  725. case RT5682_L_EQ_HPF1_H0:
  726. case RT5682_R_EQ_HPF1_H0:
  727. case RT5682_L_EQ_PRE_VOL:
  728. case RT5682_R_EQ_PRE_VOL:
  729. case RT5682_L_EQ_POST_VOL:
  730. case RT5682_R_EQ_POST_VOL:
  731. case RT5682_I2C_MODE:
  732. return true;
  733. default:
  734. return false;
  735. }
  736. }
  737. EXPORT_SYMBOL_GPL(rt5682_readable_register);
  738. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
  739. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
  740. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  741. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  742. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  743. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  744. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  745. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  746. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  747. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  748. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  749. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  750. );
  751. /* Interface data select */
  752. static const char * const rt5682_data_select[] = {
  753. "L/R", "R/L", "L/L", "R/R"
  754. };
  755. static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
  756. RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
  757. static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
  758. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
  759. static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
  760. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
  761. static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
  762. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
  763. static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
  764. RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
  765. static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
  766. SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
  767. static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
  768. SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
  769. static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
  770. SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
  771. static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
  772. SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
  773. static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
  774. SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
  775. static const char * const rt5682_dac_select[] = {
  776. "IF1", "SOUND"
  777. };
  778. static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
  779. RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
  780. static const struct snd_kcontrol_new rt5682_dac_l_mux =
  781. SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
  782. static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
  783. RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
  784. static const struct snd_kcontrol_new rt5682_dac_r_mux =
  785. SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
  786. void rt5682_reset(struct rt5682_priv *rt5682)
  787. {
  788. regmap_write(rt5682->regmap, RT5682_RESET, 0);
  789. if (!rt5682->is_sdw)
  790. regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
  791. }
  792. EXPORT_SYMBOL_GPL(rt5682_reset);
  793. /**
  794. * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
  795. * @component: SoC audio component device.
  796. * @filter_mask: mask of filters.
  797. * @clk_src: clock source
  798. *
  799. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
  800. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  801. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  802. * ASRC function will track i2s clock and generate a corresponding system clock
  803. * for codec. This function provides an API to select the clock source for a
  804. * set of filters specified by the mask. And the component driver will turn on
  805. * ASRC for these filters if ASRC is selected as their clock source.
  806. */
  807. int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
  808. unsigned int filter_mask, unsigned int clk_src)
  809. {
  810. switch (clk_src) {
  811. case RT5682_CLK_SEL_SYS:
  812. case RT5682_CLK_SEL_I2S1_ASRC:
  813. case RT5682_CLK_SEL_I2S2_ASRC:
  814. break;
  815. default:
  816. return -EINVAL;
  817. }
  818. if (filter_mask & RT5682_DA_STEREO1_FILTER) {
  819. snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
  820. RT5682_FILTER_CLK_SEL_MASK,
  821. clk_src << RT5682_FILTER_CLK_SEL_SFT);
  822. }
  823. if (filter_mask & RT5682_AD_STEREO1_FILTER) {
  824. snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
  825. RT5682_FILTER_CLK_SEL_MASK,
  826. clk_src << RT5682_FILTER_CLK_SEL_SFT);
  827. }
  828. return 0;
  829. }
  830. EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
  831. static int rt5682_button_detect(struct snd_soc_component *component)
  832. {
  833. int btn_type, val;
  834. val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
  835. btn_type = val & 0xfff0;
  836. snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
  837. dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
  838. snd_soc_component_update_bits(component,
  839. RT5682_SAR_IL_CMD_2, 0x10, 0x10);
  840. return btn_type;
  841. }
  842. static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
  843. bool enable)
  844. {
  845. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  846. if (enable) {
  847. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  848. RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
  849. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
  850. RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
  851. snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
  852. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  853. RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
  854. RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
  855. if (rt5682->is_sdw)
  856. snd_soc_component_update_bits(component,
  857. RT5682_IRQ_CTRL_3,
  858. RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
  859. RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
  860. else
  861. snd_soc_component_update_bits(component,
  862. RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
  863. RT5682_IL_IRQ_EN);
  864. } else {
  865. snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
  866. RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
  867. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  868. RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
  869. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  870. RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
  871. snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
  872. RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
  873. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
  874. RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
  875. }
  876. }
  877. /**
  878. * rt5682_headset_detect - Detect headset.
  879. * @component: SoC audio component device.
  880. * @jack_insert: Jack insert or not.
  881. *
  882. * Detect whether is headset or not when jack inserted.
  883. *
  884. * Returns detect status.
  885. */
  886. static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
  887. {
  888. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  889. struct snd_soc_dapm_context *dapm = &component->dapm;
  890. unsigned int val, count;
  891. if (jack_insert) {
  892. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  893. RT5682_PWR_VREF2 | RT5682_PWR_MB,
  894. RT5682_PWR_VREF2 | RT5682_PWR_MB);
  895. snd_soc_component_update_bits(component,
  896. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
  897. usleep_range(15000, 20000);
  898. snd_soc_component_update_bits(component,
  899. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
  900. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
  901. RT5682_PWR_CBJ, RT5682_PWR_CBJ);
  902. snd_soc_component_update_bits(component,
  903. RT5682_HP_CHARGE_PUMP_1,
  904. RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
  905. rt5682_enable_push_button_irq(component, false);
  906. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  907. RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
  908. usleep_range(55000, 60000);
  909. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  910. RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
  911. count = 0;
  912. val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
  913. & RT5682_JACK_TYPE_MASK;
  914. while (val == 0 && count < 50) {
  915. usleep_range(10000, 15000);
  916. val = snd_soc_component_read(component,
  917. RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
  918. count++;
  919. }
  920. switch (val) {
  921. case 0x1:
  922. case 0x2:
  923. rt5682->jack_type = SND_JACK_HEADSET;
  924. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  925. RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
  926. rt5682_enable_push_button_irq(component, true);
  927. break;
  928. default:
  929. rt5682->jack_type = SND_JACK_HEADPHONE;
  930. break;
  931. }
  932. snd_soc_component_update_bits(component,
  933. RT5682_HP_CHARGE_PUMP_1,
  934. RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
  935. RT5682_OSW_L_EN | RT5682_OSW_R_EN);
  936. snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
  937. RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
  938. RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
  939. } else {
  940. rt5682_enable_push_button_irq(component, false);
  941. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  942. RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
  943. if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
  944. !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
  945. !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
  946. snd_soc_component_update_bits(component,
  947. RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
  948. if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
  949. !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
  950. !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
  951. snd_soc_component_update_bits(component,
  952. RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
  953. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
  954. RT5682_PWR_CBJ, 0);
  955. snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
  956. RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
  957. RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
  958. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  959. RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
  960. rt5682->jack_type = 0;
  961. }
  962. dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
  963. return rt5682->jack_type;
  964. }
  965. static int rt5682_set_jack_detect(struct snd_soc_component *component,
  966. struct snd_soc_jack *hs_jack, void *data)
  967. {
  968. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  969. rt5682->hs_jack = hs_jack;
  970. if (!hs_jack) {
  971. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  972. RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
  973. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  974. RT5682_POW_JDH | RT5682_POW_JDL, 0);
  975. cancel_delayed_work_sync(&rt5682->jack_detect_work);
  976. return 0;
  977. }
  978. if (!rt5682->is_sdw) {
  979. switch (rt5682->pdata.jd_src) {
  980. case RT5682_JD1:
  981. snd_soc_component_update_bits(component,
  982. RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
  983. snd_soc_component_update_bits(component,
  984. RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
  985. RT5682_EXT_JD_SRC_MANUAL);
  986. snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
  987. 0xd142);
  988. snd_soc_component_update_bits(component,
  989. RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
  990. RT5682_CBJ_IN_BUF_EN);
  991. snd_soc_component_update_bits(component,
  992. RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
  993. RT5682_SAR_POW_EN);
  994. regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
  995. RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
  996. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  997. RT5682_POW_IRQ | RT5682_POW_JDH |
  998. RT5682_POW_ANA, RT5682_POW_IRQ |
  999. RT5682_POW_JDH | RT5682_POW_ANA);
  1000. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
  1001. RT5682_PWR_JDH, RT5682_PWR_JDH);
  1002. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  1003. RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
  1004. RT5682_JD1_EN | RT5682_JD1_POL_NOR);
  1005. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
  1006. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1007. rt5682->pdata.btndet_delay));
  1008. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
  1009. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1010. rt5682->pdata.btndet_delay));
  1011. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
  1012. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1013. rt5682->pdata.btndet_delay));
  1014. regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
  1015. 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
  1016. rt5682->pdata.btndet_delay));
  1017. mod_delayed_work(system_power_efficient_wq,
  1018. &rt5682->jack_detect_work,
  1019. msecs_to_jiffies(250));
  1020. break;
  1021. case RT5682_JD_NULL:
  1022. regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
  1023. RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
  1024. regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
  1025. RT5682_POW_JDH | RT5682_POW_JDL, 0);
  1026. break;
  1027. default:
  1028. dev_warn(component->dev, "Wrong JD source\n");
  1029. break;
  1030. }
  1031. }
  1032. return 0;
  1033. }
  1034. void rt5682_jack_detect_handler(struct work_struct *work)
  1035. {
  1036. struct rt5682_priv *rt5682 =
  1037. container_of(work, struct rt5682_priv, jack_detect_work.work);
  1038. struct snd_soc_dapm_context *dapm;
  1039. int val, btn_type;
  1040. if (!rt5682->component || !rt5682->component->card ||
  1041. !rt5682->component->card->instantiated) {
  1042. /* card not yet ready, try later */
  1043. mod_delayed_work(system_power_efficient_wq,
  1044. &rt5682->jack_detect_work, msecs_to_jiffies(15));
  1045. return;
  1046. }
  1047. if (rt5682->is_sdw) {
  1048. if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {
  1049. dev_dbg(&rt5682->slave->dev,
  1050. "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
  1051. __func__);
  1052. return;
  1053. }
  1054. }
  1055. dapm = snd_soc_component_get_dapm(rt5682->component);
  1056. snd_soc_dapm_mutex_lock(dapm);
  1057. mutex_lock(&rt5682->calibrate_mutex);
  1058. val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
  1059. & RT5682_JDH_RS_MASK;
  1060. if (!val) {
  1061. /* jack in */
  1062. if (rt5682->jack_type == 0) {
  1063. /* jack was out, report jack type */
  1064. rt5682->jack_type =
  1065. rt5682_headset_detect(rt5682->component, 1);
  1066. rt5682->irq_work_delay_time = 0;
  1067. } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
  1068. SND_JACK_HEADSET) {
  1069. /* jack is already in, report button event */
  1070. rt5682->jack_type = SND_JACK_HEADSET;
  1071. btn_type = rt5682_button_detect(rt5682->component);
  1072. /**
  1073. * rt5682 can report three kinds of button behavior,
  1074. * one click, double click and hold. However,
  1075. * currently we will report button pressed/released
  1076. * event. So all the three button behaviors are
  1077. * treated as button pressed.
  1078. */
  1079. switch (btn_type) {
  1080. case 0x8000:
  1081. case 0x4000:
  1082. case 0x2000:
  1083. rt5682->jack_type |= SND_JACK_BTN_0;
  1084. break;
  1085. case 0x1000:
  1086. case 0x0800:
  1087. case 0x0400:
  1088. rt5682->jack_type |= SND_JACK_BTN_1;
  1089. break;
  1090. case 0x0200:
  1091. case 0x0100:
  1092. case 0x0080:
  1093. rt5682->jack_type |= SND_JACK_BTN_2;
  1094. break;
  1095. case 0x0040:
  1096. case 0x0020:
  1097. case 0x0010:
  1098. rt5682->jack_type |= SND_JACK_BTN_3;
  1099. break;
  1100. case 0x0000: /* unpressed */
  1101. break;
  1102. default:
  1103. dev_err(rt5682->component->dev,
  1104. "Unexpected button code 0x%04x\n",
  1105. btn_type);
  1106. break;
  1107. }
  1108. }
  1109. } else {
  1110. /* jack out */
  1111. rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
  1112. rt5682->irq_work_delay_time = 50;
  1113. }
  1114. mutex_unlock(&rt5682->calibrate_mutex);
  1115. snd_soc_dapm_mutex_unlock(dapm);
  1116. snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
  1117. SND_JACK_HEADSET |
  1118. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1119. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  1120. if (!rt5682->is_sdw) {
  1121. if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1122. SND_JACK_BTN_2 | SND_JACK_BTN_3))
  1123. schedule_delayed_work(&rt5682->jd_check_work, 0);
  1124. else
  1125. cancel_delayed_work_sync(&rt5682->jd_check_work);
  1126. }
  1127. }
  1128. EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
  1129. static const struct snd_kcontrol_new rt5682_snd_controls[] = {
  1130. /* DAC Digital Volume */
  1131. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
  1132. RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
  1133. /* IN Boost Volume */
  1134. SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
  1135. RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
  1136. /* ADC Digital Volume Control */
  1137. SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
  1138. RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
  1139. SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
  1140. RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
  1141. /* ADC Boost Volume Control */
  1142. SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
  1143. RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
  1144. 3, 0, adc_bst_tlv),
  1145. };
  1146. static int rt5682_div_sel(struct rt5682_priv *rt5682,
  1147. int target, const int div[], int size)
  1148. {
  1149. int i;
  1150. if (rt5682->sysclk < target) {
  1151. dev_err(rt5682->component->dev,
  1152. "sysclk rate %d is too low\n", rt5682->sysclk);
  1153. return 0;
  1154. }
  1155. for (i = 0; i < size - 1; i++) {
  1156. dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
  1157. if (target * div[i] == rt5682->sysclk)
  1158. return i;
  1159. if (target * div[i + 1] > rt5682->sysclk) {
  1160. dev_dbg(rt5682->component->dev,
  1161. "can't find div for sysclk %d\n",
  1162. rt5682->sysclk);
  1163. return i;
  1164. }
  1165. }
  1166. if (target * div[i] < rt5682->sysclk)
  1167. dev_err(rt5682->component->dev,
  1168. "sysclk rate %d is too high\n", rt5682->sysclk);
  1169. return size - 1;
  1170. }
  1171. /**
  1172. * set_dmic_clk - Set parameter of dmic.
  1173. *
  1174. * @w: DAPM widget.
  1175. * @kcontrol: The kcontrol of this widget.
  1176. * @event: Event id.
  1177. *
  1178. * Choose dmic clock between 1MHz and 3MHz.
  1179. * It is better for clock to approximate 3MHz.
  1180. */
  1181. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  1182. struct snd_kcontrol *kcontrol, int event)
  1183. {
  1184. struct snd_soc_component *component =
  1185. snd_soc_dapm_to_component(w->dapm);
  1186. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1187. int idx, dmic_clk_rate = 3072000;
  1188. static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
  1189. if (rt5682->pdata.dmic_clk_rate)
  1190. dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
  1191. idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
  1192. snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
  1193. RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
  1194. return 0;
  1195. }
  1196. static int set_filter_clk(struct snd_soc_dapm_widget *w,
  1197. struct snd_kcontrol *kcontrol, int event)
  1198. {
  1199. struct snd_soc_component *component =
  1200. snd_soc_dapm_to_component(w->dapm);
  1201. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1202. int ref, val, reg, idx;
  1203. static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
  1204. static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
  1205. if (rt5682->is_sdw)
  1206. return 0;
  1207. val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
  1208. RT5682_GP4_PIN_MASK;
  1209. if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
  1210. val == RT5682_GP4_PIN_ADCDAT2)
  1211. ref = 256 * rt5682->lrck[RT5682_AIF2];
  1212. else
  1213. ref = 256 * rt5682->lrck[RT5682_AIF1];
  1214. idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
  1215. if (w->shift == RT5682_PWR_ADC_S1F_BIT)
  1216. reg = RT5682_PLL_TRACK_3;
  1217. else
  1218. reg = RT5682_PLL_TRACK_2;
  1219. snd_soc_component_update_bits(component, reg,
  1220. RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
  1221. /* select over sample rate */
  1222. for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
  1223. if (rt5682->sysclk <= 12288000 * div_o[idx])
  1224. break;
  1225. }
  1226. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
  1227. RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
  1228. (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
  1229. return 0;
  1230. }
  1231. static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
  1232. struct snd_soc_dapm_widget *sink)
  1233. {
  1234. unsigned int val;
  1235. struct snd_soc_component *component =
  1236. snd_soc_dapm_to_component(w->dapm);
  1237. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1238. val &= RT5682_SCLK_SRC_MASK;
  1239. if (val == RT5682_SCLK_SRC_PLL1)
  1240. return 1;
  1241. else
  1242. return 0;
  1243. }
  1244. static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
  1245. struct snd_soc_dapm_widget *sink)
  1246. {
  1247. unsigned int val;
  1248. struct snd_soc_component *component =
  1249. snd_soc_dapm_to_component(w->dapm);
  1250. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1251. val &= RT5682_SCLK_SRC_MASK;
  1252. if (val == RT5682_SCLK_SRC_PLL2)
  1253. return 1;
  1254. else
  1255. return 0;
  1256. }
  1257. static int is_using_asrc(struct snd_soc_dapm_widget *w,
  1258. struct snd_soc_dapm_widget *sink)
  1259. {
  1260. unsigned int reg, shift, val;
  1261. struct snd_soc_component *component =
  1262. snd_soc_dapm_to_component(w->dapm);
  1263. switch (w->shift) {
  1264. case RT5682_ADC_STO1_ASRC_SFT:
  1265. reg = RT5682_PLL_TRACK_3;
  1266. shift = RT5682_FILTER_CLK_SEL_SFT;
  1267. break;
  1268. case RT5682_DAC_STO1_ASRC_SFT:
  1269. reg = RT5682_PLL_TRACK_2;
  1270. shift = RT5682_FILTER_CLK_SEL_SFT;
  1271. break;
  1272. default:
  1273. return 0;
  1274. }
  1275. val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
  1276. switch (val) {
  1277. case RT5682_CLK_SEL_I2S1_ASRC:
  1278. case RT5682_CLK_SEL_I2S2_ASRC:
  1279. return 1;
  1280. default:
  1281. return 0;
  1282. }
  1283. }
  1284. /* Digital Mixer */
  1285. static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
  1286. SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
  1287. RT5682_M_STO1_ADC_L1_SFT, 1, 1),
  1288. SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
  1289. RT5682_M_STO1_ADC_L2_SFT, 1, 1),
  1290. };
  1291. static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
  1292. SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
  1293. RT5682_M_STO1_ADC_R1_SFT, 1, 1),
  1294. SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
  1295. RT5682_M_STO1_ADC_R2_SFT, 1, 1),
  1296. };
  1297. static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
  1298. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
  1299. RT5682_M_ADCMIX_L_SFT, 1, 1),
  1300. SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
  1301. RT5682_M_DAC1_L_SFT, 1, 1),
  1302. };
  1303. static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
  1304. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
  1305. RT5682_M_ADCMIX_R_SFT, 1, 1),
  1306. SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
  1307. RT5682_M_DAC1_R_SFT, 1, 1),
  1308. };
  1309. static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
  1310. SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
  1311. RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
  1312. SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
  1313. RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
  1314. };
  1315. static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
  1316. SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
  1317. RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
  1318. SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
  1319. RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
  1320. };
  1321. /* Analog Input Mixer */
  1322. static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
  1323. SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
  1324. RT5682_M_CBJ_RM1_L_SFT, 1, 1),
  1325. };
  1326. /* STO1 ADC1 Source */
  1327. /* MX-26 [13] [5] */
  1328. static const char * const rt5682_sto1_adc1_src[] = {
  1329. "DAC MIX", "ADC"
  1330. };
  1331. static SOC_ENUM_SINGLE_DECL(
  1332. rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
  1333. RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
  1334. static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
  1335. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
  1336. static SOC_ENUM_SINGLE_DECL(
  1337. rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
  1338. RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
  1339. static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
  1340. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
  1341. /* STO1 ADC Source */
  1342. /* MX-26 [11:10] [3:2] */
  1343. static const char * const rt5682_sto1_adc_src[] = {
  1344. "ADC1 L", "ADC1 R"
  1345. };
  1346. static SOC_ENUM_SINGLE_DECL(
  1347. rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
  1348. RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
  1349. static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
  1350. SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
  1351. static SOC_ENUM_SINGLE_DECL(
  1352. rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
  1353. RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
  1354. static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
  1355. SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
  1356. /* STO1 ADC2 Source */
  1357. /* MX-26 [12] [4] */
  1358. static const char * const rt5682_sto1_adc2_src[] = {
  1359. "DAC MIX", "DMIC"
  1360. };
  1361. static SOC_ENUM_SINGLE_DECL(
  1362. rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
  1363. RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
  1364. static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
  1365. SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
  1366. static SOC_ENUM_SINGLE_DECL(
  1367. rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
  1368. RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
  1369. static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
  1370. SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
  1371. /* MX-79 [6:4] I2S1 ADC data location */
  1372. static const unsigned int rt5682_if1_adc_slot_values[] = {
  1373. 0,
  1374. 2,
  1375. 4,
  1376. 6,
  1377. };
  1378. static const char * const rt5682_if1_adc_slot_src[] = {
  1379. "Slot 0", "Slot 2", "Slot 4", "Slot 6"
  1380. };
  1381. static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
  1382. RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
  1383. rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
  1384. static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
  1385. SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
  1386. /* Analog DAC L1 Source, Analog DAC R1 Source*/
  1387. /* MX-2B [4], MX-2B [0]*/
  1388. static const char * const rt5682_alg_dac1_src[] = {
  1389. "Stereo1 DAC Mixer", "DAC1"
  1390. };
  1391. static SOC_ENUM_SINGLE_DECL(
  1392. rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
  1393. RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
  1394. static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
  1395. SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
  1396. static SOC_ENUM_SINGLE_DECL(
  1397. rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
  1398. RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
  1399. static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
  1400. SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
  1401. /* Out Switch */
  1402. static const struct snd_kcontrol_new hpol_switch =
  1403. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
  1404. RT5682_L_MUTE_SFT, 1, 1);
  1405. static const struct snd_kcontrol_new hpor_switch =
  1406. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
  1407. RT5682_R_MUTE_SFT, 1, 1);
  1408. static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
  1409. struct snd_kcontrol *kcontrol, int event)
  1410. {
  1411. struct snd_soc_component *component =
  1412. snd_soc_dapm_to_component(w->dapm);
  1413. switch (event) {
  1414. case SND_SOC_DAPM_PRE_PMU:
  1415. snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
  1416. RT5682_HP_C2_DAC_AMP_MUTE, 0);
  1417. snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
  1418. RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
  1419. snd_soc_component_update_bits(component,
  1420. RT5682_DEPOP_1, 0x60, 0x60);
  1421. snd_soc_component_update_bits(component,
  1422. RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
  1423. snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
  1424. RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
  1425. RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
  1426. usleep_range(5000, 10000);
  1427. snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
  1428. RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
  1429. break;
  1430. case SND_SOC_DAPM_POST_PMD:
  1431. snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
  1432. RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
  1433. snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
  1434. RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
  1435. snd_soc_component_update_bits(component,
  1436. RT5682_DEPOP_1, 0x60, 0x0);
  1437. snd_soc_component_update_bits(component,
  1438. RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
  1439. break;
  1440. }
  1441. return 0;
  1442. }
  1443. static int set_dmic_power(struct snd_soc_dapm_widget *w,
  1444. struct snd_kcontrol *kcontrol, int event)
  1445. {
  1446. struct snd_soc_component *component =
  1447. snd_soc_dapm_to_component(w->dapm);
  1448. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1449. unsigned int delay = 50, val;
  1450. if (rt5682->pdata.dmic_delay)
  1451. delay = rt5682->pdata.dmic_delay;
  1452. switch (event) {
  1453. case SND_SOC_DAPM_POST_PMU:
  1454. val = snd_soc_component_read(component, RT5682_GLB_CLK);
  1455. val &= RT5682_SCLK_SRC_MASK;
  1456. if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
  1457. snd_soc_component_update_bits(component,
  1458. RT5682_PWR_ANLG_1,
  1459. RT5682_PWR_VREF2 | RT5682_PWR_MB,
  1460. RT5682_PWR_VREF2 | RT5682_PWR_MB);
  1461. /*Add delay to avoid pop noise*/
  1462. msleep(delay);
  1463. break;
  1464. case SND_SOC_DAPM_POST_PMD:
  1465. if (!rt5682->jack_type) {
  1466. if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
  1467. snd_soc_component_update_bits(component,
  1468. RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
  1469. if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
  1470. snd_soc_component_update_bits(component,
  1471. RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
  1472. }
  1473. break;
  1474. }
  1475. return 0;
  1476. }
  1477. static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
  1478. struct snd_kcontrol *kcontrol, int event)
  1479. {
  1480. struct snd_soc_component *component =
  1481. snd_soc_dapm_to_component(w->dapm);
  1482. switch (event) {
  1483. case SND_SOC_DAPM_PRE_PMU:
  1484. switch (w->shift) {
  1485. case RT5682_PWR_VREF1_BIT:
  1486. snd_soc_component_update_bits(component,
  1487. RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
  1488. break;
  1489. case RT5682_PWR_VREF2_BIT:
  1490. snd_soc_component_update_bits(component,
  1491. RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
  1492. break;
  1493. }
  1494. break;
  1495. case SND_SOC_DAPM_POST_PMU:
  1496. usleep_range(15000, 20000);
  1497. switch (w->shift) {
  1498. case RT5682_PWR_VREF1_BIT:
  1499. snd_soc_component_update_bits(component,
  1500. RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
  1501. RT5682_PWR_FV1);
  1502. break;
  1503. case RT5682_PWR_VREF2_BIT:
  1504. snd_soc_component_update_bits(component,
  1505. RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
  1506. RT5682_PWR_FV2);
  1507. break;
  1508. }
  1509. break;
  1510. }
  1511. return 0;
  1512. }
  1513. static const unsigned int rt5682_adcdat_pin_values[] = {
  1514. 1,
  1515. 3,
  1516. };
  1517. static const char * const rt5682_adcdat_pin_select[] = {
  1518. "ADCDAT1",
  1519. "ADCDAT2",
  1520. };
  1521. static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
  1522. RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
  1523. rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
  1524. static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
  1525. SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
  1526. static const unsigned int rt5682_hpo_sig_out_values[] = {
  1527. 2,
  1528. 7,
  1529. };
  1530. static const char * const rt5682_hpo_sig_out_mode[] = {
  1531. "Legacy",
  1532. "OneBit",
  1533. };
  1534. static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
  1535. RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
  1536. rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
  1537. static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
  1538. SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
  1539. static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
  1540. SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
  1541. 0, NULL, 0),
  1542. SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
  1543. 0, NULL, 0),
  1544. SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
  1545. 0, NULL, 0),
  1546. SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
  1547. 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
  1548. SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
  1549. rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1550. SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
  1551. SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
  1552. /* ASRC */
  1553. SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
  1554. RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
  1555. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
  1556. RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
  1557. SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
  1558. RT5682_AD_ASRC_SFT, 0, NULL, 0),
  1559. SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
  1560. RT5682_DA_ASRC_SFT, 0, NULL, 0),
  1561. SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
  1562. RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
  1563. /* Input Side */
  1564. SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
  1565. 0, NULL, 0),
  1566. SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
  1567. 0, NULL, 0),
  1568. /* Input Lines */
  1569. SND_SOC_DAPM_INPUT("DMIC L1"),
  1570. SND_SOC_DAPM_INPUT("DMIC R1"),
  1571. SND_SOC_DAPM_INPUT("IN1P"),
  1572. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  1573. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  1574. SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
  1575. RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
  1576. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1577. /* Boost */
  1578. SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
  1579. 0, 0, NULL, 0),
  1580. /* REC Mixer */
  1581. SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
  1582. ARRAY_SIZE(rt5682_rec1_l_mix)),
  1583. SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
  1584. RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
  1585. /* ADCs */
  1586. SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
  1587. SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
  1588. SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
  1589. RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
  1590. SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
  1591. RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
  1592. SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
  1593. RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
  1594. /* ADC Mux */
  1595. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  1596. &rt5682_sto1_adc1l_mux),
  1597. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  1598. &rt5682_sto1_adc1r_mux),
  1599. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  1600. &rt5682_sto1_adc2l_mux),
  1601. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  1602. &rt5682_sto1_adc2r_mux),
  1603. SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
  1604. &rt5682_sto1_adcl_mux),
  1605. SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
  1606. &rt5682_sto1_adcr_mux),
  1607. SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
  1608. &rt5682_if1_adc_slot_mux),
  1609. /* ADC Mixer */
  1610. SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
  1611. RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
  1612. SND_SOC_DAPM_PRE_PMU),
  1613. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
  1614. RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
  1615. ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
  1616. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
  1617. RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
  1618. ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
  1619. /* ADC PGA */
  1620. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  1621. /* Digital Interface */
  1622. SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
  1623. 0, NULL, 0),
  1624. SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
  1625. 0, NULL, 0),
  1626. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1627. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1628. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1629. SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1630. SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1631. /* Digital Interface Select */
  1632. SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1633. &rt5682_if1_01_adc_swap_mux),
  1634. SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1635. &rt5682_if1_23_adc_swap_mux),
  1636. SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1637. &rt5682_if1_45_adc_swap_mux),
  1638. SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1639. &rt5682_if1_67_adc_swap_mux),
  1640. SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1641. &rt5682_if2_adc_swap_mux),
  1642. SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
  1643. &rt5682_adcdat_pin_ctrl),
  1644. SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
  1645. &rt5682_dac_l_mux),
  1646. SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
  1647. &rt5682_dac_r_mux),
  1648. /* Audio Interface */
  1649. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
  1650. RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
  1651. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
  1652. RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
  1653. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  1654. SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
  1655. SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
  1656. /* Output Side */
  1657. /* DAC mixer before sound effect */
  1658. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  1659. rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
  1660. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  1661. rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
  1662. /* DAC channel Mux */
  1663. SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
  1664. &rt5682_alg_dac_l1_mux),
  1665. SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
  1666. &rt5682_alg_dac_r1_mux),
  1667. /* DAC Mixer */
  1668. SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
  1669. RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
  1670. SND_SOC_DAPM_PRE_PMU),
  1671. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
  1672. rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
  1673. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
  1674. rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
  1675. /* DACs */
  1676. SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
  1677. RT5682_PWR_DAC_L1_BIT, 0),
  1678. SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
  1679. RT5682_PWR_DAC_R1_BIT, 0),
  1680. SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
  1681. RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
  1682. /* HPO */
  1683. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
  1684. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
  1685. SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
  1686. RT5682_PWR_HA_L_BIT, 0, NULL, 0),
  1687. SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
  1688. RT5682_PWR_HA_R_BIT, 0, NULL, 0),
  1689. SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
  1690. RT5682_PUMP_EN_SFT, 0, NULL, 0),
  1691. SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
  1692. RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
  1693. SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
  1694. &hpol_switch),
  1695. SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
  1696. &hpor_switch),
  1697. SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
  1698. SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
  1699. SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
  1700. /* CLK DET */
  1701. SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
  1702. RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
  1703. SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
  1704. RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
  1705. SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
  1706. RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
  1707. SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
  1708. RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
  1709. /* Output Lines */
  1710. SND_SOC_DAPM_OUTPUT("HPOL"),
  1711. SND_SOC_DAPM_OUTPUT("HPOR"),
  1712. };
  1713. static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
  1714. /*PLL*/
  1715. {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1716. {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
  1717. {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
  1718. {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1719. {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
  1720. {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
  1721. /*ASRC*/
  1722. {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
  1723. {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
  1724. {"ADC STO1 ASRC", NULL, "AD ASRC"},
  1725. {"ADC STO1 ASRC", NULL, "DA ASRC"},
  1726. {"ADC STO1 ASRC", NULL, "CLKDET"},
  1727. {"DAC STO1 ASRC", NULL, "AD ASRC"},
  1728. {"DAC STO1 ASRC", NULL, "DA ASRC"},
  1729. {"DAC STO1 ASRC", NULL, "CLKDET"},
  1730. /*Vref*/
  1731. {"MICBIAS1", NULL, "Vref1"},
  1732. {"MICBIAS2", NULL, "Vref1"},
  1733. {"CLKDET SYS", NULL, "CLKDET"},
  1734. {"BST1 CBJ", NULL, "IN1P"},
  1735. {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
  1736. {"RECMIX1L", NULL, "RECMIX1L Power"},
  1737. {"ADC1 L", NULL, "RECMIX1L"},
  1738. {"ADC1 L", NULL, "ADC1 L Power"},
  1739. {"ADC1 L", NULL, "ADC1 clock"},
  1740. {"DMIC L1", NULL, "DMIC CLK"},
  1741. {"DMIC L1", NULL, "DMIC1 Power"},
  1742. {"DMIC R1", NULL, "DMIC CLK"},
  1743. {"DMIC R1", NULL, "DMIC1 Power"},
  1744. {"DMIC CLK", NULL, "DMIC ASRC"},
  1745. {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
  1746. {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
  1747. {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
  1748. {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
  1749. {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
  1750. {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1751. {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
  1752. {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1753. {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
  1754. {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1755. {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
  1756. {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1757. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  1758. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  1759. {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
  1760. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  1761. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  1762. {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
  1763. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
  1764. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
  1765. {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1766. {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1767. {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1768. {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1769. {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1770. {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1771. {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1772. {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1773. {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1774. {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1775. {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1776. {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1777. {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1778. {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1779. {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1780. {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1781. {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
  1782. {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
  1783. {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
  1784. {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
  1785. {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
  1786. {"AIF1TX", NULL, "I2S1"},
  1787. {"AIF1TX", NULL, "ADCDAT Mux"},
  1788. {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1789. {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1790. {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1791. {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1792. {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
  1793. {"AIF2TX", NULL, "ADCDAT Mux"},
  1794. {"SDWTX", NULL, "PLL2B"},
  1795. {"SDWTX", NULL, "PLL2F"},
  1796. {"SDWTX", NULL, "ADCDAT Mux"},
  1797. {"IF1 DAC1 L", NULL, "AIF1RX"},
  1798. {"IF1 DAC1 L", NULL, "I2S1"},
  1799. {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
  1800. {"IF1 DAC1 R", NULL, "AIF1RX"},
  1801. {"IF1 DAC1 R", NULL, "I2S1"},
  1802. {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
  1803. {"SOUND DAC L", NULL, "SDWRX"},
  1804. {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
  1805. {"SOUND DAC L", NULL, "PLL2B"},
  1806. {"SOUND DAC L", NULL, "PLL2F"},
  1807. {"SOUND DAC R", NULL, "SDWRX"},
  1808. {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
  1809. {"SOUND DAC R", NULL, "PLL2B"},
  1810. {"SOUND DAC R", NULL, "PLL2F"},
  1811. {"DAC L Mux", "IF1", "IF1 DAC1 L"},
  1812. {"DAC L Mux", "SOUND", "SOUND DAC L"},
  1813. {"DAC R Mux", "IF1", "IF1 DAC1 R"},
  1814. {"DAC R Mux", "SOUND", "SOUND DAC R"},
  1815. {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  1816. {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
  1817. {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  1818. {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
  1819. {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  1820. {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
  1821. {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  1822. {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
  1823. {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
  1824. {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
  1825. {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
  1826. {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
  1827. {"DAC L1", NULL, "DAC L1 Source"},
  1828. {"DAC R1", NULL, "DAC R1 Source"},
  1829. {"DAC L1", NULL, "DAC 1 Clock"},
  1830. {"DAC R1", NULL, "DAC 1 Clock"},
  1831. {"HP Amp", NULL, "DAC L1"},
  1832. {"HP Amp", NULL, "DAC R1"},
  1833. {"HP Amp", NULL, "HP Amp L"},
  1834. {"HP Amp", NULL, "HP Amp R"},
  1835. {"HP Amp", NULL, "Capless"},
  1836. {"HP Amp", NULL, "Charge Pump"},
  1837. {"HP Amp", NULL, "CLKDET SYS"},
  1838. {"HP Amp", NULL, "Vref1"},
  1839. {"HPO Signal Demux", NULL, "HP Amp"},
  1840. {"HPO Legacy", "Legacy", "HPO Signal Demux"},
  1841. {"HPO OneBit", "OneBit", "HPO Signal Demux"},
  1842. {"HPOL Playback", "Switch", "HPO Legacy"},
  1843. {"HPOR Playback", "Switch", "HPO Legacy"},
  1844. {"HPOL", NULL, "HPOL Playback"},
  1845. {"HPOR", NULL, "HPOR Playback"},
  1846. {"HPOL", NULL, "HPO OneBit"},
  1847. {"HPOR", NULL, "HPO OneBit"},
  1848. };
  1849. static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1850. unsigned int rx_mask, int slots, int slot_width)
  1851. {
  1852. struct snd_soc_component *component = dai->component;
  1853. unsigned int cl, val = 0;
  1854. if (tx_mask || rx_mask)
  1855. snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
  1856. RT5682_TDM_EN, RT5682_TDM_EN);
  1857. else
  1858. snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
  1859. RT5682_TDM_EN, 0);
  1860. switch (slots) {
  1861. case 4:
  1862. val |= RT5682_TDM_TX_CH_4;
  1863. val |= RT5682_TDM_RX_CH_4;
  1864. break;
  1865. case 6:
  1866. val |= RT5682_TDM_TX_CH_6;
  1867. val |= RT5682_TDM_RX_CH_6;
  1868. break;
  1869. case 8:
  1870. val |= RT5682_TDM_TX_CH_8;
  1871. val |= RT5682_TDM_RX_CH_8;
  1872. break;
  1873. case 2:
  1874. break;
  1875. default:
  1876. return -EINVAL;
  1877. }
  1878. snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
  1879. RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
  1880. switch (slot_width) {
  1881. case 8:
  1882. if (tx_mask || rx_mask)
  1883. return -EINVAL;
  1884. cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
  1885. break;
  1886. case 16:
  1887. val = RT5682_TDM_CL_16;
  1888. cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
  1889. break;
  1890. case 20:
  1891. val = RT5682_TDM_CL_20;
  1892. cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
  1893. break;
  1894. case 24:
  1895. val = RT5682_TDM_CL_24;
  1896. cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
  1897. break;
  1898. case 32:
  1899. val = RT5682_TDM_CL_32;
  1900. cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
  1901. break;
  1902. default:
  1903. return -EINVAL;
  1904. }
  1905. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  1906. RT5682_TDM_CL_MASK, val);
  1907. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  1908. RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
  1909. return 0;
  1910. }
  1911. static int rt5682_hw_params(struct snd_pcm_substream *substream,
  1912. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1913. {
  1914. struct snd_soc_component *component = dai->component;
  1915. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1916. unsigned int len_1 = 0, len_2 = 0;
  1917. int pre_div, frame_size;
  1918. rt5682->lrck[dai->id] = params_rate(params);
  1919. pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
  1920. frame_size = snd_soc_params_to_frame_size(params);
  1921. if (frame_size < 0) {
  1922. dev_err(component->dev, "Unsupported frame size: %d\n",
  1923. frame_size);
  1924. return -EINVAL;
  1925. }
  1926. dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  1927. rt5682->lrck[dai->id], pre_div, dai->id);
  1928. switch (params_width(params)) {
  1929. case 16:
  1930. break;
  1931. case 20:
  1932. len_1 |= RT5682_I2S1_DL_20;
  1933. len_2 |= RT5682_I2S2_DL_20;
  1934. break;
  1935. case 24:
  1936. len_1 |= RT5682_I2S1_DL_24;
  1937. len_2 |= RT5682_I2S2_DL_24;
  1938. break;
  1939. case 32:
  1940. len_1 |= RT5682_I2S1_DL_32;
  1941. len_2 |= RT5682_I2S2_DL_24;
  1942. break;
  1943. case 8:
  1944. len_1 |= RT5682_I2S2_DL_8;
  1945. len_2 |= RT5682_I2S2_DL_8;
  1946. break;
  1947. default:
  1948. return -EINVAL;
  1949. }
  1950. switch (dai->id) {
  1951. case RT5682_AIF1:
  1952. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  1953. RT5682_I2S1_DL_MASK, len_1);
  1954. if (rt5682->master[RT5682_AIF1]) {
  1955. snd_soc_component_update_bits(component,
  1956. RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
  1957. RT5682_I2S_CLK_SRC_MASK,
  1958. pre_div << RT5682_I2S_M_DIV_SFT |
  1959. (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
  1960. }
  1961. if (params_channels(params) == 1) /* mono mode */
  1962. snd_soc_component_update_bits(component,
  1963. RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
  1964. RT5682_I2S1_MONO_EN);
  1965. else
  1966. snd_soc_component_update_bits(component,
  1967. RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
  1968. RT5682_I2S1_MONO_DIS);
  1969. break;
  1970. case RT5682_AIF2:
  1971. snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
  1972. RT5682_I2S2_DL_MASK, len_2);
  1973. if (rt5682->master[RT5682_AIF2]) {
  1974. snd_soc_component_update_bits(component,
  1975. RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
  1976. pre_div << RT5682_I2S2_M_PD_SFT);
  1977. }
  1978. if (params_channels(params) == 1) /* mono mode */
  1979. snd_soc_component_update_bits(component,
  1980. RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
  1981. RT5682_I2S2_MONO_EN);
  1982. else
  1983. snd_soc_component_update_bits(component,
  1984. RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
  1985. RT5682_I2S2_MONO_DIS);
  1986. break;
  1987. default:
  1988. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  1989. return -EINVAL;
  1990. }
  1991. return 0;
  1992. }
  1993. static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1994. {
  1995. struct snd_soc_component *component = dai->component;
  1996. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  1997. unsigned int reg_val = 0, tdm_ctrl = 0;
  1998. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1999. case SND_SOC_DAIFMT_CBM_CFM:
  2000. rt5682->master[dai->id] = 1;
  2001. break;
  2002. case SND_SOC_DAIFMT_CBS_CFS:
  2003. rt5682->master[dai->id] = 0;
  2004. break;
  2005. default:
  2006. return -EINVAL;
  2007. }
  2008. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2009. case SND_SOC_DAIFMT_NB_NF:
  2010. break;
  2011. case SND_SOC_DAIFMT_IB_NF:
  2012. reg_val |= RT5682_I2S_BP_INV;
  2013. tdm_ctrl |= RT5682_TDM_S_BP_INV;
  2014. break;
  2015. case SND_SOC_DAIFMT_NB_IF:
  2016. if (dai->id == RT5682_AIF1)
  2017. tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
  2018. else
  2019. return -EINVAL;
  2020. break;
  2021. case SND_SOC_DAIFMT_IB_IF:
  2022. if (dai->id == RT5682_AIF1)
  2023. tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
  2024. RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
  2025. else
  2026. return -EINVAL;
  2027. break;
  2028. default:
  2029. return -EINVAL;
  2030. }
  2031. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2032. case SND_SOC_DAIFMT_I2S:
  2033. break;
  2034. case SND_SOC_DAIFMT_LEFT_J:
  2035. reg_val |= RT5682_I2S_DF_LEFT;
  2036. tdm_ctrl |= RT5682_TDM_DF_LEFT;
  2037. break;
  2038. case SND_SOC_DAIFMT_DSP_A:
  2039. reg_val |= RT5682_I2S_DF_PCM_A;
  2040. tdm_ctrl |= RT5682_TDM_DF_PCM_A;
  2041. break;
  2042. case SND_SOC_DAIFMT_DSP_B:
  2043. reg_val |= RT5682_I2S_DF_PCM_B;
  2044. tdm_ctrl |= RT5682_TDM_DF_PCM_B;
  2045. break;
  2046. default:
  2047. return -EINVAL;
  2048. }
  2049. switch (dai->id) {
  2050. case RT5682_AIF1:
  2051. snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
  2052. RT5682_I2S_DF_MASK, reg_val);
  2053. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2054. RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
  2055. RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
  2056. RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
  2057. tdm_ctrl | rt5682->master[dai->id]);
  2058. break;
  2059. case RT5682_AIF2:
  2060. if (rt5682->master[dai->id] == 0)
  2061. reg_val |= RT5682_I2S2_MS_S;
  2062. snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
  2063. RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
  2064. RT5682_I2S_DF_MASK, reg_val);
  2065. break;
  2066. default:
  2067. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  2068. return -EINVAL;
  2069. }
  2070. return 0;
  2071. }
  2072. static int rt5682_set_component_sysclk(struct snd_soc_component *component,
  2073. int clk_id, int source, unsigned int freq, int dir)
  2074. {
  2075. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2076. unsigned int reg_val = 0, src = 0;
  2077. if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
  2078. return 0;
  2079. switch (clk_id) {
  2080. case RT5682_SCLK_S_MCLK:
  2081. reg_val |= RT5682_SCLK_SRC_MCLK;
  2082. src = RT5682_CLK_SRC_MCLK;
  2083. break;
  2084. case RT5682_SCLK_S_PLL1:
  2085. reg_val |= RT5682_SCLK_SRC_PLL1;
  2086. src = RT5682_CLK_SRC_PLL1;
  2087. break;
  2088. case RT5682_SCLK_S_PLL2:
  2089. reg_val |= RT5682_SCLK_SRC_PLL2;
  2090. src = RT5682_CLK_SRC_PLL2;
  2091. break;
  2092. case RT5682_SCLK_S_RCCLK:
  2093. reg_val |= RT5682_SCLK_SRC_RCCLK;
  2094. src = RT5682_CLK_SRC_RCCLK;
  2095. break;
  2096. default:
  2097. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  2098. return -EINVAL;
  2099. }
  2100. snd_soc_component_update_bits(component, RT5682_GLB_CLK,
  2101. RT5682_SCLK_SRC_MASK, reg_val);
  2102. if (rt5682->master[RT5682_AIF2]) {
  2103. snd_soc_component_update_bits(component,
  2104. RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
  2105. src << RT5682_I2S2_SRC_SFT);
  2106. }
  2107. rt5682->sysclk = freq;
  2108. rt5682->sysclk_src = clk_id;
  2109. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  2110. freq, clk_id);
  2111. return 0;
  2112. }
  2113. static int rt5682_set_component_pll(struct snd_soc_component *component,
  2114. int pll_id, int source, unsigned int freq_in,
  2115. unsigned int freq_out)
  2116. {
  2117. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2118. struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
  2119. unsigned int pll2_fout1, pll2_ps_val;
  2120. int ret;
  2121. if (source == rt5682->pll_src[pll_id] &&
  2122. freq_in == rt5682->pll_in[pll_id] &&
  2123. freq_out == rt5682->pll_out[pll_id])
  2124. return 0;
  2125. if (!freq_in || !freq_out) {
  2126. dev_dbg(component->dev, "PLL disabled\n");
  2127. rt5682->pll_in[pll_id] = 0;
  2128. rt5682->pll_out[pll_id] = 0;
  2129. snd_soc_component_update_bits(component, RT5682_GLB_CLK,
  2130. RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
  2131. return 0;
  2132. }
  2133. if (pll_id == RT5682_PLL2) {
  2134. switch (source) {
  2135. case RT5682_PLL2_S_MCLK:
  2136. snd_soc_component_update_bits(component,
  2137. RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
  2138. RT5682_PLL2_SRC_MCLK);
  2139. break;
  2140. default:
  2141. dev_err(component->dev, "Unknown PLL2 Source %d\n",
  2142. source);
  2143. return -EINVAL;
  2144. }
  2145. /**
  2146. * PLL2 concatenates 2 PLL units.
  2147. * We suggest the Fout of the front PLL is 3.84MHz.
  2148. */
  2149. pll2_fout1 = 3840000;
  2150. ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
  2151. if (ret < 0) {
  2152. dev_err(component->dev, "Unsupported input clock %d\n",
  2153. freq_in);
  2154. return ret;
  2155. }
  2156. dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
  2157. freq_in, pll2_fout1,
  2158. pll2f_code.m_bp,
  2159. (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
  2160. pll2f_code.n_code, pll2f_code.k_code);
  2161. ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
  2162. if (ret < 0) {
  2163. dev_err(component->dev, "Unsupported input clock %d\n",
  2164. pll2_fout1);
  2165. return ret;
  2166. }
  2167. dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
  2168. pll2_fout1, freq_out,
  2169. pll2b_code.m_bp,
  2170. (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
  2171. pll2b_code.n_code, pll2b_code.k_code);
  2172. snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
  2173. pll2f_code.k_code << RT5682_PLL2F_K_SFT |
  2174. pll2b_code.k_code << RT5682_PLL2B_K_SFT |
  2175. pll2b_code.m_code);
  2176. snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
  2177. pll2f_code.m_code << RT5682_PLL2F_M_SFT |
  2178. pll2b_code.n_code);
  2179. snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
  2180. pll2f_code.n_code << RT5682_PLL2F_N_SFT);
  2181. if (freq_out == 22579200)
  2182. pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
  2183. else
  2184. pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
  2185. snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
  2186. RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
  2187. RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
  2188. pll2_ps_val |
  2189. (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
  2190. (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
  2191. 0xf);
  2192. } else {
  2193. switch (source) {
  2194. case RT5682_PLL1_S_MCLK:
  2195. snd_soc_component_update_bits(component,
  2196. RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
  2197. RT5682_PLL1_SRC_MCLK);
  2198. break;
  2199. case RT5682_PLL1_S_BCLK1:
  2200. snd_soc_component_update_bits(component,
  2201. RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
  2202. RT5682_PLL1_SRC_BCLK1);
  2203. break;
  2204. default:
  2205. dev_err(component->dev, "Unknown PLL1 Source %d\n",
  2206. source);
  2207. return -EINVAL;
  2208. }
  2209. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  2210. if (ret < 0) {
  2211. dev_err(component->dev, "Unsupported input clock %d\n",
  2212. freq_in);
  2213. return ret;
  2214. }
  2215. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  2216. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  2217. pll_code.n_code, pll_code.k_code);
  2218. snd_soc_component_write(component, RT5682_PLL_CTRL_1,
  2219. (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
  2220. snd_soc_component_write(component, RT5682_PLL_CTRL_2,
  2221. ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
  2222. ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
  2223. }
  2224. rt5682->pll_in[pll_id] = freq_in;
  2225. rt5682->pll_out[pll_id] = freq_out;
  2226. rt5682->pll_src[pll_id] = source;
  2227. return 0;
  2228. }
  2229. static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  2230. {
  2231. struct snd_soc_component *component = dai->component;
  2232. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2233. rt5682->bclk[dai->id] = ratio;
  2234. switch (ratio) {
  2235. case 256:
  2236. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2237. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
  2238. break;
  2239. case 128:
  2240. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2241. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
  2242. break;
  2243. case 64:
  2244. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2245. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
  2246. break;
  2247. case 32:
  2248. snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
  2249. RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
  2250. break;
  2251. default:
  2252. dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
  2253. return -EINVAL;
  2254. }
  2255. return 0;
  2256. }
  2257. static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  2258. {
  2259. struct snd_soc_component *component = dai->component;
  2260. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2261. rt5682->bclk[dai->id] = ratio;
  2262. switch (ratio) {
  2263. case 64:
  2264. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
  2265. RT5682_I2S2_BCLK_MS2_MASK,
  2266. RT5682_I2S2_BCLK_MS2_64);
  2267. break;
  2268. case 32:
  2269. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
  2270. RT5682_I2S2_BCLK_MS2_MASK,
  2271. RT5682_I2S2_BCLK_MS2_32);
  2272. break;
  2273. default:
  2274. dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
  2275. return -EINVAL;
  2276. }
  2277. return 0;
  2278. }
  2279. static int rt5682_set_bias_level(struct snd_soc_component *component,
  2280. enum snd_soc_bias_level level)
  2281. {
  2282. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2283. switch (level) {
  2284. case SND_SOC_BIAS_PREPARE:
  2285. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
  2286. RT5682_PWR_BG, RT5682_PWR_BG);
  2287. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2288. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
  2289. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
  2290. break;
  2291. case SND_SOC_BIAS_STANDBY:
  2292. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2293. RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
  2294. break;
  2295. case SND_SOC_BIAS_OFF:
  2296. regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
  2297. RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
  2298. regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
  2299. RT5682_PWR_BG, 0);
  2300. break;
  2301. case SND_SOC_BIAS_ON:
  2302. break;
  2303. }
  2304. return 0;
  2305. }
  2306. #ifdef CONFIG_COMMON_CLK
  2307. #define CLK_PLL2_FIN 48000000
  2308. #define CLK_48 48000
  2309. #define CLK_44 44100
  2310. static bool rt5682_clk_check(struct rt5682_priv *rt5682)
  2311. {
  2312. if (!rt5682->master[RT5682_AIF1]) {
  2313. dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
  2314. return false;
  2315. }
  2316. return true;
  2317. }
  2318. static int rt5682_wclk_prepare(struct clk_hw *hw)
  2319. {
  2320. struct rt5682_priv *rt5682 =
  2321. container_of(hw, struct rt5682_priv,
  2322. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2323. struct snd_soc_component *component;
  2324. struct snd_soc_dapm_context *dapm;
  2325. if (!rt5682_clk_check(rt5682))
  2326. return -EINVAL;
  2327. component = rt5682->component;
  2328. dapm = snd_soc_component_get_dapm(component);
  2329. snd_soc_dapm_mutex_lock(dapm);
  2330. snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
  2331. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2332. RT5682_PWR_MB, RT5682_PWR_MB);
  2333. snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
  2334. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2335. RT5682_PWR_VREF2 | RT5682_PWR_FV2,
  2336. RT5682_PWR_VREF2);
  2337. usleep_range(55000, 60000);
  2338. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2339. RT5682_PWR_FV2, RT5682_PWR_FV2);
  2340. snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
  2341. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
  2342. snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
  2343. snd_soc_dapm_sync_unlocked(dapm);
  2344. snd_soc_dapm_mutex_unlock(dapm);
  2345. return 0;
  2346. }
  2347. static void rt5682_wclk_unprepare(struct clk_hw *hw)
  2348. {
  2349. struct rt5682_priv *rt5682 =
  2350. container_of(hw, struct rt5682_priv,
  2351. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2352. struct snd_soc_component *component;
  2353. struct snd_soc_dapm_context *dapm;
  2354. if (!rt5682_clk_check(rt5682))
  2355. return;
  2356. component = rt5682->component;
  2357. dapm = snd_soc_component_get_dapm(component);
  2358. snd_soc_dapm_mutex_lock(dapm);
  2359. snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
  2360. snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
  2361. if (!rt5682->jack_type)
  2362. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
  2363. RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
  2364. RT5682_PWR_MB, 0);
  2365. snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
  2366. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
  2367. snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
  2368. snd_soc_dapm_sync_unlocked(dapm);
  2369. snd_soc_dapm_mutex_unlock(dapm);
  2370. }
  2371. static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
  2372. unsigned long parent_rate)
  2373. {
  2374. struct rt5682_priv *rt5682 =
  2375. container_of(hw, struct rt5682_priv,
  2376. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2377. const char * const clk_name = clk_hw_get_name(hw);
  2378. if (!rt5682_clk_check(rt5682))
  2379. return 0;
  2380. /*
  2381. * Only accept to set wclk rate to 44.1k or 48kHz.
  2382. */
  2383. if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
  2384. rt5682->lrck[RT5682_AIF1] != CLK_44) {
  2385. dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
  2386. __func__, clk_name, CLK_44, CLK_48);
  2387. return 0;
  2388. }
  2389. return rt5682->lrck[RT5682_AIF1];
  2390. }
  2391. static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
  2392. unsigned long *parent_rate)
  2393. {
  2394. struct rt5682_priv *rt5682 =
  2395. container_of(hw, struct rt5682_priv,
  2396. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2397. const char * const clk_name = clk_hw_get_name(hw);
  2398. if (!rt5682_clk_check(rt5682))
  2399. return -EINVAL;
  2400. /*
  2401. * Only accept to set wclk rate to 44.1k or 48kHz.
  2402. * It will force to 48kHz if not both.
  2403. */
  2404. if (rate != CLK_48 && rate != CLK_44) {
  2405. dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
  2406. __func__, clk_name, CLK_44, CLK_48);
  2407. rate = CLK_48;
  2408. }
  2409. return rate;
  2410. }
  2411. static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
  2412. unsigned long parent_rate)
  2413. {
  2414. struct rt5682_priv *rt5682 =
  2415. container_of(hw, struct rt5682_priv,
  2416. dai_clks_hw[RT5682_DAI_WCLK_IDX]);
  2417. struct snd_soc_component *component;
  2418. struct clk_hw *parent_hw;
  2419. const char * const clk_name = clk_hw_get_name(hw);
  2420. int pre_div;
  2421. unsigned int clk_pll2_out;
  2422. if (!rt5682_clk_check(rt5682))
  2423. return -EINVAL;
  2424. component = rt5682->component;
  2425. /*
  2426. * Whether the wclk's parent clk (mclk) exists or not, please ensure
  2427. * it is fixed or set to 48MHz before setting wclk rate. It's a
  2428. * temporary limitation. Only accept 48MHz clk as the clk provider.
  2429. *
  2430. * It will set the codec anyway by assuming mclk is 48MHz.
  2431. */
  2432. parent_hw = clk_hw_get_parent(hw);
  2433. if (!parent_hw)
  2434. dev_warn(rt5682->i2c_dev,
  2435. "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
  2436. CLK_PLL2_FIN);
  2437. if (parent_rate != CLK_PLL2_FIN)
  2438. dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
  2439. clk_name, CLK_PLL2_FIN);
  2440. /*
  2441. * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
  2442. * PLL2 is needed.
  2443. */
  2444. clk_pll2_out = rate * 512;
  2445. rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
  2446. CLK_PLL2_FIN, clk_pll2_out);
  2447. rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
  2448. clk_pll2_out, SND_SOC_CLOCK_IN);
  2449. rt5682->lrck[RT5682_AIF1] = rate;
  2450. pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
  2451. snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
  2452. RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
  2453. pre_div << RT5682_I2S_M_DIV_SFT |
  2454. (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
  2455. return 0;
  2456. }
  2457. static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
  2458. unsigned long parent_rate)
  2459. {
  2460. struct rt5682_priv *rt5682 =
  2461. container_of(hw, struct rt5682_priv,
  2462. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2463. unsigned int bclks_per_wclk;
  2464. regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
  2465. switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
  2466. case RT5682_TDM_BCLK_MS1_256:
  2467. return parent_rate * 256;
  2468. case RT5682_TDM_BCLK_MS1_128:
  2469. return parent_rate * 128;
  2470. case RT5682_TDM_BCLK_MS1_64:
  2471. return parent_rate * 64;
  2472. case RT5682_TDM_BCLK_MS1_32:
  2473. return parent_rate * 32;
  2474. default:
  2475. return 0;
  2476. }
  2477. }
  2478. static unsigned long rt5682_bclk_get_factor(unsigned long rate,
  2479. unsigned long parent_rate)
  2480. {
  2481. unsigned long factor;
  2482. factor = rate / parent_rate;
  2483. if (factor < 64)
  2484. return 32;
  2485. else if (factor < 128)
  2486. return 64;
  2487. else if (factor < 256)
  2488. return 128;
  2489. else
  2490. return 256;
  2491. }
  2492. static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
  2493. unsigned long *parent_rate)
  2494. {
  2495. struct rt5682_priv *rt5682 =
  2496. container_of(hw, struct rt5682_priv,
  2497. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2498. unsigned long factor;
  2499. if (!*parent_rate || !rt5682_clk_check(rt5682))
  2500. return -EINVAL;
  2501. /*
  2502. * BCLK rates are set as a multiplier of WCLK in HW.
  2503. * We don't allow changing the parent WCLK. We just do
  2504. * some rounding down based on the parent WCLK rate
  2505. * and find the appropriate multiplier of BCLK to
  2506. * get the rounded down BCLK value.
  2507. */
  2508. factor = rt5682_bclk_get_factor(rate, *parent_rate);
  2509. return *parent_rate * factor;
  2510. }
  2511. static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
  2512. unsigned long parent_rate)
  2513. {
  2514. struct rt5682_priv *rt5682 =
  2515. container_of(hw, struct rt5682_priv,
  2516. dai_clks_hw[RT5682_DAI_BCLK_IDX]);
  2517. struct snd_soc_component *component;
  2518. struct snd_soc_dai *dai;
  2519. unsigned long factor;
  2520. if (!rt5682_clk_check(rt5682))
  2521. return -EINVAL;
  2522. component = rt5682->component;
  2523. factor = rt5682_bclk_get_factor(rate, parent_rate);
  2524. for_each_component_dais(component, dai)
  2525. if (dai->id == RT5682_AIF1)
  2526. return rt5682_set_bclk1_ratio(dai, factor);
  2527. dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
  2528. RT5682_AIF1);
  2529. return -ENODEV;
  2530. }
  2531. static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
  2532. [RT5682_DAI_WCLK_IDX] = {
  2533. .prepare = rt5682_wclk_prepare,
  2534. .unprepare = rt5682_wclk_unprepare,
  2535. .recalc_rate = rt5682_wclk_recalc_rate,
  2536. .round_rate = rt5682_wclk_round_rate,
  2537. .set_rate = rt5682_wclk_set_rate,
  2538. },
  2539. [RT5682_DAI_BCLK_IDX] = {
  2540. .recalc_rate = rt5682_bclk_recalc_rate,
  2541. .round_rate = rt5682_bclk_round_rate,
  2542. .set_rate = rt5682_bclk_set_rate,
  2543. },
  2544. };
  2545. int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
  2546. {
  2547. struct device *dev = rt5682->i2c_dev;
  2548. struct rt5682_platform_data *pdata = &rt5682->pdata;
  2549. struct clk_hw *dai_clk_hw;
  2550. int i, ret;
  2551. for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
  2552. struct clk_init_data init = { };
  2553. const struct clk_hw *parent;
  2554. dai_clk_hw = &rt5682->dai_clks_hw[i];
  2555. switch (i) {
  2556. case RT5682_DAI_WCLK_IDX:
  2557. /* Make MCLK the parent of WCLK */
  2558. if (rt5682->mclk) {
  2559. parent = __clk_get_hw(rt5682->mclk);
  2560. init.parent_hws = &parent;
  2561. init.num_parents = 1;
  2562. }
  2563. break;
  2564. case RT5682_DAI_BCLK_IDX:
  2565. /* Make WCLK the parent of BCLK */
  2566. parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
  2567. init.parent_hws = &parent;
  2568. init.num_parents = 1;
  2569. break;
  2570. default:
  2571. dev_err(dev, "Invalid clock index\n");
  2572. return -EINVAL;
  2573. }
  2574. init.name = pdata->dai_clk_names[i];
  2575. init.ops = &rt5682_dai_clk_ops[i];
  2576. init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
  2577. dai_clk_hw->init = &init;
  2578. ret = devm_clk_hw_register(dev, dai_clk_hw);
  2579. if (ret) {
  2580. dev_warn(dev, "Failed to register %s: %d\n",
  2581. init.name, ret);
  2582. return ret;
  2583. }
  2584. if (dev->of_node) {
  2585. devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
  2586. dai_clk_hw);
  2587. } else {
  2588. ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
  2589. init.name,
  2590. dev_name(dev));
  2591. if (ret)
  2592. return ret;
  2593. }
  2594. }
  2595. return 0;
  2596. }
  2597. EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
  2598. #endif /* CONFIG_COMMON_CLK */
  2599. static int rt5682_probe(struct snd_soc_component *component)
  2600. {
  2601. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2602. struct sdw_slave *slave;
  2603. unsigned long time;
  2604. struct snd_soc_dapm_context *dapm = &component->dapm;
  2605. rt5682->component = component;
  2606. if (rt5682->is_sdw) {
  2607. slave = rt5682->slave;
  2608. time = wait_for_completion_timeout(
  2609. &slave->initialization_complete,
  2610. msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
  2611. if (!time) {
  2612. dev_err(&slave->dev, "Initialization not complete, timed out\n");
  2613. return -ETIMEDOUT;
  2614. }
  2615. }
  2616. snd_soc_dapm_disable_pin(dapm, "MICBIAS");
  2617. snd_soc_dapm_disable_pin(dapm, "Vref2");
  2618. snd_soc_dapm_sync(dapm);
  2619. return 0;
  2620. }
  2621. static void rt5682_remove(struct snd_soc_component *component)
  2622. {
  2623. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2624. rt5682_reset(rt5682);
  2625. }
  2626. #ifdef CONFIG_PM
  2627. static int rt5682_suspend(struct snd_soc_component *component)
  2628. {
  2629. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2630. unsigned int val;
  2631. if (rt5682->is_sdw)
  2632. return 0;
  2633. if (rt5682->irq)
  2634. disable_irq(rt5682->irq);
  2635. cancel_delayed_work_sync(&rt5682->jack_detect_work);
  2636. cancel_delayed_work_sync(&rt5682->jd_check_work);
  2637. if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
  2638. val = snd_soc_component_read(component,
  2639. RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
  2640. switch (val) {
  2641. case 0x1:
  2642. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  2643. RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
  2644. RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
  2645. break;
  2646. case 0x2:
  2647. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  2648. RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
  2649. RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
  2650. break;
  2651. default:
  2652. break;
  2653. }
  2654. /* enter SAR ADC power saving mode */
  2655. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  2656. RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
  2657. RT5682_SAR_SEL_MB1_MB2_MASK, 0);
  2658. usleep_range(5000, 6000);
  2659. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  2660. RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
  2661. RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
  2662. usleep_range(10000, 12000);
  2663. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  2664. RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
  2665. RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
  2666. snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
  2667. RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
  2668. }
  2669. regcache_cache_only(rt5682->regmap, true);
  2670. regcache_mark_dirty(rt5682->regmap);
  2671. return 0;
  2672. }
  2673. static int rt5682_resume(struct snd_soc_component *component)
  2674. {
  2675. struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
  2676. if (rt5682->is_sdw)
  2677. return 0;
  2678. regcache_cache_only(rt5682->regmap, false);
  2679. regcache_sync(rt5682->regmap);
  2680. if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
  2681. snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
  2682. RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
  2683. RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
  2684. usleep_range(5000, 6000);
  2685. snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
  2686. RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
  2687. RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
  2688. snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
  2689. RT5682_PWR_CBJ, RT5682_PWR_CBJ);
  2690. }
  2691. rt5682->jack_type = 0;
  2692. mod_delayed_work(system_power_efficient_wq,
  2693. &rt5682->jack_detect_work, msecs_to_jiffies(0));
  2694. if (rt5682->irq)
  2695. enable_irq(rt5682->irq);
  2696. return 0;
  2697. }
  2698. #else
  2699. #define rt5682_suspend NULL
  2700. #define rt5682_resume NULL
  2701. #endif
  2702. const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
  2703. .hw_params = rt5682_hw_params,
  2704. .set_fmt = rt5682_set_dai_fmt,
  2705. .set_tdm_slot = rt5682_set_tdm_slot,
  2706. .set_bclk_ratio = rt5682_set_bclk1_ratio,
  2707. };
  2708. EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
  2709. const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
  2710. .hw_params = rt5682_hw_params,
  2711. .set_fmt = rt5682_set_dai_fmt,
  2712. .set_bclk_ratio = rt5682_set_bclk2_ratio,
  2713. };
  2714. EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
  2715. const struct snd_soc_component_driver rt5682_soc_component_dev = {
  2716. .probe = rt5682_probe,
  2717. .remove = rt5682_remove,
  2718. .suspend = rt5682_suspend,
  2719. .resume = rt5682_resume,
  2720. .set_bias_level = rt5682_set_bias_level,
  2721. .controls = rt5682_snd_controls,
  2722. .num_controls = ARRAY_SIZE(rt5682_snd_controls),
  2723. .dapm_widgets = rt5682_dapm_widgets,
  2724. .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
  2725. .dapm_routes = rt5682_dapm_routes,
  2726. .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
  2727. .set_sysclk = rt5682_set_component_sysclk,
  2728. .set_pll = rt5682_set_component_pll,
  2729. .set_jack = rt5682_set_jack_detect,
  2730. .use_pmdown_time = 1,
  2731. .endianness = 1,
  2732. };
  2733. EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
  2734. int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
  2735. {
  2736. device_property_read_u32(dev, "realtek,dmic1-data-pin",
  2737. &rt5682->pdata.dmic1_data_pin);
  2738. device_property_read_u32(dev, "realtek,dmic1-clk-pin",
  2739. &rt5682->pdata.dmic1_clk_pin);
  2740. device_property_read_u32(dev, "realtek,jd-src",
  2741. &rt5682->pdata.jd_src);
  2742. device_property_read_u32(dev, "realtek,btndet-delay",
  2743. &rt5682->pdata.btndet_delay);
  2744. device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
  2745. &rt5682->pdata.dmic_clk_rate);
  2746. device_property_read_u32(dev, "realtek,dmic-delay-ms",
  2747. &rt5682->pdata.dmic_delay);
  2748. rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
  2749. "realtek,ldo1-en-gpios", 0);
  2750. if (device_property_read_string_array(dev, "clock-output-names",
  2751. rt5682->pdata.dai_clk_names,
  2752. RT5682_DAI_NUM_CLKS) < 0)
  2753. dev_warn(dev, "Using default DAI clk names: %s, %s\n",
  2754. rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
  2755. rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
  2756. rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
  2757. "realtek,dmic-clk-driving-high");
  2758. return 0;
  2759. }
  2760. EXPORT_SYMBOL_GPL(rt5682_parse_dt);
  2761. void rt5682_calibrate(struct rt5682_priv *rt5682)
  2762. {
  2763. int value, count;
  2764. mutex_lock(&rt5682->calibrate_mutex);
  2765. rt5682_reset(rt5682);
  2766. regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
  2767. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
  2768. usleep_range(15000, 20000);
  2769. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
  2770. regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
  2771. regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
  2772. regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
  2773. regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
  2774. regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
  2775. regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
  2776. regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
  2777. regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
  2778. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
  2779. regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
  2780. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
  2781. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
  2782. regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
  2783. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
  2784. regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
  2785. for (count = 0; count < 60; count++) {
  2786. regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
  2787. if (!(value & 0x8000))
  2788. break;
  2789. usleep_range(10000, 10005);
  2790. }
  2791. if (count >= 60)
  2792. dev_err(rt5682->component->dev, "HP Calibration Failure\n");
  2793. /* restore settings */
  2794. regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
  2795. regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
  2796. regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
  2797. regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
  2798. regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
  2799. regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
  2800. regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
  2801. regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
  2802. mutex_unlock(&rt5682->calibrate_mutex);
  2803. }
  2804. EXPORT_SYMBOL_GPL(rt5682_calibrate);
  2805. MODULE_DESCRIPTION("ASoC RT5682 driver");
  2806. MODULE_AUTHOR("Bard Liao <[email protected]>");
  2807. MODULE_LICENSE("GPL v2");