rt5668.c 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5668.c -- RT5668B ALSA SoC audio component driver
  4. *
  5. * Copyright 2018 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <[email protected]>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/acpi.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/mutex.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/jack.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <sound/rt5668.h>
  30. #include "rl6231.h"
  31. #include "rt5668.h"
  32. #define RT5668_NUM_SUPPLIES 3
  33. static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = {
  34. "AVDD",
  35. "MICVDD",
  36. "VBAT",
  37. };
  38. struct rt5668_priv {
  39. struct snd_soc_component *component;
  40. struct rt5668_platform_data pdata;
  41. struct regmap *regmap;
  42. struct snd_soc_jack *hs_jack;
  43. struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES];
  44. struct delayed_work jack_detect_work;
  45. struct delayed_work jd_check_work;
  46. struct mutex calibrate_mutex;
  47. int sysclk;
  48. int sysclk_src;
  49. int lrck[RT5668_AIFS];
  50. int bclk[RT5668_AIFS];
  51. int master[RT5668_AIFS];
  52. int pll_src;
  53. int pll_in;
  54. int pll_out;
  55. int jack_type;
  56. };
  57. static const struct reg_default rt5668_reg[] = {
  58. {0x0002, 0x8080},
  59. {0x0003, 0x8000},
  60. {0x0005, 0x0000},
  61. {0x0006, 0x0000},
  62. {0x0008, 0x800f},
  63. {0x000b, 0x0000},
  64. {0x0010, 0x4040},
  65. {0x0011, 0x0000},
  66. {0x0012, 0x1404},
  67. {0x0013, 0x1000},
  68. {0x0014, 0xa00a},
  69. {0x0015, 0x0404},
  70. {0x0016, 0x0404},
  71. {0x0019, 0xafaf},
  72. {0x001c, 0x2f2f},
  73. {0x001f, 0x0000},
  74. {0x0022, 0x5757},
  75. {0x0023, 0x0039},
  76. {0x0024, 0x000b},
  77. {0x0026, 0xc0c4},
  78. {0x0029, 0x8080},
  79. {0x002a, 0xa0a0},
  80. {0x002b, 0x0300},
  81. {0x0030, 0x0000},
  82. {0x003c, 0x0080},
  83. {0x0044, 0x0c0c},
  84. {0x0049, 0x0000},
  85. {0x0061, 0x0000},
  86. {0x0062, 0x0000},
  87. {0x0063, 0x003f},
  88. {0x0064, 0x0000},
  89. {0x0065, 0x0000},
  90. {0x0066, 0x0030},
  91. {0x0067, 0x0000},
  92. {0x006b, 0x0000},
  93. {0x006c, 0x0000},
  94. {0x006d, 0x2200},
  95. {0x006e, 0x0a10},
  96. {0x0070, 0x8000},
  97. {0x0071, 0x8000},
  98. {0x0073, 0x0000},
  99. {0x0074, 0x0000},
  100. {0x0075, 0x0002},
  101. {0x0076, 0x0001},
  102. {0x0079, 0x0000},
  103. {0x007a, 0x0000},
  104. {0x007b, 0x0000},
  105. {0x007c, 0x0100},
  106. {0x007e, 0x0000},
  107. {0x0080, 0x0000},
  108. {0x0081, 0x0000},
  109. {0x0082, 0x0000},
  110. {0x0083, 0x0000},
  111. {0x0084, 0x0000},
  112. {0x0085, 0x0000},
  113. {0x0086, 0x0005},
  114. {0x0087, 0x0000},
  115. {0x0088, 0x0000},
  116. {0x008c, 0x0003},
  117. {0x008d, 0x0000},
  118. {0x008e, 0x0060},
  119. {0x008f, 0x1000},
  120. {0x0091, 0x0c26},
  121. {0x0092, 0x0073},
  122. {0x0093, 0x0000},
  123. {0x0094, 0x0080},
  124. {0x0098, 0x0000},
  125. {0x009a, 0x0000},
  126. {0x009b, 0x0000},
  127. {0x009c, 0x0000},
  128. {0x009d, 0x0000},
  129. {0x009e, 0x100c},
  130. {0x009f, 0x0000},
  131. {0x00a0, 0x0000},
  132. {0x00a3, 0x0002},
  133. {0x00a4, 0x0001},
  134. {0x00ae, 0x2040},
  135. {0x00af, 0x0000},
  136. {0x00b6, 0x0000},
  137. {0x00b7, 0x0000},
  138. {0x00b8, 0x0000},
  139. {0x00b9, 0x0002},
  140. {0x00be, 0x0000},
  141. {0x00c0, 0x0160},
  142. {0x00c1, 0x82a0},
  143. {0x00c2, 0x0000},
  144. {0x00d0, 0x0000},
  145. {0x00d1, 0x2244},
  146. {0x00d2, 0x3300},
  147. {0x00d3, 0x2200},
  148. {0x00d4, 0x0000},
  149. {0x00d9, 0x0009},
  150. {0x00da, 0x0000},
  151. {0x00db, 0x0000},
  152. {0x00dc, 0x00c0},
  153. {0x00dd, 0x2220},
  154. {0x00de, 0x3131},
  155. {0x00df, 0x3131},
  156. {0x00e0, 0x3131},
  157. {0x00e2, 0x0000},
  158. {0x00e3, 0x4000},
  159. {0x00e4, 0x0aa0},
  160. {0x00e5, 0x3131},
  161. {0x00e6, 0x3131},
  162. {0x00e7, 0x3131},
  163. {0x00e8, 0x3131},
  164. {0x00ea, 0xb320},
  165. {0x00eb, 0x0000},
  166. {0x00f0, 0x0000},
  167. {0x00f1, 0x00d0},
  168. {0x00f2, 0x00d0},
  169. {0x00f6, 0x0000},
  170. {0x00fa, 0x0000},
  171. {0x00fb, 0x0000},
  172. {0x00fc, 0x0000},
  173. {0x00fd, 0x0000},
  174. {0x00fe, 0x10ec},
  175. {0x00ff, 0x6530},
  176. {0x0100, 0xa0a0},
  177. {0x010b, 0x0000},
  178. {0x010c, 0xae00},
  179. {0x010d, 0xaaa0},
  180. {0x010e, 0x8aa2},
  181. {0x010f, 0x02a2},
  182. {0x0110, 0xc000},
  183. {0x0111, 0x04a2},
  184. {0x0112, 0x2800},
  185. {0x0113, 0x0000},
  186. {0x0117, 0x0100},
  187. {0x0125, 0x0410},
  188. {0x0132, 0x6026},
  189. {0x0136, 0x5555},
  190. {0x0138, 0x3700},
  191. {0x013a, 0x2000},
  192. {0x013b, 0x2000},
  193. {0x013c, 0x2005},
  194. {0x013f, 0x0000},
  195. {0x0142, 0x0000},
  196. {0x0145, 0x0002},
  197. {0x0146, 0x0000},
  198. {0x0147, 0x0000},
  199. {0x0148, 0x0000},
  200. {0x0149, 0x0000},
  201. {0x0150, 0x79a1},
  202. {0x0151, 0x0000},
  203. {0x0160, 0x4ec0},
  204. {0x0161, 0x0080},
  205. {0x0162, 0x0200},
  206. {0x0163, 0x0800},
  207. {0x0164, 0x0000},
  208. {0x0165, 0x0000},
  209. {0x0166, 0x0000},
  210. {0x0167, 0x000f},
  211. {0x0168, 0x000f},
  212. {0x0169, 0x0021},
  213. {0x0190, 0x413d},
  214. {0x0194, 0x0000},
  215. {0x0195, 0x0000},
  216. {0x0197, 0x0022},
  217. {0x0198, 0x0000},
  218. {0x0199, 0x0000},
  219. {0x01af, 0x0000},
  220. {0x01b0, 0x0400},
  221. {0x01b1, 0x0000},
  222. {0x01b2, 0x0000},
  223. {0x01b3, 0x0000},
  224. {0x01b4, 0x0000},
  225. {0x01b5, 0x0000},
  226. {0x01b6, 0x01c3},
  227. {0x01b7, 0x02a0},
  228. {0x01b8, 0x03e9},
  229. {0x01b9, 0x1389},
  230. {0x01ba, 0xc351},
  231. {0x01bb, 0x0009},
  232. {0x01bc, 0x0018},
  233. {0x01bd, 0x002a},
  234. {0x01be, 0x004c},
  235. {0x01bf, 0x0097},
  236. {0x01c0, 0x433d},
  237. {0x01c1, 0x2800},
  238. {0x01c2, 0x0000},
  239. {0x01c3, 0x0000},
  240. {0x01c4, 0x0000},
  241. {0x01c5, 0x0000},
  242. {0x01c6, 0x0000},
  243. {0x01c7, 0x0000},
  244. {0x01c8, 0x40af},
  245. {0x01c9, 0x0702},
  246. {0x01ca, 0x0000},
  247. {0x01cb, 0x0000},
  248. {0x01cc, 0x5757},
  249. {0x01cd, 0x5757},
  250. {0x01ce, 0x5757},
  251. {0x01cf, 0x5757},
  252. {0x01d0, 0x5757},
  253. {0x01d1, 0x5757},
  254. {0x01d2, 0x5757},
  255. {0x01d3, 0x5757},
  256. {0x01d4, 0x5757},
  257. {0x01d5, 0x5757},
  258. {0x01d6, 0x0000},
  259. {0x01d7, 0x0008},
  260. {0x01d8, 0x0029},
  261. {0x01d9, 0x3333},
  262. {0x01da, 0x0000},
  263. {0x01db, 0x0004},
  264. {0x01dc, 0x0000},
  265. {0x01de, 0x7c00},
  266. {0x01df, 0x0320},
  267. {0x01e0, 0x06a1},
  268. {0x01e1, 0x0000},
  269. {0x01e2, 0x0000},
  270. {0x01e3, 0x0000},
  271. {0x01e4, 0x0000},
  272. {0x01e6, 0x0001},
  273. {0x01e7, 0x0000},
  274. {0x01e8, 0x0000},
  275. {0x01ea, 0x0000},
  276. {0x01eb, 0x0000},
  277. {0x01ec, 0x0000},
  278. {0x01ed, 0x0000},
  279. {0x01ee, 0x0000},
  280. {0x01ef, 0x0000},
  281. {0x01f0, 0x0000},
  282. {0x01f1, 0x0000},
  283. {0x01f2, 0x0000},
  284. {0x01f3, 0x0000},
  285. {0x01f4, 0x0000},
  286. {0x0210, 0x6297},
  287. {0x0211, 0xa005},
  288. {0x0212, 0x824c},
  289. {0x0213, 0xf7ff},
  290. {0x0214, 0xf24c},
  291. {0x0215, 0x0102},
  292. {0x0216, 0x00a3},
  293. {0x0217, 0x0048},
  294. {0x0218, 0xa2c0},
  295. {0x0219, 0x0400},
  296. {0x021a, 0x00c8},
  297. {0x021b, 0x00c0},
  298. {0x021c, 0x0000},
  299. {0x0250, 0x4500},
  300. {0x0251, 0x40b3},
  301. {0x0252, 0x0000},
  302. {0x0253, 0x0000},
  303. {0x0254, 0x0000},
  304. {0x0255, 0x0000},
  305. {0x0256, 0x0000},
  306. {0x0257, 0x0000},
  307. {0x0258, 0x0000},
  308. {0x0259, 0x0000},
  309. {0x025a, 0x0005},
  310. {0x0270, 0x0000},
  311. {0x02ff, 0x0110},
  312. {0x0300, 0x001f},
  313. {0x0301, 0x032c},
  314. {0x0302, 0x5f21},
  315. {0x0303, 0x4000},
  316. {0x0304, 0x4000},
  317. {0x0305, 0x06d5},
  318. {0x0306, 0x8000},
  319. {0x0307, 0x0700},
  320. {0x0310, 0x4560},
  321. {0x0311, 0xa4a8},
  322. {0x0312, 0x7418},
  323. {0x0313, 0x0000},
  324. {0x0314, 0x0006},
  325. {0x0315, 0xffff},
  326. {0x0316, 0xc400},
  327. {0x0317, 0x0000},
  328. {0x03c0, 0x7e00},
  329. {0x03c1, 0x8000},
  330. {0x03c2, 0x8000},
  331. {0x03c3, 0x8000},
  332. {0x03c4, 0x8000},
  333. {0x03c5, 0x8000},
  334. {0x03c6, 0x8000},
  335. {0x03c7, 0x8000},
  336. {0x03c8, 0x8000},
  337. {0x03c9, 0x8000},
  338. {0x03ca, 0x8000},
  339. {0x03cb, 0x8000},
  340. {0x03cc, 0x8000},
  341. {0x03d0, 0x0000},
  342. {0x03d1, 0x0000},
  343. {0x03d2, 0x0000},
  344. {0x03d3, 0x0000},
  345. {0x03d4, 0x2000},
  346. {0x03d5, 0x2000},
  347. {0x03d6, 0x0000},
  348. {0x03d7, 0x0000},
  349. {0x03d8, 0x2000},
  350. {0x03d9, 0x2000},
  351. {0x03da, 0x2000},
  352. {0x03db, 0x2000},
  353. {0x03dc, 0x0000},
  354. {0x03dd, 0x0000},
  355. {0x03de, 0x0000},
  356. {0x03df, 0x2000},
  357. {0x03e0, 0x0000},
  358. {0x03e1, 0x0000},
  359. {0x03e2, 0x0000},
  360. {0x03e3, 0x0000},
  361. {0x03e4, 0x0000},
  362. {0x03e5, 0x0000},
  363. {0x03e6, 0x0000},
  364. {0x03e7, 0x0000},
  365. {0x03e8, 0x0000},
  366. {0x03e9, 0x0000},
  367. {0x03ea, 0x0000},
  368. {0x03eb, 0x0000},
  369. {0x03ec, 0x0000},
  370. {0x03ed, 0x0000},
  371. {0x03ee, 0x0000},
  372. {0x03ef, 0x0000},
  373. {0x03f0, 0x0800},
  374. {0x03f1, 0x0800},
  375. {0x03f2, 0x0800},
  376. {0x03f3, 0x0800},
  377. };
  378. static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
  379. {
  380. switch (reg) {
  381. case RT5668_RESET:
  382. case RT5668_CBJ_CTRL_2:
  383. case RT5668_INT_ST_1:
  384. case RT5668_4BTN_IL_CMD_1:
  385. case RT5668_AJD1_CTRL:
  386. case RT5668_HP_CALIB_CTRL_1:
  387. case RT5668_DEVICE_ID:
  388. case RT5668_I2C_MODE:
  389. case RT5668_HP_CALIB_CTRL_10:
  390. case RT5668_EFUSE_CTRL_2:
  391. case RT5668_JD_TOP_VC_VTRL:
  392. case RT5668_HP_IMP_SENS_CTRL_19:
  393. case RT5668_IL_CMD_1:
  394. case RT5668_SAR_IL_CMD_2:
  395. case RT5668_SAR_IL_CMD_4:
  396. case RT5668_SAR_IL_CMD_10:
  397. case RT5668_SAR_IL_CMD_11:
  398. case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11:
  399. case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11:
  400. return true;
  401. default:
  402. return false;
  403. }
  404. }
  405. static bool rt5668_readable_register(struct device *dev, unsigned int reg)
  406. {
  407. switch (reg) {
  408. case RT5668_RESET:
  409. case RT5668_VERSION_ID:
  410. case RT5668_VENDOR_ID:
  411. case RT5668_DEVICE_ID:
  412. case RT5668_HP_CTRL_1:
  413. case RT5668_HP_CTRL_2:
  414. case RT5668_HPL_GAIN:
  415. case RT5668_HPR_GAIN:
  416. case RT5668_I2C_CTRL:
  417. case RT5668_CBJ_BST_CTRL:
  418. case RT5668_CBJ_CTRL_1:
  419. case RT5668_CBJ_CTRL_2:
  420. case RT5668_CBJ_CTRL_3:
  421. case RT5668_CBJ_CTRL_4:
  422. case RT5668_CBJ_CTRL_5:
  423. case RT5668_CBJ_CTRL_6:
  424. case RT5668_CBJ_CTRL_7:
  425. case RT5668_DAC1_DIG_VOL:
  426. case RT5668_STO1_ADC_DIG_VOL:
  427. case RT5668_STO1_ADC_BOOST:
  428. case RT5668_HP_IMP_GAIN_1:
  429. case RT5668_HP_IMP_GAIN_2:
  430. case RT5668_SIDETONE_CTRL:
  431. case RT5668_STO1_ADC_MIXER:
  432. case RT5668_AD_DA_MIXER:
  433. case RT5668_STO1_DAC_MIXER:
  434. case RT5668_A_DAC1_MUX:
  435. case RT5668_DIG_INF2_DATA:
  436. case RT5668_REC_MIXER:
  437. case RT5668_CAL_REC:
  438. case RT5668_ALC_BACK_GAIN:
  439. case RT5668_PWR_DIG_1:
  440. case RT5668_PWR_DIG_2:
  441. case RT5668_PWR_ANLG_1:
  442. case RT5668_PWR_ANLG_2:
  443. case RT5668_PWR_ANLG_3:
  444. case RT5668_PWR_MIXER:
  445. case RT5668_PWR_VOL:
  446. case RT5668_CLK_DET:
  447. case RT5668_RESET_LPF_CTRL:
  448. case RT5668_RESET_HPF_CTRL:
  449. case RT5668_DMIC_CTRL_1:
  450. case RT5668_I2S1_SDP:
  451. case RT5668_I2S2_SDP:
  452. case RT5668_ADDA_CLK_1:
  453. case RT5668_ADDA_CLK_2:
  454. case RT5668_I2S1_F_DIV_CTRL_1:
  455. case RT5668_I2S1_F_DIV_CTRL_2:
  456. case RT5668_TDM_CTRL:
  457. case RT5668_TDM_ADDA_CTRL_1:
  458. case RT5668_TDM_ADDA_CTRL_2:
  459. case RT5668_DATA_SEL_CTRL_1:
  460. case RT5668_TDM_TCON_CTRL:
  461. case RT5668_GLB_CLK:
  462. case RT5668_PLL_CTRL_1:
  463. case RT5668_PLL_CTRL_2:
  464. case RT5668_PLL_TRACK_1:
  465. case RT5668_PLL_TRACK_2:
  466. case RT5668_PLL_TRACK_3:
  467. case RT5668_PLL_TRACK_4:
  468. case RT5668_PLL_TRACK_5:
  469. case RT5668_PLL_TRACK_6:
  470. case RT5668_PLL_TRACK_11:
  471. case RT5668_SDW_REF_CLK:
  472. case RT5668_DEPOP_1:
  473. case RT5668_DEPOP_2:
  474. case RT5668_HP_CHARGE_PUMP_1:
  475. case RT5668_HP_CHARGE_PUMP_2:
  476. case RT5668_MICBIAS_1:
  477. case RT5668_MICBIAS_2:
  478. case RT5668_PLL_TRACK_12:
  479. case RT5668_PLL_TRACK_14:
  480. case RT5668_PLL2_CTRL_1:
  481. case RT5668_PLL2_CTRL_2:
  482. case RT5668_PLL2_CTRL_3:
  483. case RT5668_PLL2_CTRL_4:
  484. case RT5668_RC_CLK_CTRL:
  485. case RT5668_I2S_M_CLK_CTRL_1:
  486. case RT5668_I2S2_F_DIV_CTRL_1:
  487. case RT5668_I2S2_F_DIV_CTRL_2:
  488. case RT5668_EQ_CTRL_1:
  489. case RT5668_EQ_CTRL_2:
  490. case RT5668_IRQ_CTRL_1:
  491. case RT5668_IRQ_CTRL_2:
  492. case RT5668_IRQ_CTRL_3:
  493. case RT5668_IRQ_CTRL_4:
  494. case RT5668_INT_ST_1:
  495. case RT5668_GPIO_CTRL_1:
  496. case RT5668_GPIO_CTRL_2:
  497. case RT5668_GPIO_CTRL_3:
  498. case RT5668_HP_AMP_DET_CTRL_1:
  499. case RT5668_HP_AMP_DET_CTRL_2:
  500. case RT5668_MID_HP_AMP_DET:
  501. case RT5668_LOW_HP_AMP_DET:
  502. case RT5668_DELAY_BUF_CTRL:
  503. case RT5668_SV_ZCD_1:
  504. case RT5668_SV_ZCD_2:
  505. case RT5668_IL_CMD_1:
  506. case RT5668_IL_CMD_2:
  507. case RT5668_IL_CMD_3:
  508. case RT5668_IL_CMD_4:
  509. case RT5668_IL_CMD_5:
  510. case RT5668_IL_CMD_6:
  511. case RT5668_4BTN_IL_CMD_1:
  512. case RT5668_4BTN_IL_CMD_2:
  513. case RT5668_4BTN_IL_CMD_3:
  514. case RT5668_4BTN_IL_CMD_4:
  515. case RT5668_4BTN_IL_CMD_5:
  516. case RT5668_4BTN_IL_CMD_6:
  517. case RT5668_4BTN_IL_CMD_7:
  518. case RT5668_ADC_STO1_HP_CTRL_1:
  519. case RT5668_ADC_STO1_HP_CTRL_2:
  520. case RT5668_AJD1_CTRL:
  521. case RT5668_JD1_THD:
  522. case RT5668_JD2_THD:
  523. case RT5668_JD_CTRL_1:
  524. case RT5668_DUMMY_1:
  525. case RT5668_DUMMY_2:
  526. case RT5668_DUMMY_3:
  527. case RT5668_DAC_ADC_DIG_VOL1:
  528. case RT5668_BIAS_CUR_CTRL_2:
  529. case RT5668_BIAS_CUR_CTRL_3:
  530. case RT5668_BIAS_CUR_CTRL_4:
  531. case RT5668_BIAS_CUR_CTRL_5:
  532. case RT5668_BIAS_CUR_CTRL_6:
  533. case RT5668_BIAS_CUR_CTRL_7:
  534. case RT5668_BIAS_CUR_CTRL_8:
  535. case RT5668_BIAS_CUR_CTRL_9:
  536. case RT5668_BIAS_CUR_CTRL_10:
  537. case RT5668_VREF_REC_OP_FB_CAP_CTRL:
  538. case RT5668_CHARGE_PUMP_1:
  539. case RT5668_DIG_IN_CTRL_1:
  540. case RT5668_PAD_DRIVING_CTRL:
  541. case RT5668_SOFT_RAMP_DEPOP:
  542. case RT5668_CHOP_DAC:
  543. case RT5668_CHOP_ADC:
  544. case RT5668_CALIB_ADC_CTRL:
  545. case RT5668_VOL_TEST:
  546. case RT5668_SPKVDD_DET_STA:
  547. case RT5668_TEST_MODE_CTRL_1:
  548. case RT5668_TEST_MODE_CTRL_2:
  549. case RT5668_TEST_MODE_CTRL_3:
  550. case RT5668_TEST_MODE_CTRL_4:
  551. case RT5668_TEST_MODE_CTRL_5:
  552. case RT5668_PLL1_INTERNAL:
  553. case RT5668_PLL2_INTERNAL:
  554. case RT5668_STO_NG2_CTRL_1:
  555. case RT5668_STO_NG2_CTRL_2:
  556. case RT5668_STO_NG2_CTRL_3:
  557. case RT5668_STO_NG2_CTRL_4:
  558. case RT5668_STO_NG2_CTRL_5:
  559. case RT5668_STO_NG2_CTRL_6:
  560. case RT5668_STO_NG2_CTRL_7:
  561. case RT5668_STO_NG2_CTRL_8:
  562. case RT5668_STO_NG2_CTRL_9:
  563. case RT5668_STO_NG2_CTRL_10:
  564. case RT5668_STO1_DAC_SIL_DET:
  565. case RT5668_SIL_PSV_CTRL1:
  566. case RT5668_SIL_PSV_CTRL2:
  567. case RT5668_SIL_PSV_CTRL3:
  568. case RT5668_SIL_PSV_CTRL4:
  569. case RT5668_SIL_PSV_CTRL5:
  570. case RT5668_HP_IMP_SENS_CTRL_01:
  571. case RT5668_HP_IMP_SENS_CTRL_02:
  572. case RT5668_HP_IMP_SENS_CTRL_03:
  573. case RT5668_HP_IMP_SENS_CTRL_04:
  574. case RT5668_HP_IMP_SENS_CTRL_05:
  575. case RT5668_HP_IMP_SENS_CTRL_06:
  576. case RT5668_HP_IMP_SENS_CTRL_07:
  577. case RT5668_HP_IMP_SENS_CTRL_08:
  578. case RT5668_HP_IMP_SENS_CTRL_09:
  579. case RT5668_HP_IMP_SENS_CTRL_10:
  580. case RT5668_HP_IMP_SENS_CTRL_11:
  581. case RT5668_HP_IMP_SENS_CTRL_12:
  582. case RT5668_HP_IMP_SENS_CTRL_13:
  583. case RT5668_HP_IMP_SENS_CTRL_14:
  584. case RT5668_HP_IMP_SENS_CTRL_15:
  585. case RT5668_HP_IMP_SENS_CTRL_16:
  586. case RT5668_HP_IMP_SENS_CTRL_17:
  587. case RT5668_HP_IMP_SENS_CTRL_18:
  588. case RT5668_HP_IMP_SENS_CTRL_19:
  589. case RT5668_HP_IMP_SENS_CTRL_20:
  590. case RT5668_HP_IMP_SENS_CTRL_21:
  591. case RT5668_HP_IMP_SENS_CTRL_22:
  592. case RT5668_HP_IMP_SENS_CTRL_23:
  593. case RT5668_HP_IMP_SENS_CTRL_24:
  594. case RT5668_HP_IMP_SENS_CTRL_25:
  595. case RT5668_HP_IMP_SENS_CTRL_26:
  596. case RT5668_HP_IMP_SENS_CTRL_27:
  597. case RT5668_HP_IMP_SENS_CTRL_28:
  598. case RT5668_HP_IMP_SENS_CTRL_29:
  599. case RT5668_HP_IMP_SENS_CTRL_30:
  600. case RT5668_HP_IMP_SENS_CTRL_31:
  601. case RT5668_HP_IMP_SENS_CTRL_32:
  602. case RT5668_HP_IMP_SENS_CTRL_33:
  603. case RT5668_HP_IMP_SENS_CTRL_34:
  604. case RT5668_HP_IMP_SENS_CTRL_35:
  605. case RT5668_HP_IMP_SENS_CTRL_36:
  606. case RT5668_HP_IMP_SENS_CTRL_37:
  607. case RT5668_HP_IMP_SENS_CTRL_38:
  608. case RT5668_HP_IMP_SENS_CTRL_39:
  609. case RT5668_HP_IMP_SENS_CTRL_40:
  610. case RT5668_HP_IMP_SENS_CTRL_41:
  611. case RT5668_HP_IMP_SENS_CTRL_42:
  612. case RT5668_HP_IMP_SENS_CTRL_43:
  613. case RT5668_HP_LOGIC_CTRL_1:
  614. case RT5668_HP_LOGIC_CTRL_2:
  615. case RT5668_HP_LOGIC_CTRL_3:
  616. case RT5668_HP_CALIB_CTRL_1:
  617. case RT5668_HP_CALIB_CTRL_2:
  618. case RT5668_HP_CALIB_CTRL_3:
  619. case RT5668_HP_CALIB_CTRL_4:
  620. case RT5668_HP_CALIB_CTRL_5:
  621. case RT5668_HP_CALIB_CTRL_6:
  622. case RT5668_HP_CALIB_CTRL_7:
  623. case RT5668_HP_CALIB_CTRL_9:
  624. case RT5668_HP_CALIB_CTRL_10:
  625. case RT5668_HP_CALIB_CTRL_11:
  626. case RT5668_HP_CALIB_STA_1:
  627. case RT5668_HP_CALIB_STA_2:
  628. case RT5668_HP_CALIB_STA_3:
  629. case RT5668_HP_CALIB_STA_4:
  630. case RT5668_HP_CALIB_STA_5:
  631. case RT5668_HP_CALIB_STA_6:
  632. case RT5668_HP_CALIB_STA_7:
  633. case RT5668_HP_CALIB_STA_8:
  634. case RT5668_HP_CALIB_STA_9:
  635. case RT5668_HP_CALIB_STA_10:
  636. case RT5668_HP_CALIB_STA_11:
  637. case RT5668_SAR_IL_CMD_1:
  638. case RT5668_SAR_IL_CMD_2:
  639. case RT5668_SAR_IL_CMD_3:
  640. case RT5668_SAR_IL_CMD_4:
  641. case RT5668_SAR_IL_CMD_5:
  642. case RT5668_SAR_IL_CMD_6:
  643. case RT5668_SAR_IL_CMD_7:
  644. case RT5668_SAR_IL_CMD_8:
  645. case RT5668_SAR_IL_CMD_9:
  646. case RT5668_SAR_IL_CMD_10:
  647. case RT5668_SAR_IL_CMD_11:
  648. case RT5668_SAR_IL_CMD_12:
  649. case RT5668_SAR_IL_CMD_13:
  650. case RT5668_EFUSE_CTRL_1:
  651. case RT5668_EFUSE_CTRL_2:
  652. case RT5668_EFUSE_CTRL_3:
  653. case RT5668_EFUSE_CTRL_4:
  654. case RT5668_EFUSE_CTRL_5:
  655. case RT5668_EFUSE_CTRL_6:
  656. case RT5668_EFUSE_CTRL_7:
  657. case RT5668_EFUSE_CTRL_8:
  658. case RT5668_EFUSE_CTRL_9:
  659. case RT5668_EFUSE_CTRL_10:
  660. case RT5668_EFUSE_CTRL_11:
  661. case RT5668_JD_TOP_VC_VTRL:
  662. case RT5668_DRC1_CTRL_0:
  663. case RT5668_DRC1_CTRL_1:
  664. case RT5668_DRC1_CTRL_2:
  665. case RT5668_DRC1_CTRL_3:
  666. case RT5668_DRC1_CTRL_4:
  667. case RT5668_DRC1_CTRL_5:
  668. case RT5668_DRC1_CTRL_6:
  669. case RT5668_DRC1_HARD_LMT_CTRL_1:
  670. case RT5668_DRC1_HARD_LMT_CTRL_2:
  671. case RT5668_DRC1_PRIV_1:
  672. case RT5668_DRC1_PRIV_2:
  673. case RT5668_DRC1_PRIV_3:
  674. case RT5668_DRC1_PRIV_4:
  675. case RT5668_DRC1_PRIV_5:
  676. case RT5668_DRC1_PRIV_6:
  677. case RT5668_DRC1_PRIV_7:
  678. case RT5668_DRC1_PRIV_8:
  679. case RT5668_EQ_AUTO_RCV_CTRL1:
  680. case RT5668_EQ_AUTO_RCV_CTRL2:
  681. case RT5668_EQ_AUTO_RCV_CTRL3:
  682. case RT5668_EQ_AUTO_RCV_CTRL4:
  683. case RT5668_EQ_AUTO_RCV_CTRL5:
  684. case RT5668_EQ_AUTO_RCV_CTRL6:
  685. case RT5668_EQ_AUTO_RCV_CTRL7:
  686. case RT5668_EQ_AUTO_RCV_CTRL8:
  687. case RT5668_EQ_AUTO_RCV_CTRL9:
  688. case RT5668_EQ_AUTO_RCV_CTRL10:
  689. case RT5668_EQ_AUTO_RCV_CTRL11:
  690. case RT5668_EQ_AUTO_RCV_CTRL12:
  691. case RT5668_EQ_AUTO_RCV_CTRL13:
  692. case RT5668_ADC_L_EQ_LPF1_A1:
  693. case RT5668_R_EQ_LPF1_A1:
  694. case RT5668_L_EQ_LPF1_H0:
  695. case RT5668_R_EQ_LPF1_H0:
  696. case RT5668_L_EQ_BPF1_A1:
  697. case RT5668_R_EQ_BPF1_A1:
  698. case RT5668_L_EQ_BPF1_A2:
  699. case RT5668_R_EQ_BPF1_A2:
  700. case RT5668_L_EQ_BPF1_H0:
  701. case RT5668_R_EQ_BPF1_H0:
  702. case RT5668_L_EQ_BPF2_A1:
  703. case RT5668_R_EQ_BPF2_A1:
  704. case RT5668_L_EQ_BPF2_A2:
  705. case RT5668_R_EQ_BPF2_A2:
  706. case RT5668_L_EQ_BPF2_H0:
  707. case RT5668_R_EQ_BPF2_H0:
  708. case RT5668_L_EQ_BPF3_A1:
  709. case RT5668_R_EQ_BPF3_A1:
  710. case RT5668_L_EQ_BPF3_A2:
  711. case RT5668_R_EQ_BPF3_A2:
  712. case RT5668_L_EQ_BPF3_H0:
  713. case RT5668_R_EQ_BPF3_H0:
  714. case RT5668_L_EQ_BPF4_A1:
  715. case RT5668_R_EQ_BPF4_A1:
  716. case RT5668_L_EQ_BPF4_A2:
  717. case RT5668_R_EQ_BPF4_A2:
  718. case RT5668_L_EQ_BPF4_H0:
  719. case RT5668_R_EQ_BPF4_H0:
  720. case RT5668_L_EQ_HPF1_A1:
  721. case RT5668_R_EQ_HPF1_A1:
  722. case RT5668_L_EQ_HPF1_H0:
  723. case RT5668_R_EQ_HPF1_H0:
  724. case RT5668_L_EQ_PRE_VOL:
  725. case RT5668_R_EQ_PRE_VOL:
  726. case RT5668_L_EQ_POST_VOL:
  727. case RT5668_R_EQ_POST_VOL:
  728. case RT5668_I2C_MODE:
  729. return true;
  730. default:
  731. return false;
  732. }
  733. }
  734. static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
  735. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
  736. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
  737. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  738. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  739. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  740. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  741. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  742. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  743. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  744. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  745. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  746. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  747. );
  748. /* Interface data select */
  749. static const char * const rt5668_data_select[] = {
  750. "L/R", "R/L", "L/L", "R/R"
  751. };
  752. static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum,
  753. RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select);
  754. static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum,
  755. RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select);
  756. static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum,
  757. RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select);
  758. static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum,
  759. RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select);
  760. static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum,
  761. RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select);
  762. static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux =
  763. SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum);
  764. static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux =
  765. SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum);
  766. static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux =
  767. SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum);
  768. static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux =
  769. SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum);
  770. static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux =
  771. SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum);
  772. static void rt5668_reset(struct regmap *regmap)
  773. {
  774. regmap_write(regmap, RT5668_RESET, 0);
  775. regmap_write(regmap, RT5668_I2C_MODE, 1);
  776. }
  777. /**
  778. * rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters
  779. * @component: SoC audio component device.
  780. * @filter_mask: mask of filters.
  781. * @clk_src: clock source
  782. *
  783. * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
  784. * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
  785. * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
  786. * ASRC function will track i2s clock and generate a corresponding system clock
  787. * for codec. This function provides an API to select the clock source for a
  788. * set of filters specified by the mask. And the component driver will turn on
  789. * ASRC for these filters if ASRC is selected as their clock source.
  790. */
  791. int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
  792. unsigned int filter_mask, unsigned int clk_src)
  793. {
  794. switch (clk_src) {
  795. case RT5668_CLK_SEL_SYS:
  796. case RT5668_CLK_SEL_I2S1_ASRC:
  797. case RT5668_CLK_SEL_I2S2_ASRC:
  798. break;
  799. default:
  800. return -EINVAL;
  801. }
  802. if (filter_mask & RT5668_DA_STEREO1_FILTER) {
  803. snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2,
  804. RT5668_FILTER_CLK_SEL_MASK,
  805. clk_src << RT5668_FILTER_CLK_SEL_SFT);
  806. }
  807. if (filter_mask & RT5668_AD_STEREO1_FILTER) {
  808. snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3,
  809. RT5668_FILTER_CLK_SEL_MASK,
  810. clk_src << RT5668_FILTER_CLK_SEL_SFT);
  811. }
  812. return 0;
  813. }
  814. EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src);
  815. static int rt5668_button_detect(struct snd_soc_component *component)
  816. {
  817. int btn_type, val;
  818. val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1);
  819. btn_type = val & 0xfff0;
  820. snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val);
  821. pr_debug("%s btn_type=%x\n", __func__, btn_type);
  822. return btn_type;
  823. }
  824. static void rt5668_enable_push_button_irq(struct snd_soc_component *component,
  825. bool enable)
  826. {
  827. if (enable) {
  828. snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
  829. RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN);
  830. snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
  831. RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN);
  832. snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040);
  833. snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
  834. RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK,
  835. RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR);
  836. snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
  837. RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN);
  838. } else {
  839. snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
  840. RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS);
  841. snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
  842. RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS);
  843. snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
  844. RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS);
  845. snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
  846. RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST);
  847. snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
  848. RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE);
  849. }
  850. }
  851. /**
  852. * rt5668_headset_detect - Detect headset.
  853. * @component: SoC audio component device.
  854. * @jack_insert: Jack insert or not.
  855. *
  856. * Detect whether is headset or not when jack inserted.
  857. *
  858. * Returns detect status.
  859. */
  860. static int rt5668_headset_detect(struct snd_soc_component *component,
  861. int jack_insert)
  862. {
  863. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  864. struct snd_soc_dapm_context *dapm =
  865. snd_soc_component_get_dapm(component);
  866. unsigned int val, count;
  867. if (jack_insert) {
  868. snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
  869. snd_soc_dapm_sync(dapm);
  870. snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
  871. RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH);
  872. count = 0;
  873. val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2)
  874. & RT5668_JACK_TYPE_MASK;
  875. while (val == 0 && count < 50) {
  876. usleep_range(10000, 15000);
  877. val = snd_soc_component_read(component,
  878. RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK;
  879. count++;
  880. }
  881. switch (val) {
  882. case 0x1:
  883. case 0x2:
  884. rt5668->jack_type = SND_JACK_HEADSET;
  885. rt5668_enable_push_button_irq(component, true);
  886. break;
  887. default:
  888. rt5668->jack_type = SND_JACK_HEADPHONE;
  889. }
  890. } else {
  891. rt5668_enable_push_button_irq(component, false);
  892. snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
  893. RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW);
  894. snd_soc_dapm_disable_pin(dapm, "CBJ Power");
  895. snd_soc_dapm_sync(dapm);
  896. rt5668->jack_type = 0;
  897. }
  898. dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type);
  899. return rt5668->jack_type;
  900. }
  901. static irqreturn_t rt5668_irq(int irq, void *data)
  902. {
  903. struct rt5668_priv *rt5668 = data;
  904. mod_delayed_work(system_power_efficient_wq,
  905. &rt5668->jack_detect_work, msecs_to_jiffies(250));
  906. return IRQ_HANDLED;
  907. }
  908. static void rt5668_jd_check_handler(struct work_struct *work)
  909. {
  910. struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv,
  911. jd_check_work.work);
  912. if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
  913. & RT5668_JDH_RS_MASK) {
  914. /* jack out */
  915. rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
  916. snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
  917. SND_JACK_HEADSET |
  918. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  919. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  920. } else {
  921. schedule_delayed_work(&rt5668->jd_check_work, 500);
  922. }
  923. }
  924. static int rt5668_set_jack_detect(struct snd_soc_component *component,
  925. struct snd_soc_jack *hs_jack, void *data)
  926. {
  927. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  928. switch (rt5668->pdata.jd_src) {
  929. case RT5668_JD1:
  930. snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2,
  931. RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL);
  932. snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002);
  933. snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3,
  934. RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN);
  935. snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
  936. RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN);
  937. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  938. RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ);
  939. regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
  940. RT5668_POW_IRQ | RT5668_POW_JDH |
  941. RT5668_POW_ANA, RT5668_POW_IRQ |
  942. RT5668_POW_JDH | RT5668_POW_ANA);
  943. regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2,
  944. RT5668_PWR_JDH | RT5668_PWR_JDL,
  945. RT5668_PWR_JDH | RT5668_PWR_JDL);
  946. regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
  947. RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK,
  948. RT5668_JD1_EN | RT5668_JD1_POL_NOR);
  949. mod_delayed_work(system_power_efficient_wq,
  950. &rt5668->jack_detect_work, msecs_to_jiffies(250));
  951. break;
  952. case RT5668_JD_NULL:
  953. regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
  954. RT5668_JD1_EN_MASK, RT5668_JD1_DIS);
  955. regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
  956. RT5668_POW_JDH | RT5668_POW_JDL, 0);
  957. break;
  958. default:
  959. dev_warn(component->dev, "Wrong JD source\n");
  960. break;
  961. }
  962. rt5668->hs_jack = hs_jack;
  963. return 0;
  964. }
  965. static void rt5668_jack_detect_handler(struct work_struct *work)
  966. {
  967. struct rt5668_priv *rt5668 =
  968. container_of(work, struct rt5668_priv, jack_detect_work.work);
  969. int val, btn_type;
  970. if (!rt5668->component || !rt5668->component->card ||
  971. !rt5668->component->card->instantiated) {
  972. /* card not yet ready, try later */
  973. mod_delayed_work(system_power_efficient_wq,
  974. &rt5668->jack_detect_work, msecs_to_jiffies(15));
  975. return;
  976. }
  977. mutex_lock(&rt5668->calibrate_mutex);
  978. val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
  979. & RT5668_JDH_RS_MASK;
  980. if (!val) {
  981. /* jack in */
  982. if (rt5668->jack_type == 0) {
  983. /* jack was out, report jack type */
  984. rt5668->jack_type =
  985. rt5668_headset_detect(rt5668->component, 1);
  986. } else {
  987. /* jack is already in, report button event */
  988. rt5668->jack_type = SND_JACK_HEADSET;
  989. btn_type = rt5668_button_detect(rt5668->component);
  990. /**
  991. * rt5668 can report three kinds of button behavior,
  992. * one click, double click and hold. However,
  993. * currently we will report button pressed/released
  994. * event. So all the three button behaviors are
  995. * treated as button pressed.
  996. */
  997. switch (btn_type) {
  998. case 0x8000:
  999. case 0x4000:
  1000. case 0x2000:
  1001. rt5668->jack_type |= SND_JACK_BTN_0;
  1002. break;
  1003. case 0x1000:
  1004. case 0x0800:
  1005. case 0x0400:
  1006. rt5668->jack_type |= SND_JACK_BTN_1;
  1007. break;
  1008. case 0x0200:
  1009. case 0x0100:
  1010. case 0x0080:
  1011. rt5668->jack_type |= SND_JACK_BTN_2;
  1012. break;
  1013. case 0x0040:
  1014. case 0x0020:
  1015. case 0x0010:
  1016. rt5668->jack_type |= SND_JACK_BTN_3;
  1017. break;
  1018. case 0x0000: /* unpressed */
  1019. break;
  1020. default:
  1021. btn_type = 0;
  1022. dev_err(rt5668->component->dev,
  1023. "Unexpected button code 0x%04x\n",
  1024. btn_type);
  1025. break;
  1026. }
  1027. }
  1028. } else {
  1029. /* jack out */
  1030. rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
  1031. }
  1032. snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
  1033. SND_JACK_HEADSET |
  1034. SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1035. SND_JACK_BTN_2 | SND_JACK_BTN_3);
  1036. if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  1037. SND_JACK_BTN_2 | SND_JACK_BTN_3))
  1038. schedule_delayed_work(&rt5668->jd_check_work, 0);
  1039. else
  1040. cancel_delayed_work_sync(&rt5668->jd_check_work);
  1041. mutex_unlock(&rt5668->calibrate_mutex);
  1042. }
  1043. static const struct snd_kcontrol_new rt5668_snd_controls[] = {
  1044. /* Headphone Output Volume */
  1045. SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN,
  1046. RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv),
  1047. /* DAC Digital Volume */
  1048. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL,
  1049. RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv),
  1050. /* IN Boost Volume */
  1051. SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL,
  1052. RT5668_BST_CBJ_SFT, 8, 0, bst_tlv),
  1053. /* ADC Digital Volume Control */
  1054. SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL,
  1055. RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1),
  1056. SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL,
  1057. RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv),
  1058. /* ADC Boost Volume Control */
  1059. SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST,
  1060. RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT,
  1061. 3, 0, adc_bst_tlv),
  1062. };
  1063. static int rt5668_div_sel(struct rt5668_priv *rt5668,
  1064. int target, const int div[], int size)
  1065. {
  1066. int i;
  1067. if (rt5668->sysclk < target) {
  1068. pr_err("sysclk rate %d is too low\n",
  1069. rt5668->sysclk);
  1070. return 0;
  1071. }
  1072. for (i = 0; i < size - 1; i++) {
  1073. pr_info("div[%d]=%d\n", i, div[i]);
  1074. if (target * div[i] == rt5668->sysclk)
  1075. return i;
  1076. if (target * div[i + 1] > rt5668->sysclk) {
  1077. pr_err("can't find div for sysclk %d\n",
  1078. rt5668->sysclk);
  1079. return i;
  1080. }
  1081. }
  1082. if (target * div[i] < rt5668->sysclk)
  1083. pr_err("sysclk rate %d is too high\n",
  1084. rt5668->sysclk);
  1085. return size - 1;
  1086. }
  1087. /**
  1088. * set_dmic_clk - Set parameter of dmic.
  1089. *
  1090. * @w: DAPM widget.
  1091. * @kcontrol: The kcontrol of this widget.
  1092. * @event: Event id.
  1093. *
  1094. * Choose dmic clock between 1MHz and 3MHz.
  1095. * It is better for clock to approximate 3MHz.
  1096. */
  1097. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  1098. struct snd_kcontrol *kcontrol, int event)
  1099. {
  1100. struct snd_soc_component *component =
  1101. snd_soc_dapm_to_component(w->dapm);
  1102. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1103. int idx;
  1104. static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
  1105. idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div));
  1106. snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1,
  1107. RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT);
  1108. return 0;
  1109. }
  1110. static int set_filter_clk(struct snd_soc_dapm_widget *w,
  1111. struct snd_kcontrol *kcontrol, int event)
  1112. {
  1113. struct snd_soc_component *component =
  1114. snd_soc_dapm_to_component(w->dapm);
  1115. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1116. int ref, val, reg, idx;
  1117. static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
  1118. val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) &
  1119. RT5668_GP4_PIN_MASK;
  1120. if (w->shift == RT5668_PWR_ADC_S1F_BIT &&
  1121. val == RT5668_GP4_PIN_ADCDAT2)
  1122. ref = 256 * rt5668->lrck[RT5668_AIF2];
  1123. else
  1124. ref = 256 * rt5668->lrck[RT5668_AIF1];
  1125. idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div));
  1126. if (w->shift == RT5668_PWR_ADC_S1F_BIT)
  1127. reg = RT5668_PLL_TRACK_3;
  1128. else
  1129. reg = RT5668_PLL_TRACK_2;
  1130. snd_soc_component_update_bits(component, reg,
  1131. RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT);
  1132. return 0;
  1133. }
  1134. static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
  1135. struct snd_soc_dapm_widget *sink)
  1136. {
  1137. unsigned int val;
  1138. struct snd_soc_component *component =
  1139. snd_soc_dapm_to_component(w->dapm);
  1140. val = snd_soc_component_read(component, RT5668_GLB_CLK);
  1141. val &= RT5668_SCLK_SRC_MASK;
  1142. if (val == RT5668_SCLK_SRC_PLL1)
  1143. return 1;
  1144. else
  1145. return 0;
  1146. }
  1147. static int is_using_asrc(struct snd_soc_dapm_widget *w,
  1148. struct snd_soc_dapm_widget *sink)
  1149. {
  1150. unsigned int reg, shift, val;
  1151. struct snd_soc_component *component =
  1152. snd_soc_dapm_to_component(w->dapm);
  1153. switch (w->shift) {
  1154. case RT5668_ADC_STO1_ASRC_SFT:
  1155. reg = RT5668_PLL_TRACK_3;
  1156. shift = RT5668_FILTER_CLK_SEL_SFT;
  1157. break;
  1158. case RT5668_DAC_STO1_ASRC_SFT:
  1159. reg = RT5668_PLL_TRACK_2;
  1160. shift = RT5668_FILTER_CLK_SEL_SFT;
  1161. break;
  1162. default:
  1163. return 0;
  1164. }
  1165. val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
  1166. switch (val) {
  1167. case RT5668_CLK_SEL_I2S1_ASRC:
  1168. case RT5668_CLK_SEL_I2S2_ASRC:
  1169. return 1;
  1170. default:
  1171. return 0;
  1172. }
  1173. }
  1174. /* Digital Mixer */
  1175. static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = {
  1176. SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
  1177. RT5668_M_STO1_ADC_L1_SFT, 1, 1),
  1178. SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
  1179. RT5668_M_STO1_ADC_L2_SFT, 1, 1),
  1180. };
  1181. static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
  1182. SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
  1183. RT5668_M_STO1_ADC_R1_SFT, 1, 1),
  1184. SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
  1185. RT5668_M_STO1_ADC_R2_SFT, 1, 1),
  1186. };
  1187. static const struct snd_kcontrol_new rt5668_dac_l_mix[] = {
  1188. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
  1189. RT5668_M_ADCMIX_L_SFT, 1, 1),
  1190. SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
  1191. RT5668_M_DAC1_L_SFT, 1, 1),
  1192. };
  1193. static const struct snd_kcontrol_new rt5668_dac_r_mix[] = {
  1194. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
  1195. RT5668_M_ADCMIX_R_SFT, 1, 1),
  1196. SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
  1197. RT5668_M_DAC1_R_SFT, 1, 1),
  1198. };
  1199. static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = {
  1200. SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
  1201. RT5668_M_DAC_L1_STO_L_SFT, 1, 1),
  1202. SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
  1203. RT5668_M_DAC_R1_STO_L_SFT, 1, 1),
  1204. };
  1205. static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = {
  1206. SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
  1207. RT5668_M_DAC_L1_STO_R_SFT, 1, 1),
  1208. SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
  1209. RT5668_M_DAC_R1_STO_R_SFT, 1, 1),
  1210. };
  1211. /* Analog Input Mixer */
  1212. static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = {
  1213. SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER,
  1214. RT5668_M_CBJ_RM1_L_SFT, 1, 1),
  1215. };
  1216. /* STO1 ADC1 Source */
  1217. /* MX-26 [13] [5] */
  1218. static const char * const rt5668_sto1_adc1_src[] = {
  1219. "DAC MIX", "ADC"
  1220. };
  1221. static SOC_ENUM_SINGLE_DECL(
  1222. rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER,
  1223. RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src);
  1224. static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux =
  1225. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum);
  1226. static SOC_ENUM_SINGLE_DECL(
  1227. rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER,
  1228. RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src);
  1229. static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux =
  1230. SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum);
  1231. /* STO1 ADC Source */
  1232. /* MX-26 [11:10] [3:2] */
  1233. static const char * const rt5668_sto1_adc_src[] = {
  1234. "ADC1 L", "ADC1 R"
  1235. };
  1236. static SOC_ENUM_SINGLE_DECL(
  1237. rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER,
  1238. RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src);
  1239. static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
  1240. SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum);
  1241. static SOC_ENUM_SINGLE_DECL(
  1242. rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER,
  1243. RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src);
  1244. static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
  1245. SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum);
  1246. /* STO1 ADC2 Source */
  1247. /* MX-26 [12] [4] */
  1248. static const char * const rt5668_sto1_adc2_src[] = {
  1249. "DAC MIX", "DMIC"
  1250. };
  1251. static SOC_ENUM_SINGLE_DECL(
  1252. rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER,
  1253. RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src);
  1254. static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux =
  1255. SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum);
  1256. static SOC_ENUM_SINGLE_DECL(
  1257. rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER,
  1258. RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src);
  1259. static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux =
  1260. SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum);
  1261. /* MX-79 [6:4] I2S1 ADC data location */
  1262. static const unsigned int rt5668_if1_adc_slot_values[] = {
  1263. 0,
  1264. 2,
  1265. 4,
  1266. 6,
  1267. };
  1268. static const char * const rt5668_if1_adc_slot_src[] = {
  1269. "Slot 0", "Slot 2", "Slot 4", "Slot 6"
  1270. };
  1271. static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum,
  1272. RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK,
  1273. rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values);
  1274. static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux =
  1275. SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum);
  1276. /* Analog DAC L1 Source, Analog DAC R1 Source*/
  1277. /* MX-2B [4], MX-2B [0]*/
  1278. static const char * const rt5668_alg_dac1_src[] = {
  1279. "Stereo1 DAC Mixer", "DAC1"
  1280. };
  1281. static SOC_ENUM_SINGLE_DECL(
  1282. rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX,
  1283. RT5668_A_DACL1_SFT, rt5668_alg_dac1_src);
  1284. static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux =
  1285. SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum);
  1286. static SOC_ENUM_SINGLE_DECL(
  1287. rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX,
  1288. RT5668_A_DACR1_SFT, rt5668_alg_dac1_src);
  1289. static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux =
  1290. SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum);
  1291. /* Out Switch */
  1292. static const struct snd_kcontrol_new hpol_switch =
  1293. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
  1294. RT5668_L_MUTE_SFT, 1, 1);
  1295. static const struct snd_kcontrol_new hpor_switch =
  1296. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
  1297. RT5668_R_MUTE_SFT, 1, 1);
  1298. static int rt5668_hp_event(struct snd_soc_dapm_widget *w,
  1299. struct snd_kcontrol *kcontrol, int event)
  1300. {
  1301. struct snd_soc_component *component =
  1302. snd_soc_dapm_to_component(w->dapm);
  1303. switch (event) {
  1304. case SND_SOC_DAPM_PRE_PMU:
  1305. snd_soc_component_write(component,
  1306. RT5668_HP_LOGIC_CTRL_2, 0x0012);
  1307. snd_soc_component_write(component,
  1308. RT5668_HP_CTRL_2, 0x6000);
  1309. snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1,
  1310. RT5668_NG2_EN_MASK, RT5668_NG2_EN);
  1311. snd_soc_component_update_bits(component,
  1312. RT5668_DEPOP_1, 0x60, 0x60);
  1313. break;
  1314. case SND_SOC_DAPM_POST_PMD:
  1315. snd_soc_component_update_bits(component,
  1316. RT5668_DEPOP_1, 0x60, 0x0);
  1317. snd_soc_component_write(component,
  1318. RT5668_HP_CTRL_2, 0x0000);
  1319. break;
  1320. default:
  1321. return 0;
  1322. }
  1323. return 0;
  1324. }
  1325. static int set_dmic_power(struct snd_soc_dapm_widget *w,
  1326. struct snd_kcontrol *kcontrol, int event)
  1327. {
  1328. switch (event) {
  1329. case SND_SOC_DAPM_POST_PMU:
  1330. /*Add delay to avoid pop noise*/
  1331. msleep(150);
  1332. break;
  1333. default:
  1334. return 0;
  1335. }
  1336. return 0;
  1337. }
  1338. static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
  1339. struct snd_kcontrol *kcontrol, int event)
  1340. {
  1341. struct snd_soc_component *component =
  1342. snd_soc_dapm_to_component(w->dapm);
  1343. switch (event) {
  1344. case SND_SOC_DAPM_PRE_PMU:
  1345. switch (w->shift) {
  1346. case RT5668_PWR_VREF1_BIT:
  1347. snd_soc_component_update_bits(component,
  1348. RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0);
  1349. break;
  1350. case RT5668_PWR_VREF2_BIT:
  1351. snd_soc_component_update_bits(component,
  1352. RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0);
  1353. break;
  1354. default:
  1355. break;
  1356. }
  1357. break;
  1358. case SND_SOC_DAPM_POST_PMU:
  1359. usleep_range(15000, 20000);
  1360. switch (w->shift) {
  1361. case RT5668_PWR_VREF1_BIT:
  1362. snd_soc_component_update_bits(component,
  1363. RT5668_PWR_ANLG_1, RT5668_PWR_FV1,
  1364. RT5668_PWR_FV1);
  1365. break;
  1366. case RT5668_PWR_VREF2_BIT:
  1367. snd_soc_component_update_bits(component,
  1368. RT5668_PWR_ANLG_1, RT5668_PWR_FV2,
  1369. RT5668_PWR_FV2);
  1370. break;
  1371. default:
  1372. break;
  1373. }
  1374. break;
  1375. default:
  1376. return 0;
  1377. }
  1378. return 0;
  1379. }
  1380. static const unsigned int rt5668_adcdat_pin_values[] = {
  1381. 1,
  1382. 3,
  1383. };
  1384. static const char * const rt5668_adcdat_pin_select[] = {
  1385. "ADCDAT1",
  1386. "ADCDAT2",
  1387. };
  1388. static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum,
  1389. RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK,
  1390. rt5668_adcdat_pin_select, rt5668_adcdat_pin_values);
  1391. static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl =
  1392. SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum);
  1393. static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = {
  1394. SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT,
  1395. 0, NULL, 0),
  1396. SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT,
  1397. 0, NULL, 0),
  1398. SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT,
  1399. 0, NULL, 0),
  1400. SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT,
  1401. 0, NULL, 0),
  1402. SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0,
  1403. rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1404. SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0,
  1405. rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1406. /* ASRC */
  1407. SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
  1408. RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0),
  1409. SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
  1410. RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0),
  1411. SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1,
  1412. RT5668_AD_ASRC_SFT, 0, NULL, 0),
  1413. SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1,
  1414. RT5668_DA_ASRC_SFT, 0, NULL, 0),
  1415. SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1,
  1416. RT5668_DMIC_ASRC_SFT, 0, NULL, 0),
  1417. /* Input Side */
  1418. SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT,
  1419. 0, NULL, 0),
  1420. SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT,
  1421. 0, NULL, 0),
  1422. /* Input Lines */
  1423. SND_SOC_DAPM_INPUT("DMIC L1"),
  1424. SND_SOC_DAPM_INPUT("DMIC R1"),
  1425. SND_SOC_DAPM_INPUT("IN1P"),
  1426. SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  1427. set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  1428. SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1,
  1429. RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
  1430. /* Boost */
  1431. SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
  1432. 0, 0, NULL, 0),
  1433. SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3,
  1434. RT5668_PWR_CBJ_BIT, 0, NULL, 0),
  1435. /* REC Mixer */
  1436. SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix,
  1437. ARRAY_SIZE(rt5668_rec1_l_mix)),
  1438. SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2,
  1439. RT5668_PWR_RM1_L_BIT, 0, NULL, 0),
  1440. /* ADCs */
  1441. SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
  1442. SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
  1443. SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1,
  1444. RT5668_PWR_ADC_L1_BIT, 0, NULL, 0),
  1445. SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1,
  1446. RT5668_PWR_ADC_R1_BIT, 0, NULL, 0),
  1447. SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC,
  1448. RT5668_CKGEN_ADC1_SFT, 0, NULL, 0),
  1449. /* ADC Mux */
  1450. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  1451. &rt5668_sto1_adc1l_mux),
  1452. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  1453. &rt5668_sto1_adc1r_mux),
  1454. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  1455. &rt5668_sto1_adc2l_mux),
  1456. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  1457. &rt5668_sto1_adc2r_mux),
  1458. SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
  1459. &rt5668_sto1_adcl_mux),
  1460. SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
  1461. &rt5668_sto1_adcr_mux),
  1462. SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
  1463. &rt5668_if1_adc_slot_mux),
  1464. /* ADC Mixer */
  1465. SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2,
  1466. RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk,
  1467. SND_SOC_DAPM_PRE_PMU),
  1468. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL,
  1469. RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix,
  1470. ARRAY_SIZE(rt5668_sto1_adc_l_mix)),
  1471. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL,
  1472. RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix,
  1473. ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
  1474. /* ADC PGA */
  1475. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  1476. /* Digital Interface */
  1477. SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT,
  1478. 0, NULL, 0),
  1479. SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT,
  1480. 0, NULL, 0),
  1481. SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  1482. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  1483. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  1484. /* Digital Interface Select */
  1485. SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1486. &rt5668_if1_01_adc_swap_mux),
  1487. SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1488. &rt5668_if1_23_adc_swap_mux),
  1489. SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1490. &rt5668_if1_45_adc_swap_mux),
  1491. SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1492. &rt5668_if1_67_adc_swap_mux),
  1493. SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
  1494. &rt5668_if2_adc_swap_mux),
  1495. SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
  1496. &rt5668_adcdat_pin_ctrl),
  1497. /* Audio Interface */
  1498. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
  1499. RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1),
  1500. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
  1501. RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1),
  1502. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  1503. /* Output Side */
  1504. /* DAC mixer before sound effect */
  1505. SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
  1506. rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)),
  1507. SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  1508. rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)),
  1509. /* DAC channel Mux */
  1510. SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
  1511. &rt5668_alg_dac_l1_mux),
  1512. SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
  1513. &rt5668_alg_dac_r1_mux),
  1514. /* DAC Mixer */
  1515. SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2,
  1516. RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk,
  1517. SND_SOC_DAPM_PRE_PMU),
  1518. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
  1519. rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)),
  1520. SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
  1521. rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)),
  1522. /* DACs */
  1523. SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1,
  1524. RT5668_PWR_DAC_L1_BIT, 0),
  1525. SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1,
  1526. RT5668_PWR_DAC_R1_BIT, 0),
  1527. SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC,
  1528. RT5668_CKGEN_DAC1_SFT, 0, NULL, 0),
  1529. /* HPO */
  1530. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event,
  1531. SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
  1532. SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1,
  1533. RT5668_PWR_HA_L_BIT, 0, NULL, 0),
  1534. SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1,
  1535. RT5668_PWR_HA_R_BIT, 0, NULL, 0),
  1536. SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1,
  1537. RT5668_PUMP_EN_SFT, 0, NULL, 0),
  1538. SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1,
  1539. RT5668_CAPLESS_EN_SFT, 0, NULL, 0),
  1540. SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
  1541. &hpol_switch),
  1542. SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
  1543. &hpor_switch),
  1544. /* CLK DET */
  1545. SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET,
  1546. RT5668_SYS_CLK_DET_SFT, 0, NULL, 0),
  1547. SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET,
  1548. RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0),
  1549. SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET,
  1550. RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0),
  1551. SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET,
  1552. RT5668_POW_CLK_DET_SFT, 0, NULL, 0),
  1553. /* Output Lines */
  1554. SND_SOC_DAPM_OUTPUT("HPOL"),
  1555. SND_SOC_DAPM_OUTPUT("HPOR"),
  1556. };
  1557. static const struct snd_soc_dapm_route rt5668_dapm_routes[] = {
  1558. /*PLL*/
  1559. {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1560. {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
  1561. /*ASRC*/
  1562. {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
  1563. {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
  1564. {"ADC STO1 ASRC", NULL, "AD ASRC"},
  1565. {"DAC STO1 ASRC", NULL, "DA ASRC"},
  1566. /*Vref*/
  1567. {"MICBIAS1", NULL, "Vref1"},
  1568. {"MICBIAS1", NULL, "Vref2"},
  1569. {"MICBIAS2", NULL, "Vref1"},
  1570. {"MICBIAS2", NULL, "Vref2"},
  1571. {"CLKDET SYS", NULL, "CLKDET"},
  1572. {"IN1P", NULL, "LDO2"},
  1573. {"BST1 CBJ", NULL, "IN1P"},
  1574. {"BST1 CBJ", NULL, "CBJ Power"},
  1575. {"CBJ Power", NULL, "Vref2"},
  1576. {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
  1577. {"RECMIX1L", NULL, "RECMIX1L Power"},
  1578. {"ADC1 L", NULL, "RECMIX1L"},
  1579. {"ADC1 L", NULL, "ADC1 L Power"},
  1580. {"ADC1 L", NULL, "ADC1 clock"},
  1581. {"DMIC L1", NULL, "DMIC CLK"},
  1582. {"DMIC L1", NULL, "DMIC1 Power"},
  1583. {"DMIC R1", NULL, "DMIC CLK"},
  1584. {"DMIC R1", NULL, "DMIC1 Power"},
  1585. {"DMIC CLK", NULL, "DMIC ASRC"},
  1586. {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
  1587. {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
  1588. {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
  1589. {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
  1590. {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
  1591. {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1592. {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
  1593. {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
  1594. {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
  1595. {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1596. {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
  1597. {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
  1598. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  1599. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  1600. {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
  1601. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  1602. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  1603. {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
  1604. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
  1605. {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
  1606. {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1607. {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1608. {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1609. {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1610. {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1611. {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1612. {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1613. {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1614. {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1615. {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1616. {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1617. {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1618. {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1619. {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1620. {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1621. {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1622. {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
  1623. {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
  1624. {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
  1625. {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
  1626. {"IF1_ADC Mux", NULL, "I2S1"},
  1627. {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
  1628. {"AIF1TX", NULL, "ADCDAT Mux"},
  1629. {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
  1630. {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
  1631. {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
  1632. {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
  1633. {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
  1634. {"AIF2TX", NULL, "ADCDAT Mux"},
  1635. {"IF1 DAC1 L", NULL, "AIF1RX"},
  1636. {"IF1 DAC1 L", NULL, "I2S1"},
  1637. {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
  1638. {"IF1 DAC1 R", NULL, "AIF1RX"},
  1639. {"IF1 DAC1 R", NULL, "I2S1"},
  1640. {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
  1641. {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  1642. {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
  1643. {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  1644. {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
  1645. {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
  1646. {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
  1647. {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
  1648. {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
  1649. {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
  1650. {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
  1651. {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
  1652. {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
  1653. {"DAC L1", NULL, "DAC L1 Source"},
  1654. {"DAC R1", NULL, "DAC R1 Source"},
  1655. {"DAC L1", NULL, "DAC 1 Clock"},
  1656. {"DAC R1", NULL, "DAC 1 Clock"},
  1657. {"HP Amp", NULL, "DAC L1"},
  1658. {"HP Amp", NULL, "DAC R1"},
  1659. {"HP Amp", NULL, "HP Amp L"},
  1660. {"HP Amp", NULL, "HP Amp R"},
  1661. {"HP Amp", NULL, "Capless"},
  1662. {"HP Amp", NULL, "Charge Pump"},
  1663. {"HP Amp", NULL, "CLKDET SYS"},
  1664. {"HP Amp", NULL, "CBJ Power"},
  1665. {"HP Amp", NULL, "Vref2"},
  1666. {"HPOL Playback", "Switch", "HP Amp"},
  1667. {"HPOR Playback", "Switch", "HP Amp"},
  1668. {"HPOL", NULL, "HPOL Playback"},
  1669. {"HPOR", NULL, "HPOR Playback"},
  1670. };
  1671. static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1672. unsigned int rx_mask, int slots, int slot_width)
  1673. {
  1674. struct snd_soc_component *component = dai->component;
  1675. unsigned int val = 0;
  1676. switch (slots) {
  1677. case 4:
  1678. val |= RT5668_TDM_TX_CH_4;
  1679. val |= RT5668_TDM_RX_CH_4;
  1680. break;
  1681. case 6:
  1682. val |= RT5668_TDM_TX_CH_6;
  1683. val |= RT5668_TDM_RX_CH_6;
  1684. break;
  1685. case 8:
  1686. val |= RT5668_TDM_TX_CH_8;
  1687. val |= RT5668_TDM_RX_CH_8;
  1688. break;
  1689. case 2:
  1690. break;
  1691. default:
  1692. return -EINVAL;
  1693. }
  1694. snd_soc_component_update_bits(component, RT5668_TDM_CTRL,
  1695. RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val);
  1696. switch (slot_width) {
  1697. case 16:
  1698. val = RT5668_TDM_CL_16;
  1699. break;
  1700. case 20:
  1701. val = RT5668_TDM_CL_20;
  1702. break;
  1703. case 24:
  1704. val = RT5668_TDM_CL_24;
  1705. break;
  1706. case 32:
  1707. val = RT5668_TDM_CL_32;
  1708. break;
  1709. default:
  1710. return -EINVAL;
  1711. }
  1712. snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
  1713. RT5668_TDM_CL_MASK, val);
  1714. return 0;
  1715. }
  1716. static int rt5668_hw_params(struct snd_pcm_substream *substream,
  1717. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1718. {
  1719. struct snd_soc_component *component = dai->component;
  1720. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1721. unsigned int len_1 = 0, len_2 = 0;
  1722. int pre_div, frame_size;
  1723. rt5668->lrck[dai->id] = params_rate(params);
  1724. pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]);
  1725. frame_size = snd_soc_params_to_frame_size(params);
  1726. if (frame_size < 0) {
  1727. dev_err(component->dev, "Unsupported frame size: %d\n",
  1728. frame_size);
  1729. return -EINVAL;
  1730. }
  1731. dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
  1732. rt5668->lrck[dai->id], pre_div, dai->id);
  1733. switch (params_width(params)) {
  1734. case 16:
  1735. break;
  1736. case 20:
  1737. len_1 |= RT5668_I2S1_DL_20;
  1738. len_2 |= RT5668_I2S2_DL_20;
  1739. break;
  1740. case 24:
  1741. len_1 |= RT5668_I2S1_DL_24;
  1742. len_2 |= RT5668_I2S2_DL_24;
  1743. break;
  1744. case 32:
  1745. len_1 |= RT5668_I2S1_DL_32;
  1746. len_2 |= RT5668_I2S2_DL_24;
  1747. break;
  1748. case 8:
  1749. len_1 |= RT5668_I2S2_DL_8;
  1750. len_2 |= RT5668_I2S2_DL_8;
  1751. break;
  1752. default:
  1753. return -EINVAL;
  1754. }
  1755. switch (dai->id) {
  1756. case RT5668_AIF1:
  1757. snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
  1758. RT5668_I2S1_DL_MASK, len_1);
  1759. if (rt5668->master[RT5668_AIF1]) {
  1760. snd_soc_component_update_bits(component,
  1761. RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK,
  1762. pre_div << RT5668_I2S_M_DIV_SFT);
  1763. }
  1764. if (params_channels(params) == 1) /* mono mode */
  1765. snd_soc_component_update_bits(component,
  1766. RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
  1767. RT5668_I2S1_MONO_EN);
  1768. else
  1769. snd_soc_component_update_bits(component,
  1770. RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
  1771. RT5668_I2S1_MONO_DIS);
  1772. break;
  1773. case RT5668_AIF2:
  1774. snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
  1775. RT5668_I2S2_DL_MASK, len_2);
  1776. if (rt5668->master[RT5668_AIF2]) {
  1777. snd_soc_component_update_bits(component,
  1778. RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK,
  1779. pre_div << RT5668_I2S2_M_PD_SFT);
  1780. }
  1781. if (params_channels(params) == 1) /* mono mode */
  1782. snd_soc_component_update_bits(component,
  1783. RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
  1784. RT5668_I2S2_MONO_EN);
  1785. else
  1786. snd_soc_component_update_bits(component,
  1787. RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
  1788. RT5668_I2S2_MONO_DIS);
  1789. break;
  1790. default:
  1791. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  1792. return -EINVAL;
  1793. }
  1794. return 0;
  1795. }
  1796. static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1797. {
  1798. struct snd_soc_component *component = dai->component;
  1799. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1800. unsigned int reg_val = 0, tdm_ctrl = 0;
  1801. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1802. case SND_SOC_DAIFMT_CBM_CFM:
  1803. rt5668->master[dai->id] = 1;
  1804. break;
  1805. case SND_SOC_DAIFMT_CBS_CFS:
  1806. rt5668->master[dai->id] = 0;
  1807. break;
  1808. default:
  1809. return -EINVAL;
  1810. }
  1811. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1812. case SND_SOC_DAIFMT_NB_NF:
  1813. break;
  1814. case SND_SOC_DAIFMT_IB_NF:
  1815. reg_val |= RT5668_I2S_BP_INV;
  1816. tdm_ctrl |= RT5668_TDM_S_BP_INV;
  1817. break;
  1818. case SND_SOC_DAIFMT_NB_IF:
  1819. if (dai->id == RT5668_AIF1)
  1820. tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV;
  1821. else
  1822. return -EINVAL;
  1823. break;
  1824. case SND_SOC_DAIFMT_IB_IF:
  1825. if (dai->id == RT5668_AIF1)
  1826. tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV |
  1827. RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV;
  1828. else
  1829. return -EINVAL;
  1830. break;
  1831. default:
  1832. return -EINVAL;
  1833. }
  1834. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1835. case SND_SOC_DAIFMT_I2S:
  1836. break;
  1837. case SND_SOC_DAIFMT_LEFT_J:
  1838. reg_val |= RT5668_I2S_DF_LEFT;
  1839. tdm_ctrl |= RT5668_TDM_DF_LEFT;
  1840. break;
  1841. case SND_SOC_DAIFMT_DSP_A:
  1842. reg_val |= RT5668_I2S_DF_PCM_A;
  1843. tdm_ctrl |= RT5668_TDM_DF_PCM_A;
  1844. break;
  1845. case SND_SOC_DAIFMT_DSP_B:
  1846. reg_val |= RT5668_I2S_DF_PCM_B;
  1847. tdm_ctrl |= RT5668_TDM_DF_PCM_B;
  1848. break;
  1849. default:
  1850. return -EINVAL;
  1851. }
  1852. switch (dai->id) {
  1853. case RT5668_AIF1:
  1854. snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
  1855. RT5668_I2S_DF_MASK, reg_val);
  1856. snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
  1857. RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK |
  1858. RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK |
  1859. RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK,
  1860. tdm_ctrl | rt5668->master[dai->id]);
  1861. break;
  1862. case RT5668_AIF2:
  1863. if (rt5668->master[dai->id] == 0)
  1864. reg_val |= RT5668_I2S2_MS_S;
  1865. snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
  1866. RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK |
  1867. RT5668_I2S_DF_MASK, reg_val);
  1868. break;
  1869. default:
  1870. dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
  1871. return -EINVAL;
  1872. }
  1873. return 0;
  1874. }
  1875. static int rt5668_set_component_sysclk(struct snd_soc_component *component,
  1876. int clk_id, int source, unsigned int freq, int dir)
  1877. {
  1878. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1879. unsigned int reg_val = 0, src = 0;
  1880. if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src)
  1881. return 0;
  1882. switch (clk_id) {
  1883. case RT5668_SCLK_S_MCLK:
  1884. reg_val |= RT5668_SCLK_SRC_MCLK;
  1885. src = RT5668_CLK_SRC_MCLK;
  1886. break;
  1887. case RT5668_SCLK_S_PLL1:
  1888. reg_val |= RT5668_SCLK_SRC_PLL1;
  1889. src = RT5668_CLK_SRC_PLL1;
  1890. break;
  1891. case RT5668_SCLK_S_PLL2:
  1892. reg_val |= RT5668_SCLK_SRC_PLL2;
  1893. src = RT5668_CLK_SRC_PLL2;
  1894. break;
  1895. case RT5668_SCLK_S_RCCLK:
  1896. reg_val |= RT5668_SCLK_SRC_RCCLK;
  1897. src = RT5668_CLK_SRC_RCCLK;
  1898. break;
  1899. default:
  1900. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  1901. return -EINVAL;
  1902. }
  1903. snd_soc_component_update_bits(component, RT5668_GLB_CLK,
  1904. RT5668_SCLK_SRC_MASK, reg_val);
  1905. if (rt5668->master[RT5668_AIF2]) {
  1906. snd_soc_component_update_bits(component,
  1907. RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK,
  1908. src << RT5668_I2S2_SRC_SFT);
  1909. }
  1910. rt5668->sysclk = freq;
  1911. rt5668->sysclk_src = clk_id;
  1912. dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
  1913. freq, clk_id);
  1914. return 0;
  1915. }
  1916. static int rt5668_set_component_pll(struct snd_soc_component *component,
  1917. int pll_id, int source, unsigned int freq_in,
  1918. unsigned int freq_out)
  1919. {
  1920. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1921. struct rl6231_pll_code pll_code;
  1922. int ret;
  1923. if (source == rt5668->pll_src && freq_in == rt5668->pll_in &&
  1924. freq_out == rt5668->pll_out)
  1925. return 0;
  1926. if (!freq_in || !freq_out) {
  1927. dev_dbg(component->dev, "PLL disabled\n");
  1928. rt5668->pll_in = 0;
  1929. rt5668->pll_out = 0;
  1930. snd_soc_component_update_bits(component, RT5668_GLB_CLK,
  1931. RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK);
  1932. return 0;
  1933. }
  1934. switch (source) {
  1935. case RT5668_PLL1_S_MCLK:
  1936. snd_soc_component_update_bits(component, RT5668_GLB_CLK,
  1937. RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK);
  1938. break;
  1939. case RT5668_PLL1_S_BCLK1:
  1940. snd_soc_component_update_bits(component, RT5668_GLB_CLK,
  1941. RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1);
  1942. break;
  1943. default:
  1944. dev_err(component->dev, "Unknown PLL Source %d\n", source);
  1945. return -EINVAL;
  1946. }
  1947. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  1948. if (ret < 0) {
  1949. dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
  1950. return ret;
  1951. }
  1952. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  1953. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  1954. pll_code.n_code, pll_code.k_code);
  1955. snd_soc_component_write(component, RT5668_PLL_CTRL_1,
  1956. pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code);
  1957. snd_soc_component_write(component, RT5668_PLL_CTRL_2,
  1958. ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) |
  1959. (pll_code.m_bp << RT5668_PLL_M_BP_SFT));
  1960. rt5668->pll_in = freq_in;
  1961. rt5668->pll_out = freq_out;
  1962. rt5668->pll_src = source;
  1963. return 0;
  1964. }
  1965. static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  1966. {
  1967. struct snd_soc_component *component = dai->component;
  1968. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1969. rt5668->bclk[dai->id] = ratio;
  1970. switch (ratio) {
  1971. case 64:
  1972. snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
  1973. RT5668_I2S2_BCLK_MS2_MASK,
  1974. RT5668_I2S2_BCLK_MS2_64);
  1975. break;
  1976. case 32:
  1977. snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
  1978. RT5668_I2S2_BCLK_MS2_MASK,
  1979. RT5668_I2S2_BCLK_MS2_32);
  1980. break;
  1981. default:
  1982. dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
  1983. return -EINVAL;
  1984. }
  1985. return 0;
  1986. }
  1987. static int rt5668_set_bias_level(struct snd_soc_component *component,
  1988. enum snd_soc_bias_level level)
  1989. {
  1990. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  1991. switch (level) {
  1992. case SND_SOC_BIAS_PREPARE:
  1993. regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
  1994. RT5668_PWR_MB | RT5668_PWR_BG,
  1995. RT5668_PWR_MB | RT5668_PWR_BG);
  1996. regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
  1997. RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO,
  1998. RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO);
  1999. break;
  2000. case SND_SOC_BIAS_STANDBY:
  2001. regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
  2002. RT5668_PWR_MB, RT5668_PWR_MB);
  2003. regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
  2004. RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL);
  2005. break;
  2006. case SND_SOC_BIAS_OFF:
  2007. regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
  2008. RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0);
  2009. regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
  2010. RT5668_PWR_MB | RT5668_PWR_BG, 0);
  2011. break;
  2012. default:
  2013. break;
  2014. }
  2015. return 0;
  2016. }
  2017. static int rt5668_probe(struct snd_soc_component *component)
  2018. {
  2019. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  2020. rt5668->component = component;
  2021. return 0;
  2022. }
  2023. static void rt5668_remove(struct snd_soc_component *component)
  2024. {
  2025. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  2026. rt5668_reset(rt5668->regmap);
  2027. }
  2028. #ifdef CONFIG_PM
  2029. static int rt5668_suspend(struct snd_soc_component *component)
  2030. {
  2031. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  2032. regcache_cache_only(rt5668->regmap, true);
  2033. regcache_mark_dirty(rt5668->regmap);
  2034. return 0;
  2035. }
  2036. static int rt5668_resume(struct snd_soc_component *component)
  2037. {
  2038. struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
  2039. regcache_cache_only(rt5668->regmap, false);
  2040. regcache_sync(rt5668->regmap);
  2041. return 0;
  2042. }
  2043. #else
  2044. #define rt5668_suspend NULL
  2045. #define rt5668_resume NULL
  2046. #endif
  2047. #define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000
  2048. #define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  2049. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  2050. static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = {
  2051. .hw_params = rt5668_hw_params,
  2052. .set_fmt = rt5668_set_dai_fmt,
  2053. .set_tdm_slot = rt5668_set_tdm_slot,
  2054. };
  2055. static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = {
  2056. .hw_params = rt5668_hw_params,
  2057. .set_fmt = rt5668_set_dai_fmt,
  2058. .set_bclk_ratio = rt5668_set_bclk_ratio,
  2059. };
  2060. static struct snd_soc_dai_driver rt5668_dai[] = {
  2061. {
  2062. .name = "rt5668-aif1",
  2063. .id = RT5668_AIF1,
  2064. .playback = {
  2065. .stream_name = "AIF1 Playback",
  2066. .channels_min = 1,
  2067. .channels_max = 2,
  2068. .rates = RT5668_STEREO_RATES,
  2069. .formats = RT5668_FORMATS,
  2070. },
  2071. .capture = {
  2072. .stream_name = "AIF1 Capture",
  2073. .channels_min = 1,
  2074. .channels_max = 2,
  2075. .rates = RT5668_STEREO_RATES,
  2076. .formats = RT5668_FORMATS,
  2077. },
  2078. .ops = &rt5668_aif1_dai_ops,
  2079. },
  2080. {
  2081. .name = "rt5668-aif2",
  2082. .id = RT5668_AIF2,
  2083. .capture = {
  2084. .stream_name = "AIF2 Capture",
  2085. .channels_min = 1,
  2086. .channels_max = 2,
  2087. .rates = RT5668_STEREO_RATES,
  2088. .formats = RT5668_FORMATS,
  2089. },
  2090. .ops = &rt5668_aif2_dai_ops,
  2091. },
  2092. };
  2093. static const struct snd_soc_component_driver soc_component_dev_rt5668 = {
  2094. .probe = rt5668_probe,
  2095. .remove = rt5668_remove,
  2096. .suspend = rt5668_suspend,
  2097. .resume = rt5668_resume,
  2098. .set_bias_level = rt5668_set_bias_level,
  2099. .controls = rt5668_snd_controls,
  2100. .num_controls = ARRAY_SIZE(rt5668_snd_controls),
  2101. .dapm_widgets = rt5668_dapm_widgets,
  2102. .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets),
  2103. .dapm_routes = rt5668_dapm_routes,
  2104. .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes),
  2105. .set_sysclk = rt5668_set_component_sysclk,
  2106. .set_pll = rt5668_set_component_pll,
  2107. .set_jack = rt5668_set_jack_detect,
  2108. .use_pmdown_time = 1,
  2109. .endianness = 1,
  2110. };
  2111. static const struct regmap_config rt5668_regmap = {
  2112. .reg_bits = 16,
  2113. .val_bits = 16,
  2114. .max_register = RT5668_I2C_MODE,
  2115. .volatile_reg = rt5668_volatile_register,
  2116. .readable_reg = rt5668_readable_register,
  2117. .cache_type = REGCACHE_RBTREE,
  2118. .reg_defaults = rt5668_reg,
  2119. .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
  2120. .use_single_read = true,
  2121. .use_single_write = true,
  2122. };
  2123. static const struct i2c_device_id rt5668_i2c_id[] = {
  2124. {"rt5668b", 0},
  2125. {}
  2126. };
  2127. MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id);
  2128. static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev)
  2129. {
  2130. of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
  2131. &rt5668->pdata.dmic1_data_pin);
  2132. of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin",
  2133. &rt5668->pdata.dmic1_clk_pin);
  2134. of_property_read_u32(dev->of_node, "realtek,jd-src",
  2135. &rt5668->pdata.jd_src);
  2136. rt5668->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
  2137. "realtek,ldo1-en-gpios", 0);
  2138. return 0;
  2139. }
  2140. static void rt5668_calibrate(struct rt5668_priv *rt5668)
  2141. {
  2142. int value, count;
  2143. mutex_lock(&rt5668->calibrate_mutex);
  2144. rt5668_reset(rt5668->regmap);
  2145. regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf);
  2146. usleep_range(15000, 20000);
  2147. regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf);
  2148. regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
  2149. regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001);
  2150. regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
  2151. regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080);
  2152. regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040);
  2153. regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069);
  2154. regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000);
  2155. regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000);
  2156. regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26);
  2157. regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05);
  2158. regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c);
  2159. regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d);
  2160. regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f);
  2161. regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01);
  2162. regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321);
  2163. regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004);
  2164. regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00);
  2165. regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1);
  2166. regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311);
  2167. regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000);
  2168. regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320);
  2169. regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00);
  2170. for (count = 0; count < 60; count++) {
  2171. regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value);
  2172. if (!(value & 0x8000))
  2173. break;
  2174. usleep_range(10000, 10005);
  2175. }
  2176. if (count >= 60)
  2177. pr_err("HP Calibration Failure\n");
  2178. /* restore settings */
  2179. regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4);
  2180. regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000);
  2181. mutex_unlock(&rt5668->calibrate_mutex);
  2182. }
  2183. static int rt5668_i2c_probe(struct i2c_client *i2c)
  2184. {
  2185. struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev);
  2186. struct rt5668_priv *rt5668;
  2187. int i, ret;
  2188. unsigned int val;
  2189. rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv),
  2190. GFP_KERNEL);
  2191. if (rt5668 == NULL)
  2192. return -ENOMEM;
  2193. i2c_set_clientdata(i2c, rt5668);
  2194. if (pdata)
  2195. rt5668->pdata = *pdata;
  2196. else
  2197. rt5668_parse_dt(rt5668, &i2c->dev);
  2198. rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
  2199. if (IS_ERR(rt5668->regmap)) {
  2200. ret = PTR_ERR(rt5668->regmap);
  2201. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  2202. ret);
  2203. return ret;
  2204. }
  2205. for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++)
  2206. rt5668->supplies[i].supply = rt5668_supply_names[i];
  2207. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies),
  2208. rt5668->supplies);
  2209. if (ret != 0) {
  2210. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  2211. return ret;
  2212. }
  2213. ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies),
  2214. rt5668->supplies);
  2215. if (ret != 0) {
  2216. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  2217. return ret;
  2218. }
  2219. if (gpio_is_valid(rt5668->pdata.ldo1_en)) {
  2220. if (devm_gpio_request_one(&i2c->dev, rt5668->pdata.ldo1_en,
  2221. GPIOF_OUT_INIT_HIGH, "rt5668"))
  2222. dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
  2223. }
  2224. /* Sleep for 300 ms miniumum */
  2225. usleep_range(300000, 350000);
  2226. regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1);
  2227. usleep_range(10000, 15000);
  2228. regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val);
  2229. if (val != DEVICE_ID) {
  2230. pr_err("Device with ID register %x is not rt5668\n", val);
  2231. return -ENODEV;
  2232. }
  2233. rt5668_reset(rt5668->regmap);
  2234. rt5668_calibrate(rt5668);
  2235. regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000);
  2236. /* DMIC pin*/
  2237. if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) {
  2238. switch (rt5668->pdata.dmic1_data_pin) {
  2239. case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */
  2240. regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
  2241. RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2);
  2242. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  2243. RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA);
  2244. break;
  2245. case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
  2246. regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
  2247. RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5);
  2248. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  2249. RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA);
  2250. break;
  2251. default:
  2252. dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n");
  2253. break;
  2254. }
  2255. switch (rt5668->pdata.dmic1_clk_pin) {
  2256. case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */
  2257. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  2258. RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK);
  2259. break;
  2260. case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */
  2261. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  2262. RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK);
  2263. break;
  2264. default:
  2265. dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n");
  2266. break;
  2267. }
  2268. }
  2269. regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
  2270. RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK,
  2271. RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X);
  2272. regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
  2273. regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
  2274. RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK,
  2275. RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1);
  2276. regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
  2277. INIT_DELAYED_WORK(&rt5668->jack_detect_work,
  2278. rt5668_jack_detect_handler);
  2279. INIT_DELAYED_WORK(&rt5668->jd_check_work,
  2280. rt5668_jd_check_handler);
  2281. mutex_init(&rt5668->calibrate_mutex);
  2282. if (i2c->irq) {
  2283. ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
  2284. rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  2285. | IRQF_ONESHOT, "rt5668", rt5668);
  2286. if (ret)
  2287. dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
  2288. }
  2289. return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668,
  2290. rt5668_dai, ARRAY_SIZE(rt5668_dai));
  2291. }
  2292. static void rt5668_i2c_shutdown(struct i2c_client *client)
  2293. {
  2294. struct rt5668_priv *rt5668 = i2c_get_clientdata(client);
  2295. rt5668_reset(rt5668->regmap);
  2296. }
  2297. #ifdef CONFIG_OF
  2298. static const struct of_device_id rt5668_of_match[] = {
  2299. {.compatible = "realtek,rt5668b"},
  2300. {},
  2301. };
  2302. MODULE_DEVICE_TABLE(of, rt5668_of_match);
  2303. #endif
  2304. #ifdef CONFIG_ACPI
  2305. static const struct acpi_device_id rt5668_acpi_match[] = {
  2306. {"10EC5668", 0,},
  2307. {},
  2308. };
  2309. MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match);
  2310. #endif
  2311. static struct i2c_driver rt5668_i2c_driver = {
  2312. .driver = {
  2313. .name = "rt5668b",
  2314. .of_match_table = of_match_ptr(rt5668_of_match),
  2315. .acpi_match_table = ACPI_PTR(rt5668_acpi_match),
  2316. },
  2317. .probe_new = rt5668_i2c_probe,
  2318. .shutdown = rt5668_i2c_shutdown,
  2319. .id_table = rt5668_i2c_id,
  2320. };
  2321. module_i2c_driver(rt5668_i2c_driver);
  2322. MODULE_DESCRIPTION("ASoC RT5668B driver");
  2323. MODULE_AUTHOR("Bard Liao <[email protected]>");
  2324. MODULE_LICENSE("GPL v2");