rt5514.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt5514.c -- RT5514 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2015 Realtek Semiconductor Corp.
  6. * Author: Oder Chiou <[email protected]>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/fs.h>
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/regmap.h>
  16. #include <linux/i2c.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/firmware.h>
  19. #include <linux/gpio.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "rl6231.h"
  28. #include "rt5514.h"
  29. #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  30. #include "rt5514-spi.h"
  31. #endif
  32. static const struct reg_sequence rt5514_i2c_patch[] = {
  33. {0x1800101c, 0x00000000},
  34. {0x18001100, 0x0000031f},
  35. {0x18001104, 0x00000007},
  36. {0x18001108, 0x00000000},
  37. {0x1800110c, 0x00000000},
  38. {0x18001110, 0x00000000},
  39. {0x18001114, 0x00000001},
  40. {0x18001118, 0x00000000},
  41. {0x18002f08, 0x00000006},
  42. {0x18002f00, 0x00055149},
  43. {0x18002f00, 0x0005514b},
  44. {0x18002f00, 0x00055149},
  45. {0xfafafafa, 0x00000001},
  46. {0x18002f10, 0x00000001},
  47. {0x18002f10, 0x00000000},
  48. {0x18002f10, 0x00000001},
  49. {0xfafafafa, 0x00000001},
  50. {0x18002000, 0x000010ec},
  51. {0xfafafafa, 0x00000000},
  52. };
  53. static const struct reg_sequence rt5514_patch[] = {
  54. {RT5514_DIG_IO_CTRL, 0x00000040},
  55. {RT5514_CLK_CTRL1, 0x38020041},
  56. {RT5514_SRC_CTRL, 0x44000eee},
  57. {RT5514_ANA_CTRL_LDO10, 0x00028604},
  58. {RT5514_ANA_CTRL_ADCFED, 0x00000800},
  59. {RT5514_ASRC_IN_CTRL1, 0x00000003},
  60. {RT5514_DOWNFILTER0_CTRL3, 0x10000342},
  61. {RT5514_DOWNFILTER1_CTRL3, 0x10000342},
  62. };
  63. static const struct reg_default rt5514_reg[] = {
  64. {RT5514_RESET, 0x00000000},
  65. {RT5514_PWR_ANA1, 0x00808880},
  66. {RT5514_PWR_ANA2, 0x00220000},
  67. {RT5514_I2S_CTRL1, 0x00000330},
  68. {RT5514_I2S_CTRL2, 0x20000000},
  69. {RT5514_VAD_CTRL6, 0xc00007d2},
  70. {RT5514_EXT_VAD_CTRL, 0x80000080},
  71. {RT5514_DIG_IO_CTRL, 0x00000040},
  72. {RT5514_PAD_CTRL1, 0x00804000},
  73. {RT5514_DMIC_DATA_CTRL, 0x00000005},
  74. {RT5514_DIG_SOURCE_CTRL, 0x00000002},
  75. {RT5514_SRC_CTRL, 0x44000eee},
  76. {RT5514_DOWNFILTER2_CTRL1, 0x0000882f},
  77. {RT5514_PLL_SOURCE_CTRL, 0x00000004},
  78. {RT5514_CLK_CTRL1, 0x38020041},
  79. {RT5514_CLK_CTRL2, 0x00000000},
  80. {RT5514_PLL3_CALIB_CTRL1, 0x00400200},
  81. {RT5514_PLL3_CALIB_CTRL5, 0x40220012},
  82. {RT5514_DELAY_BUF_CTRL1, 0x7fff006a},
  83. {RT5514_DELAY_BUF_CTRL3, 0x00000000},
  84. {RT5514_ASRC_IN_CTRL1, 0x00000003},
  85. {RT5514_DOWNFILTER0_CTRL1, 0x00020c2f},
  86. {RT5514_DOWNFILTER0_CTRL2, 0x00020c2f},
  87. {RT5514_DOWNFILTER0_CTRL3, 0x10000342},
  88. {RT5514_DOWNFILTER1_CTRL1, 0x00020c2f},
  89. {RT5514_DOWNFILTER1_CTRL2, 0x00020c2f},
  90. {RT5514_DOWNFILTER1_CTRL3, 0x10000342},
  91. {RT5514_ANA_CTRL_LDO10, 0x00028604},
  92. {RT5514_ANA_CTRL_LDO18_16, 0x02000345},
  93. {RT5514_ANA_CTRL_ADC12, 0x0000a2a8},
  94. {RT5514_ANA_CTRL_ADC21, 0x00001180},
  95. {RT5514_ANA_CTRL_ADC22, 0x0000aaa8},
  96. {RT5514_ANA_CTRL_ADC23, 0x00151427},
  97. {RT5514_ANA_CTRL_MICBST, 0x00002000},
  98. {RT5514_ANA_CTRL_ADCFED, 0x00000800},
  99. {RT5514_ANA_CTRL_INBUF, 0x00000143},
  100. {RT5514_ANA_CTRL_VREF, 0x00008d50},
  101. {RT5514_ANA_CTRL_PLL3, 0x0000000e},
  102. {RT5514_ANA_CTRL_PLL1_1, 0x00000000},
  103. {RT5514_ANA_CTRL_PLL1_2, 0x00030220},
  104. {RT5514_DMIC_LP_CTRL, 0x00000000},
  105. {RT5514_MISC_CTRL_DSP, 0x00000000},
  106. {RT5514_DSP_CTRL1, 0x00055149},
  107. {RT5514_DSP_CTRL3, 0x00000006},
  108. {RT5514_DSP_CTRL4, 0x00000001},
  109. {RT5514_VENDOR_ID1, 0x00000001},
  110. {RT5514_VENDOR_ID2, 0x10ec5514},
  111. };
  112. static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
  113. {
  114. /* Reset */
  115. regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
  116. /* LDO_I_limit */
  117. regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
  118. /* I2C bypass enable */
  119. regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
  120. /* mini-core reset */
  121. regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
  122. regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
  123. /* I2C bypass disable */
  124. regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
  125. /* PIN config */
  126. regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
  127. /* PLL3(QN)=RCOSC*(10+2) */
  128. regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
  129. /* PLL3 source=RCOSC, fsi=rt_clk */
  130. regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
  131. /* Power on RCOSC, pll3 */
  132. regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
  133. /* DSP clk source = pll3, ENABLE DSP clk */
  134. regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
  135. /* Enable DSP clk auto switch */
  136. regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
  137. /* Reduce DSP power */
  138. regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
  139. }
  140. static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
  141. {
  142. switch (reg) {
  143. case RT5514_VENDOR_ID1:
  144. case RT5514_VENDOR_ID2:
  145. return true;
  146. default:
  147. return false;
  148. }
  149. }
  150. static bool rt5514_readable_register(struct device *dev, unsigned int reg)
  151. {
  152. switch (reg) {
  153. case RT5514_RESET:
  154. case RT5514_PWR_ANA1:
  155. case RT5514_PWR_ANA2:
  156. case RT5514_I2S_CTRL1:
  157. case RT5514_I2S_CTRL2:
  158. case RT5514_VAD_CTRL6:
  159. case RT5514_EXT_VAD_CTRL:
  160. case RT5514_DIG_IO_CTRL:
  161. case RT5514_PAD_CTRL1:
  162. case RT5514_DMIC_DATA_CTRL:
  163. case RT5514_DIG_SOURCE_CTRL:
  164. case RT5514_SRC_CTRL:
  165. case RT5514_DOWNFILTER2_CTRL1:
  166. case RT5514_PLL_SOURCE_CTRL:
  167. case RT5514_CLK_CTRL1:
  168. case RT5514_CLK_CTRL2:
  169. case RT5514_PLL3_CALIB_CTRL1:
  170. case RT5514_PLL3_CALIB_CTRL5:
  171. case RT5514_DELAY_BUF_CTRL1:
  172. case RT5514_DELAY_BUF_CTRL3:
  173. case RT5514_ASRC_IN_CTRL1:
  174. case RT5514_DOWNFILTER0_CTRL1:
  175. case RT5514_DOWNFILTER0_CTRL2:
  176. case RT5514_DOWNFILTER0_CTRL3:
  177. case RT5514_DOWNFILTER1_CTRL1:
  178. case RT5514_DOWNFILTER1_CTRL2:
  179. case RT5514_DOWNFILTER1_CTRL3:
  180. case RT5514_ANA_CTRL_LDO10:
  181. case RT5514_ANA_CTRL_LDO18_16:
  182. case RT5514_ANA_CTRL_ADC12:
  183. case RT5514_ANA_CTRL_ADC21:
  184. case RT5514_ANA_CTRL_ADC22:
  185. case RT5514_ANA_CTRL_ADC23:
  186. case RT5514_ANA_CTRL_MICBST:
  187. case RT5514_ANA_CTRL_ADCFED:
  188. case RT5514_ANA_CTRL_INBUF:
  189. case RT5514_ANA_CTRL_VREF:
  190. case RT5514_ANA_CTRL_PLL3:
  191. case RT5514_ANA_CTRL_PLL1_1:
  192. case RT5514_ANA_CTRL_PLL1_2:
  193. case RT5514_DMIC_LP_CTRL:
  194. case RT5514_MISC_CTRL_DSP:
  195. case RT5514_DSP_CTRL1:
  196. case RT5514_DSP_CTRL3:
  197. case RT5514_DSP_CTRL4:
  198. case RT5514_VENDOR_ID1:
  199. case RT5514_VENDOR_ID2:
  200. return true;
  201. default:
  202. return false;
  203. }
  204. }
  205. static bool rt5514_i2c_readable_register(struct device *dev,
  206. unsigned int reg)
  207. {
  208. switch (reg) {
  209. case RT5514_DSP_MAPPING | RT5514_RESET:
  210. case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
  211. case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
  212. case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
  213. case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
  214. case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
  215. case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
  216. case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
  217. case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
  218. case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
  219. case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
  220. case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
  221. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
  222. case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
  223. case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
  224. case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
  225. case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
  226. case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
  227. case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
  228. case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
  229. case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
  230. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
  231. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
  232. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
  233. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
  234. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
  235. case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
  236. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
  237. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
  238. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
  239. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
  240. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
  241. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
  242. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
  243. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
  244. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
  245. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
  246. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
  247. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
  248. case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
  249. case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
  250. case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
  251. case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
  252. case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
  253. case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
  254. case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
  255. case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
  256. return true;
  257. default:
  258. return false;
  259. }
  260. }
  261. /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
  262. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  263. 0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
  264. 3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
  265. 4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
  266. 5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
  267. 6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
  268. 7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
  269. 8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
  270. );
  271. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
  272. static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
  273. struct snd_ctl_elem_value *ucontrol)
  274. {
  275. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  276. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  277. ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
  278. return 0;
  279. }
  280. static int rt5514_calibration(struct rt5514_priv *rt5514, bool on)
  281. {
  282. if (on) {
  283. regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL3, 0x0000000a);
  284. regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
  285. 0xa);
  286. regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301,
  287. 0x301);
  288. regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL4,
  289. 0x80000000 | rt5514->pll3_cal_value);
  290. regmap_write(rt5514->regmap, RT5514_PLL3_CALIB_CTRL1,
  291. 0x8bb80800);
  292. regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
  293. 0xc0000000, 0x80000000);
  294. regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
  295. 0xc0000000, 0xc0000000);
  296. } else {
  297. regmap_update_bits(rt5514->regmap, RT5514_PLL3_CALIB_CTRL5,
  298. 0xc0000000, 0x40000000);
  299. regmap_update_bits(rt5514->regmap, RT5514_PWR_ANA1, 0x301, 0);
  300. regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL, 0xf,
  301. 0x4);
  302. }
  303. return 0;
  304. }
  305. static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
  306. struct snd_ctl_elem_value *ucontrol)
  307. {
  308. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  309. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  310. const struct firmware *fw = NULL;
  311. u8 buf[8];
  312. if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
  313. return 0;
  314. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  315. rt5514->dsp_enabled = ucontrol->value.integer.value[0];
  316. if (rt5514->dsp_enabled) {
  317. if (rt5514->pdata.dsp_calib_clk_name &&
  318. !IS_ERR(rt5514->dsp_calib_clk)) {
  319. if (clk_set_rate(rt5514->dsp_calib_clk,
  320. rt5514->pdata.dsp_calib_clk_rate))
  321. dev_err(component->dev,
  322. "Can't set rate for mclk");
  323. if (clk_prepare_enable(rt5514->dsp_calib_clk))
  324. dev_err(component->dev,
  325. "Can't enable dsp_calib_clk");
  326. rt5514_calibration(rt5514, true);
  327. msleep(20);
  328. #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  329. rt5514_spi_burst_read(RT5514_PLL3_CALIB_CTRL6 |
  330. RT5514_DSP_MAPPING, buf, sizeof(buf));
  331. #else
  332. dev_err(component->dev, "There is no SPI driver for"
  333. " loading the firmware\n");
  334. memset(buf, 0, sizeof(buf));
  335. #endif
  336. rt5514->pll3_cal_value = buf[0] | buf[1] << 8 |
  337. buf[2] << 16 | buf[3] << 24;
  338. rt5514_calibration(rt5514, false);
  339. clk_disable_unprepare(rt5514->dsp_calib_clk);
  340. }
  341. rt5514_enable_dsp_prepare(rt5514);
  342. request_firmware(&fw, RT5514_FIRMWARE1, component->dev);
  343. if (fw) {
  344. #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  345. rt5514_spi_burst_write(0x4ff60000, fw->data,
  346. ((fw->size/8)+1)*8);
  347. #else
  348. dev_err(component->dev, "There is no SPI driver for"
  349. " loading the firmware\n");
  350. #endif
  351. release_firmware(fw);
  352. fw = NULL;
  353. }
  354. request_firmware(&fw, RT5514_FIRMWARE2, component->dev);
  355. if (fw) {
  356. #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  357. rt5514_spi_burst_write(0x4ffc0000, fw->data,
  358. ((fw->size/8)+1)*8);
  359. #else
  360. dev_err(component->dev, "There is no SPI driver for"
  361. " loading the firmware\n");
  362. #endif
  363. release_firmware(fw);
  364. fw = NULL;
  365. }
  366. /* DSP run */
  367. regmap_write(rt5514->i2c_regmap, 0x18002f00,
  368. 0x00055148);
  369. if (rt5514->pdata.dsp_calib_clk_name &&
  370. !IS_ERR(rt5514->dsp_calib_clk)) {
  371. msleep(20);
  372. regmap_write(rt5514->i2c_regmap, 0x1800211c,
  373. rt5514->pll3_cal_value);
  374. regmap_write(rt5514->i2c_regmap, 0x18002124,
  375. 0x00220012);
  376. regmap_write(rt5514->i2c_regmap, 0x18002124,
  377. 0x80220042);
  378. regmap_write(rt5514->i2c_regmap, 0x18002124,
  379. 0xe0220042);
  380. }
  381. } else {
  382. regmap_multi_reg_write(rt5514->i2c_regmap,
  383. rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
  384. regcache_mark_dirty(rt5514->regmap);
  385. regcache_sync(rt5514->regmap);
  386. }
  387. }
  388. return 1;
  389. }
  390. static const struct snd_kcontrol_new rt5514_snd_controls[] = {
  391. SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
  392. RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
  393. SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
  394. RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
  395. adc_vol_tlv),
  396. SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
  397. RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
  398. adc_vol_tlv),
  399. SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
  400. rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
  401. };
  402. /* ADC Mixer*/
  403. static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
  404. SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
  405. RT5514_AD_DMIC_MIX_BIT, 1, 1),
  406. SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
  407. RT5514_AD_AD_MIX_BIT, 1, 1),
  408. };
  409. static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
  410. SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
  411. RT5514_AD_DMIC_MIX_BIT, 1, 1),
  412. SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
  413. RT5514_AD_AD_MIX_BIT, 1, 1),
  414. };
  415. static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
  416. SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
  417. RT5514_AD_DMIC_MIX_BIT, 1, 1),
  418. SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
  419. RT5514_AD_AD_MIX_BIT, 1, 1),
  420. };
  421. static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
  422. SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
  423. RT5514_AD_DMIC_MIX_BIT, 1, 1),
  424. SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
  425. RT5514_AD_AD_MIX_BIT, 1, 1),
  426. };
  427. /* DMIC Source */
  428. static const char * const rt5514_dmic_src[] = {
  429. "DMIC1", "DMIC2"
  430. };
  431. static SOC_ENUM_SINGLE_DECL(
  432. rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
  433. RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
  434. static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
  435. SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
  436. static SOC_ENUM_SINGLE_DECL(
  437. rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
  438. RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
  439. static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
  440. SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
  441. /**
  442. * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
  443. *
  444. * @component: only used for dev_warn
  445. * @rate: base clock rate.
  446. *
  447. * Choose divider parameter that gives the highest possible DMIC frequency in
  448. * 1MHz - 3MHz range.
  449. */
  450. static int rt5514_calc_dmic_clk(struct snd_soc_component *component, int rate)
  451. {
  452. static const int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
  453. int i;
  454. if (rate < 1000000 * div[0]) {
  455. pr_warn("Base clock rate %d is too low\n", rate);
  456. return -EINVAL;
  457. }
  458. for (i = 0; i < ARRAY_SIZE(div); i++) {
  459. /* find divider that gives DMIC frequency below 3.072MHz */
  460. if (3072000 * div[i] >= rate)
  461. return i;
  462. }
  463. dev_warn(component->dev, "Base clock rate %d is too high\n", rate);
  464. return -EINVAL;
  465. }
  466. static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
  467. struct snd_kcontrol *kcontrol, int event)
  468. {
  469. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  470. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  471. int idx;
  472. idx = rt5514_calc_dmic_clk(component, rt5514->sysclk);
  473. if (idx < 0)
  474. dev_err(component->dev, "Failed to set DMIC clock\n");
  475. else
  476. regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
  477. RT5514_CLK_DMIC_OUT_SEL_MASK,
  478. idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
  479. if (rt5514->pdata.dmic_init_delay)
  480. msleep(rt5514->pdata.dmic_init_delay);
  481. return idx;
  482. }
  483. static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
  484. struct snd_soc_dapm_widget *sink)
  485. {
  486. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  487. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  488. if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
  489. return 1;
  490. else
  491. return 0;
  492. }
  493. static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
  494. struct snd_soc_dapm_widget *sink)
  495. {
  496. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  497. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  498. return (rt5514->sysclk > rt5514->lrck * 384);
  499. }
  500. static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
  501. /* Input Lines */
  502. SND_SOC_DAPM_INPUT("DMIC1L"),
  503. SND_SOC_DAPM_INPUT("DMIC1R"),
  504. SND_SOC_DAPM_INPUT("DMIC2L"),
  505. SND_SOC_DAPM_INPUT("DMIC2R"),
  506. SND_SOC_DAPM_INPUT("AMICL"),
  507. SND_SOC_DAPM_INPUT("AMICR"),
  508. SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  509. SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  510. SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
  511. rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  512. SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
  513. RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
  514. SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
  515. RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
  516. SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
  517. RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
  518. SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
  519. NULL, 0),
  520. SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
  521. RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
  522. SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
  523. RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
  524. SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
  525. RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
  526. SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
  527. NULL, 0),
  528. SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
  529. NULL, 0),
  530. SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
  531. NULL, 0),
  532. SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
  533. SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
  534. NULL, 0),
  535. SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
  536. NULL, 0),
  537. SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
  538. NULL, 0),
  539. SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
  540. NULL, 0),
  541. SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
  542. 0, NULL, 0),
  543. SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
  544. SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
  545. NULL, 0),
  546. SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
  547. NULL, 0),
  548. SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
  549. NULL, 0),
  550. SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
  551. NULL, 0),
  552. SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
  553. 0, NULL, 0),
  554. SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
  555. SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
  556. RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
  557. SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
  558. RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
  559. SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
  560. NULL, 0),
  561. SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
  562. RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
  563. SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
  564. RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
  565. /* ADC Mux */
  566. SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
  567. &rt5514_sto1_dmic_mux),
  568. SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
  569. &rt5514_sto2_dmic_mux),
  570. /* ADC Mixer */
  571. SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
  572. RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
  573. SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
  574. RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
  575. SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  576. rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
  577. SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  578. rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
  579. SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
  580. rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
  581. SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
  582. rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
  583. SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
  584. RT5514_AD_AD_MUTE_BIT, 1),
  585. SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
  586. RT5514_AD_AD_MUTE_BIT, 1),
  587. SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
  588. RT5514_AD_AD_MUTE_BIT, 1),
  589. SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
  590. RT5514_AD_AD_MUTE_BIT, 1),
  591. /* ADC PGA */
  592. SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  593. SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  594. /* Audio Interface */
  595. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  596. };
  597. static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
  598. { "DMIC1", NULL, "DMIC1L" },
  599. { "DMIC1", NULL, "DMIC1R" },
  600. { "DMIC2", NULL, "DMIC2L" },
  601. { "DMIC2", NULL, "DMIC2R" },
  602. { "DMIC1L", NULL, "DMIC CLK" },
  603. { "DMIC1R", NULL, "DMIC CLK" },
  604. { "DMIC2L", NULL, "DMIC CLK" },
  605. { "DMIC2R", NULL, "DMIC CLK" },
  606. { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
  607. { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
  608. { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
  609. { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
  610. { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
  611. { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
  612. { "ADC Power", NULL, "LDO18 IN" },
  613. { "ADC Power", NULL, "LDO18 ADC" },
  614. { "ADC Power", NULL, "LDO21" },
  615. { "ADC Power", NULL, "BG LDO18 IN" },
  616. { "ADC Power", NULL, "BG LDO21" },
  617. { "ADC Power", NULL, "BG MBIAS" },
  618. { "ADC Power", NULL, "MBIAS" },
  619. { "ADC Power", NULL, "VREF2" },
  620. { "ADC Power", NULL, "VREF1" },
  621. { "ADCL Power", NULL, "LDO16L" },
  622. { "ADCL Power", NULL, "ADC1L" },
  623. { "ADCL Power", NULL, "BSTL2" },
  624. { "ADCL Power", NULL, "BSTL" },
  625. { "ADCL Power", NULL, "ADCFEDL" },
  626. { "ADCR Power", NULL, "LDO16R" },
  627. { "ADCR Power", NULL, "ADC1R" },
  628. { "ADCR Power", NULL, "BSTR2" },
  629. { "ADCR Power", NULL, "BSTR" },
  630. { "ADCR Power", NULL, "ADCFEDR" },
  631. { "AMICL", NULL, "ADC CLK" },
  632. { "AMICL", NULL, "ADC Power" },
  633. { "AMICL", NULL, "ADCL Power" },
  634. { "AMICR", NULL, "ADC CLK" },
  635. { "AMICR", NULL, "ADC Power" },
  636. { "AMICR", NULL, "ADCR Power" },
  637. { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
  638. { "PLL1", NULL, "PLL1 LDO" },
  639. { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
  640. { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
  641. { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
  642. { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
  643. { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
  644. { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
  645. { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
  646. { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
  647. { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
  648. { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
  649. { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
  650. { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
  651. { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
  652. { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
  653. { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
  654. { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
  655. { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
  656. { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
  657. { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
  658. { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
  659. { "AIF1TX", NULL, "Stereo1 ADC MIX"},
  660. { "AIF1TX", NULL, "Stereo2 ADC MIX"},
  661. };
  662. static int rt5514_hw_params(struct snd_pcm_substream *substream,
  663. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  664. {
  665. struct snd_soc_component *component = dai->component;
  666. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  667. int pre_div, bclk_ms, frame_size;
  668. unsigned int val_len = 0;
  669. rt5514->lrck = params_rate(params);
  670. pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
  671. if (pre_div < 0) {
  672. dev_err(component->dev, "Unsupported clock setting\n");
  673. return -EINVAL;
  674. }
  675. frame_size = snd_soc_params_to_frame_size(params);
  676. if (frame_size < 0) {
  677. dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
  678. return -EINVAL;
  679. }
  680. bclk_ms = frame_size > 32;
  681. rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
  682. dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  683. rt5514->bclk, rt5514->lrck);
  684. dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  685. bclk_ms, pre_div, dai->id);
  686. switch (params_format(params)) {
  687. case SNDRV_PCM_FORMAT_S16_LE:
  688. break;
  689. case SNDRV_PCM_FORMAT_S20_3LE:
  690. val_len = RT5514_I2S_DL_20;
  691. break;
  692. case SNDRV_PCM_FORMAT_S24_LE:
  693. val_len = RT5514_I2S_DL_24;
  694. break;
  695. case SNDRV_PCM_FORMAT_S8:
  696. val_len = RT5514_I2S_DL_8;
  697. break;
  698. default:
  699. return -EINVAL;
  700. }
  701. regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
  702. val_len);
  703. regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
  704. RT5514_CLK_AD_ANA1_SEL_MASK,
  705. (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
  706. regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
  707. RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
  708. pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
  709. pre_div << RT5514_SEL_ADC_OSR_SFT);
  710. return 0;
  711. }
  712. static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  713. {
  714. struct snd_soc_component *component = dai->component;
  715. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  716. unsigned int reg_val = 0;
  717. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  718. case SND_SOC_DAIFMT_NB_NF:
  719. break;
  720. case SND_SOC_DAIFMT_NB_IF:
  721. reg_val |= RT5514_I2S_LR_INV;
  722. break;
  723. case SND_SOC_DAIFMT_IB_NF:
  724. reg_val |= RT5514_I2S_BP_INV;
  725. break;
  726. case SND_SOC_DAIFMT_IB_IF:
  727. reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
  728. break;
  729. default:
  730. return -EINVAL;
  731. }
  732. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  733. case SND_SOC_DAIFMT_I2S:
  734. break;
  735. case SND_SOC_DAIFMT_LEFT_J:
  736. reg_val |= RT5514_I2S_DF_LEFT;
  737. break;
  738. case SND_SOC_DAIFMT_DSP_A:
  739. reg_val |= RT5514_I2S_DF_PCM_A;
  740. break;
  741. case SND_SOC_DAIFMT_DSP_B:
  742. reg_val |= RT5514_I2S_DF_PCM_B;
  743. break;
  744. default:
  745. return -EINVAL;
  746. }
  747. regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
  748. RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
  749. reg_val);
  750. return 0;
  751. }
  752. static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
  753. int clk_id, unsigned int freq, int dir)
  754. {
  755. struct snd_soc_component *component = dai->component;
  756. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  757. unsigned int reg_val = 0;
  758. if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
  759. return 0;
  760. switch (clk_id) {
  761. case RT5514_SCLK_S_MCLK:
  762. reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
  763. break;
  764. case RT5514_SCLK_S_PLL1:
  765. reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
  766. break;
  767. default:
  768. dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
  769. return -EINVAL;
  770. }
  771. regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
  772. RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
  773. rt5514->sysclk = freq;
  774. rt5514->sysclk_src = clk_id;
  775. dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  776. return 0;
  777. }
  778. static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  779. unsigned int freq_in, unsigned int freq_out)
  780. {
  781. struct snd_soc_component *component = dai->component;
  782. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  783. struct rl6231_pll_code pll_code;
  784. int ret;
  785. if (!freq_in || !freq_out) {
  786. dev_dbg(component->dev, "PLL disabled\n");
  787. rt5514->pll_in = 0;
  788. rt5514->pll_out = 0;
  789. regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
  790. RT5514_CLK_SYS_PRE_SEL_MASK,
  791. RT5514_CLK_SYS_PRE_SEL_MCLK);
  792. return 0;
  793. }
  794. if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
  795. freq_out == rt5514->pll_out)
  796. return 0;
  797. switch (source) {
  798. case RT5514_PLL1_S_MCLK:
  799. regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
  800. RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
  801. break;
  802. case RT5514_PLL1_S_BCLK:
  803. regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
  804. RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
  805. break;
  806. default:
  807. dev_err(component->dev, "Unknown PLL source %d\n", source);
  808. return -EINVAL;
  809. }
  810. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  811. if (ret < 0) {
  812. dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
  813. return ret;
  814. }
  815. dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
  816. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  817. pll_code.n_code, pll_code.k_code);
  818. regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
  819. pll_code.k_code << RT5514_PLL_K_SFT |
  820. pll_code.n_code << RT5514_PLL_N_SFT |
  821. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
  822. regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
  823. RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
  824. rt5514->pll_in = freq_in;
  825. rt5514->pll_out = freq_out;
  826. rt5514->pll_src = source;
  827. return 0;
  828. }
  829. static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  830. unsigned int rx_mask, int slots, int slot_width)
  831. {
  832. struct snd_soc_component *component = dai->component;
  833. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  834. unsigned int val = 0, val2 = 0;
  835. if (rx_mask || tx_mask)
  836. val |= RT5514_TDM_MODE;
  837. switch (tx_mask) {
  838. case 0x3:
  839. val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
  840. RT5514_TDM_DOCKING_START_SLOT0;
  841. break;
  842. case 0x30:
  843. val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
  844. RT5514_TDM_DOCKING_START_SLOT4;
  845. break;
  846. case 0xf:
  847. val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
  848. RT5514_TDM_DOCKING_START_SLOT0;
  849. break;
  850. case 0xf0:
  851. val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
  852. RT5514_TDM_DOCKING_START_SLOT4;
  853. break;
  854. default:
  855. break;
  856. }
  857. switch (slots) {
  858. case 4:
  859. val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
  860. break;
  861. case 6:
  862. val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
  863. break;
  864. case 8:
  865. val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
  866. break;
  867. case 2:
  868. default:
  869. break;
  870. }
  871. switch (slot_width) {
  872. case 20:
  873. val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
  874. break;
  875. case 24:
  876. val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
  877. break;
  878. case 25:
  879. val |= RT5514_TDM_MODE2;
  880. break;
  881. case 32:
  882. val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
  883. break;
  884. case 16:
  885. default:
  886. break;
  887. }
  888. regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
  889. RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
  890. RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
  891. RT5514_TDM_MODE2, val);
  892. regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
  893. RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
  894. RT5514_TDM_DOCKING_START_MASK, val2);
  895. return 0;
  896. }
  897. static int rt5514_set_bias_level(struct snd_soc_component *component,
  898. enum snd_soc_bias_level level)
  899. {
  900. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  901. int ret;
  902. switch (level) {
  903. case SND_SOC_BIAS_PREPARE:
  904. if (IS_ERR(rt5514->mclk))
  905. break;
  906. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
  907. clk_disable_unprepare(rt5514->mclk);
  908. } else {
  909. ret = clk_prepare_enable(rt5514->mclk);
  910. if (ret)
  911. return ret;
  912. }
  913. break;
  914. case SND_SOC_BIAS_STANDBY:
  915. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  916. /*
  917. * If the DSP is enabled in start of recording, the DSP
  918. * should be disabled, and sync back to normal recording
  919. * settings to make sure recording properly.
  920. */
  921. if (rt5514->dsp_enabled) {
  922. rt5514->dsp_enabled = 0;
  923. regmap_multi_reg_write(rt5514->i2c_regmap,
  924. rt5514_i2c_patch,
  925. ARRAY_SIZE(rt5514_i2c_patch));
  926. regcache_mark_dirty(rt5514->regmap);
  927. regcache_sync(rt5514->regmap);
  928. }
  929. }
  930. break;
  931. default:
  932. break;
  933. }
  934. return 0;
  935. }
  936. static int rt5514_probe(struct snd_soc_component *component)
  937. {
  938. struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
  939. struct platform_device *pdev = container_of(component->dev,
  940. struct platform_device, dev);
  941. rt5514->mclk = devm_clk_get(component->dev, "mclk");
  942. if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
  943. return -EPROBE_DEFER;
  944. if (rt5514->pdata.dsp_calib_clk_name) {
  945. rt5514->dsp_calib_clk = devm_clk_get(&pdev->dev,
  946. rt5514->pdata.dsp_calib_clk_name);
  947. if (PTR_ERR(rt5514->dsp_calib_clk) == -EPROBE_DEFER)
  948. return -EPROBE_DEFER;
  949. }
  950. rt5514->component = component;
  951. rt5514->pll3_cal_value = 0x0078b000;
  952. return 0;
  953. }
  954. static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
  955. {
  956. struct i2c_client *client = context;
  957. struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
  958. regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
  959. return 0;
  960. }
  961. static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
  962. {
  963. struct i2c_client *client = context;
  964. struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
  965. regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
  966. return 0;
  967. }
  968. #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
  969. #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  970. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  971. static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
  972. .hw_params = rt5514_hw_params,
  973. .set_fmt = rt5514_set_dai_fmt,
  974. .set_sysclk = rt5514_set_dai_sysclk,
  975. .set_pll = rt5514_set_dai_pll,
  976. .set_tdm_slot = rt5514_set_tdm_slot,
  977. };
  978. static struct snd_soc_dai_driver rt5514_dai[] = {
  979. {
  980. .name = "rt5514-aif1",
  981. .id = 0,
  982. .capture = {
  983. .stream_name = "AIF1 Capture",
  984. .channels_min = 1,
  985. .channels_max = 4,
  986. .rates = RT5514_STEREO_RATES,
  987. .formats = RT5514_FORMATS,
  988. },
  989. .ops = &rt5514_aif_dai_ops,
  990. }
  991. };
  992. static const struct snd_soc_component_driver soc_component_dev_rt5514 = {
  993. .probe = rt5514_probe,
  994. .set_bias_level = rt5514_set_bias_level,
  995. .controls = rt5514_snd_controls,
  996. .num_controls = ARRAY_SIZE(rt5514_snd_controls),
  997. .dapm_widgets = rt5514_dapm_widgets,
  998. .num_dapm_widgets = ARRAY_SIZE(rt5514_dapm_widgets),
  999. .dapm_routes = rt5514_dapm_routes,
  1000. .num_dapm_routes = ARRAY_SIZE(rt5514_dapm_routes),
  1001. .use_pmdown_time = 1,
  1002. .endianness = 1,
  1003. };
  1004. static const struct regmap_config rt5514_i2c_regmap = {
  1005. .name = "i2c",
  1006. .reg_bits = 32,
  1007. .val_bits = 32,
  1008. .readable_reg = rt5514_i2c_readable_register,
  1009. .cache_type = REGCACHE_NONE,
  1010. };
  1011. static const struct regmap_config rt5514_regmap = {
  1012. .reg_bits = 16,
  1013. .val_bits = 32,
  1014. .max_register = RT5514_VENDOR_ID2,
  1015. .volatile_reg = rt5514_volatile_register,
  1016. .readable_reg = rt5514_readable_register,
  1017. .reg_read = rt5514_i2c_read,
  1018. .reg_write = rt5514_i2c_write,
  1019. .cache_type = REGCACHE_RBTREE,
  1020. .reg_defaults = rt5514_reg,
  1021. .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
  1022. .use_single_read = true,
  1023. .use_single_write = true,
  1024. };
  1025. static const struct i2c_device_id rt5514_i2c_id[] = {
  1026. { "rt5514", 0 },
  1027. { }
  1028. };
  1029. MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
  1030. #if defined(CONFIG_OF)
  1031. static const struct of_device_id rt5514_of_match[] = {
  1032. { .compatible = "realtek,rt5514", },
  1033. {},
  1034. };
  1035. MODULE_DEVICE_TABLE(of, rt5514_of_match);
  1036. #endif
  1037. #ifdef CONFIG_ACPI
  1038. static const struct acpi_device_id rt5514_acpi_match[] = {
  1039. { "10EC5514", 0},
  1040. {},
  1041. };
  1042. MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
  1043. #endif
  1044. static int rt5514_parse_dp(struct rt5514_priv *rt5514, struct device *dev)
  1045. {
  1046. device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
  1047. &rt5514->pdata.dmic_init_delay);
  1048. device_property_read_string(dev, "realtek,dsp-calib-clk-name",
  1049. &rt5514->pdata.dsp_calib_clk_name);
  1050. device_property_read_u32(dev, "realtek,dsp-calib-clk-rate",
  1051. &rt5514->pdata.dsp_calib_clk_rate);
  1052. return 0;
  1053. }
  1054. static __maybe_unused int rt5514_i2c_resume(struct device *dev)
  1055. {
  1056. struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
  1057. unsigned int val;
  1058. /*
  1059. * Add a bogus read to avoid rt5514's confusion after s2r in case it
  1060. * saw glitches on the i2c lines and thought the other side sent a
  1061. * start bit.
  1062. */
  1063. regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
  1064. return 0;
  1065. }
  1066. static int rt5514_i2c_probe(struct i2c_client *i2c)
  1067. {
  1068. struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1069. struct rt5514_priv *rt5514;
  1070. int ret;
  1071. unsigned int val = ~0;
  1072. rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
  1073. GFP_KERNEL);
  1074. if (rt5514 == NULL)
  1075. return -ENOMEM;
  1076. i2c_set_clientdata(i2c, rt5514);
  1077. if (pdata)
  1078. rt5514->pdata = *pdata;
  1079. else
  1080. rt5514_parse_dp(rt5514, &i2c->dev);
  1081. rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
  1082. if (IS_ERR(rt5514->i2c_regmap)) {
  1083. ret = PTR_ERR(rt5514->i2c_regmap);
  1084. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1085. ret);
  1086. return ret;
  1087. }
  1088. rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
  1089. if (IS_ERR(rt5514->regmap)) {
  1090. ret = PTR_ERR(rt5514->regmap);
  1091. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1092. ret);
  1093. return ret;
  1094. }
  1095. /*
  1096. * The rt5514 can get confused if the i2c lines glitch together, as
  1097. * can happen at bootup as regulators are turned off and on. If it's
  1098. * in this glitched state the first i2c read will fail, so we'll give
  1099. * it one change to retry.
  1100. */
  1101. ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
  1102. if (ret || val != RT5514_DEVICE_ID)
  1103. ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
  1104. if (ret || val != RT5514_DEVICE_ID) {
  1105. dev_err(&i2c->dev,
  1106. "Device with ID register %x is not rt5514\n", val);
  1107. return -ENODEV;
  1108. }
  1109. ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
  1110. ARRAY_SIZE(rt5514_i2c_patch));
  1111. if (ret != 0)
  1112. dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
  1113. ret);
  1114. ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
  1115. ARRAY_SIZE(rt5514_patch));
  1116. if (ret != 0)
  1117. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  1118. return devm_snd_soc_register_component(&i2c->dev,
  1119. &soc_component_dev_rt5514,
  1120. rt5514_dai, ARRAY_SIZE(rt5514_dai));
  1121. }
  1122. static const struct dev_pm_ops rt5514_i2_pm_ops = {
  1123. SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
  1124. };
  1125. static struct i2c_driver rt5514_i2c_driver = {
  1126. .driver = {
  1127. .name = "rt5514",
  1128. .acpi_match_table = ACPI_PTR(rt5514_acpi_match),
  1129. .of_match_table = of_match_ptr(rt5514_of_match),
  1130. .pm = &rt5514_i2_pm_ops,
  1131. },
  1132. .probe_new = rt5514_i2c_probe,
  1133. .id_table = rt5514_i2c_id,
  1134. };
  1135. module_i2c_driver(rt5514_i2c_driver);
  1136. MODULE_DESCRIPTION("ASoC RT5514 driver");
  1137. MODULE_AUTHOR("Oder Chiou <[email protected]>");
  1138. MODULE_LICENSE("GPL v2");