rt298.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt298.c -- RT298 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2015 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <[email protected]>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/dmi.h>
  17. #include <linux/acpi.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <sound/jack.h>
  26. #include <linux/workqueue.h>
  27. #include <sound/rt298.h>
  28. #include "rl6347a.h"
  29. #include "rt298.h"
  30. #define RT298_VENDOR_ID 0x10ec0298
  31. struct rt298_priv {
  32. struct reg_default *index_cache;
  33. int index_cache_size;
  34. struct regmap *regmap;
  35. struct snd_soc_component *component;
  36. struct rt298_platform_data pdata;
  37. struct i2c_client *i2c;
  38. struct snd_soc_jack *jack;
  39. struct delayed_work jack_detect_work;
  40. int sys_clk;
  41. int clk_id;
  42. int is_hp_in;
  43. };
  44. static const struct reg_default rt298_index_def[] = {
  45. { 0x01, 0xa5a8 },
  46. { 0x02, 0x8e95 },
  47. { 0x03, 0x0002 },
  48. { 0x04, 0xaf67 },
  49. { 0x08, 0x200f },
  50. { 0x09, 0xd010 },
  51. { 0x0a, 0x0100 },
  52. { 0x0b, 0x0000 },
  53. { 0x0d, 0x2800 },
  54. { 0x0f, 0x0022 },
  55. { 0x19, 0x0217 },
  56. { 0x20, 0x0020 },
  57. { 0x33, 0x0208 },
  58. { 0x46, 0x0300 },
  59. { 0x49, 0x4004 },
  60. { 0x4f, 0x50c9 },
  61. { 0x50, 0x3000 },
  62. { 0x63, 0x1b02 },
  63. { 0x67, 0x1111 },
  64. { 0x68, 0x1016 },
  65. { 0x69, 0x273f },
  66. };
  67. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def)
  68. static const struct reg_default rt298_reg[] = {
  69. { 0x00170500, 0x00000400 },
  70. { 0x00220000, 0x00000031 },
  71. { 0x00239000, 0x0000007f },
  72. { 0x0023a000, 0x0000007f },
  73. { 0x00270500, 0x00000400 },
  74. { 0x00370500, 0x00000400 },
  75. { 0x00870500, 0x00000400 },
  76. { 0x00920000, 0x00000031 },
  77. { 0x00935000, 0x000000c3 },
  78. { 0x00936000, 0x000000c3 },
  79. { 0x00970500, 0x00000400 },
  80. { 0x00b37000, 0x00000097 },
  81. { 0x00b37200, 0x00000097 },
  82. { 0x00b37300, 0x00000097 },
  83. { 0x00c37000, 0x00000000 },
  84. { 0x00c37100, 0x00000080 },
  85. { 0x01270500, 0x00000400 },
  86. { 0x01370500, 0x00000400 },
  87. { 0x01371f00, 0x411111f0 },
  88. { 0x01439000, 0x00000080 },
  89. { 0x0143a000, 0x00000080 },
  90. { 0x01470700, 0x00000000 },
  91. { 0x01470500, 0x00000400 },
  92. { 0x01470c00, 0x00000000 },
  93. { 0x01470100, 0x00000000 },
  94. { 0x01837000, 0x00000000 },
  95. { 0x01870500, 0x00000400 },
  96. { 0x02050000, 0x00000000 },
  97. { 0x02139000, 0x00000080 },
  98. { 0x0213a000, 0x00000080 },
  99. { 0x02170100, 0x00000000 },
  100. { 0x02170500, 0x00000400 },
  101. { 0x02170700, 0x00000000 },
  102. { 0x02270100, 0x00000000 },
  103. { 0x02370100, 0x00000000 },
  104. { 0x01870700, 0x00000020 },
  105. { 0x00830000, 0x000000c3 },
  106. { 0x00930000, 0x000000c3 },
  107. { 0x01270700, 0x00000000 },
  108. };
  109. static bool rt298_volatile_register(struct device *dev, unsigned int reg)
  110. {
  111. switch (reg) {
  112. case 0 ... 0xff:
  113. case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  114. case RT298_GET_HP_SENSE:
  115. case RT298_GET_MIC1_SENSE:
  116. case RT298_PROC_COEF:
  117. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
  118. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
  119. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
  120. return true;
  121. default:
  122. return false;
  123. }
  124. }
  125. static bool rt298_readable_register(struct device *dev, unsigned int reg)
  126. {
  127. switch (reg) {
  128. case 0 ... 0xff:
  129. case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  130. case RT298_GET_HP_SENSE:
  131. case RT298_GET_MIC1_SENSE:
  132. case RT298_SET_AUDIO_POWER:
  133. case RT298_SET_HPO_POWER:
  134. case RT298_SET_SPK_POWER:
  135. case RT298_SET_DMIC1_POWER:
  136. case RT298_SPK_MUX:
  137. case RT298_HPO_MUX:
  138. case RT298_ADC0_MUX:
  139. case RT298_ADC1_MUX:
  140. case RT298_SET_MIC1:
  141. case RT298_SET_PIN_HPO:
  142. case RT298_SET_PIN_SPK:
  143. case RT298_SET_PIN_DMIC1:
  144. case RT298_SPK_EAPD:
  145. case RT298_SET_AMP_GAIN_HPO:
  146. case RT298_SET_DMIC2_DEFAULT:
  147. case RT298_DACL_GAIN:
  148. case RT298_DACR_GAIN:
  149. case RT298_ADCL_GAIN:
  150. case RT298_ADCR_GAIN:
  151. case RT298_MIC_GAIN:
  152. case RT298_SPOL_GAIN:
  153. case RT298_SPOR_GAIN:
  154. case RT298_HPOL_GAIN:
  155. case RT298_HPOR_GAIN:
  156. case RT298_F_DAC_SWITCH:
  157. case RT298_F_RECMIX_SWITCH:
  158. case RT298_REC_MIC_SWITCH:
  159. case RT298_REC_I2S_SWITCH:
  160. case RT298_REC_LINE_SWITCH:
  161. case RT298_REC_BEEP_SWITCH:
  162. case RT298_DAC_FORMAT:
  163. case RT298_ADC_FORMAT:
  164. case RT298_COEF_INDEX:
  165. case RT298_PROC_COEF:
  166. case RT298_SET_AMP_GAIN_ADC_IN1:
  167. case RT298_SET_AMP_GAIN_ADC_IN2:
  168. case RT298_SET_POWER(RT298_DAC_OUT1):
  169. case RT298_SET_POWER(RT298_DAC_OUT2):
  170. case RT298_SET_POWER(RT298_ADC_IN1):
  171. case RT298_SET_POWER(RT298_ADC_IN2):
  172. case RT298_SET_POWER(RT298_DMIC2):
  173. case RT298_SET_POWER(RT298_MIC1):
  174. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
  175. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
  176. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
  177. return true;
  178. default:
  179. return false;
  180. }
  181. }
  182. #ifdef CONFIG_PM
  183. static void rt298_index_sync(struct snd_soc_component *component)
  184. {
  185. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  186. int i;
  187. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  188. snd_soc_component_write(component, rt298->index_cache[i].reg,
  189. rt298->index_cache[i].def);
  190. }
  191. }
  192. #endif
  193. static int rt298_support_power_controls[] = {
  194. RT298_DAC_OUT1,
  195. RT298_DAC_OUT2,
  196. RT298_ADC_IN1,
  197. RT298_ADC_IN2,
  198. RT298_MIC1,
  199. RT298_DMIC1,
  200. RT298_DMIC2,
  201. RT298_SPK_OUT,
  202. RT298_HP_OUT,
  203. };
  204. #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls)
  205. static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic)
  206. {
  207. struct snd_soc_dapm_context *dapm;
  208. unsigned int val, buf;
  209. *hp = false;
  210. *mic = false;
  211. if (!rt298->component)
  212. return -EINVAL;
  213. dapm = snd_soc_component_get_dapm(rt298->component);
  214. if (rt298->pdata.cbj_en) {
  215. regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
  216. *hp = buf & 0x80000000;
  217. if (*hp == rt298->is_hp_in)
  218. return -1;
  219. rt298->is_hp_in = *hp;
  220. if (*hp) {
  221. /* power on HV,VERF */
  222. regmap_update_bits(rt298->regmap,
  223. RT298_DC_GAIN, 0x200, 0x200);
  224. snd_soc_dapm_force_enable_pin(dapm, "HV");
  225. snd_soc_dapm_force_enable_pin(dapm, "VREF");
  226. /* power LDO1 */
  227. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  228. snd_soc_dapm_sync(dapm);
  229. regmap_update_bits(rt298->regmap,
  230. RT298_POWER_CTRL1, 0x1001, 0);
  231. regmap_update_bits(rt298->regmap,
  232. RT298_POWER_CTRL2, 0x4, 0x4);
  233. regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24);
  234. msleep(50);
  235. regmap_update_bits(rt298->regmap,
  236. RT298_CBJ_CTRL1, 0xfcc0, 0xd400);
  237. msleep(300);
  238. regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val);
  239. if (0x0070 == (val & 0x0070)) {
  240. *mic = true;
  241. } else {
  242. regmap_update_bits(rt298->regmap,
  243. RT298_CBJ_CTRL1, 0xfcc0, 0xe400);
  244. msleep(300);
  245. regmap_read(rt298->regmap,
  246. RT298_CBJ_CTRL2, &val);
  247. if (0x0070 == (val & 0x0070)) {
  248. *mic = true;
  249. } else {
  250. *mic = false;
  251. regmap_update_bits(rt298->regmap,
  252. RT298_CBJ_CTRL1,
  253. 0xfcc0, 0xc400);
  254. }
  255. }
  256. regmap_update_bits(rt298->regmap,
  257. RT298_DC_GAIN, 0x200, 0x0);
  258. } else {
  259. *mic = false;
  260. regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20);
  261. regmap_update_bits(rt298->regmap,
  262. RT298_CBJ_CTRL1, 0x0400, 0x0000);
  263. }
  264. } else {
  265. regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
  266. *hp = buf & 0x80000000;
  267. regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf);
  268. *mic = buf & 0x80000000;
  269. }
  270. if (!*mic) {
  271. snd_soc_dapm_disable_pin(dapm, "HV");
  272. snd_soc_dapm_disable_pin(dapm, "VREF");
  273. }
  274. if (!*hp)
  275. snd_soc_dapm_disable_pin(dapm, "LDO1");
  276. snd_soc_dapm_sync(dapm);
  277. pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
  278. return 0;
  279. }
  280. static void rt298_jack_detect_work(struct work_struct *work)
  281. {
  282. struct rt298_priv *rt298 =
  283. container_of(work, struct rt298_priv, jack_detect_work.work);
  284. int status = 0;
  285. bool hp = false;
  286. bool mic = false;
  287. if (rt298_jack_detect(rt298, &hp, &mic) < 0)
  288. return;
  289. if (hp)
  290. status |= SND_JACK_HEADPHONE;
  291. if (mic)
  292. status |= SND_JACK_MICROPHONE;
  293. snd_soc_jack_report(rt298->jack, status,
  294. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  295. }
  296. static int rt298_mic_detect(struct snd_soc_component *component,
  297. struct snd_soc_jack *jack, void *data)
  298. {
  299. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  300. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  301. rt298->jack = jack;
  302. if (jack) {
  303. /* Enable IRQ */
  304. if (rt298->jack->status & SND_JACK_HEADPHONE)
  305. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  306. if (rt298->jack->status & SND_JACK_MICROPHONE) {
  307. snd_soc_dapm_force_enable_pin(dapm, "HV");
  308. snd_soc_dapm_force_enable_pin(dapm, "VREF");
  309. }
  310. regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x2);
  311. /* Send an initial empty report */
  312. snd_soc_jack_report(rt298->jack, rt298->jack->status,
  313. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  314. } else {
  315. /* Disable IRQ */
  316. regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x0);
  317. snd_soc_dapm_disable_pin(dapm, "HV");
  318. snd_soc_dapm_disable_pin(dapm, "VREF");
  319. snd_soc_dapm_disable_pin(dapm, "LDO1");
  320. }
  321. snd_soc_dapm_sync(dapm);
  322. return 0;
  323. }
  324. static int is_mclk_mode(struct snd_soc_dapm_widget *source,
  325. struct snd_soc_dapm_widget *sink)
  326. {
  327. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  328. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  329. if (rt298->clk_id == RT298_SCLK_S_MCLK)
  330. return 1;
  331. else
  332. return 0;
  333. }
  334. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  335. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  336. static const struct snd_kcontrol_new rt298_snd_controls[] = {
  337. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN,
  338. RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  339. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN,
  340. RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  341. SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN,
  342. 0, 0x3, 0, mic_vol_tlv),
  343. SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN,
  344. RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1),
  345. };
  346. /* Digital Mixer */
  347. static const struct snd_kcontrol_new rt298_front_mix[] = {
  348. SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH,
  349. RT298_MUTE_SFT, 1, 1),
  350. SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH,
  351. RT298_MUTE_SFT, 1, 1),
  352. };
  353. /* Analog Input Mixer */
  354. static const struct snd_kcontrol_new rt298_rec_mix[] = {
  355. SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH,
  356. RT298_MUTE_SFT, 1, 1),
  357. SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH,
  358. RT298_MUTE_SFT, 1, 1),
  359. SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH,
  360. RT298_MUTE_SFT, 1, 1),
  361. SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH,
  362. RT298_MUTE_SFT, 1, 1),
  363. };
  364. static const struct snd_kcontrol_new spo_enable_control =
  365. SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK,
  366. RT298_SET_PIN_SFT, 1, 0);
  367. static const struct snd_kcontrol_new hpol_enable_control =
  368. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN,
  369. RT298_MUTE_SFT, 1, 1);
  370. static const struct snd_kcontrol_new hpor_enable_control =
  371. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN,
  372. RT298_MUTE_SFT, 1, 1);
  373. /* ADC0 source */
  374. static const char * const rt298_adc_src[] = {
  375. "Mic", "RECMIX", "Dmic"
  376. };
  377. static const int rt298_adc_values[] = {
  378. 0, 4, 5,
  379. };
  380. static SOC_VALUE_ENUM_SINGLE_DECL(
  381. rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT,
  382. RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
  383. static const struct snd_kcontrol_new rt298_adc0_mux =
  384. SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum);
  385. static SOC_VALUE_ENUM_SINGLE_DECL(
  386. rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT,
  387. RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
  388. static const struct snd_kcontrol_new rt298_adc1_mux =
  389. SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum);
  390. static const char * const rt298_dac_src[] = {
  391. "Front", "Surround"
  392. };
  393. /* HP-OUT source */
  394. static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX,
  395. 0, rt298_dac_src);
  396. static const struct snd_kcontrol_new rt298_hpo_mux =
  397. SOC_DAPM_ENUM("HPO source", rt298_hpo_enum);
  398. /* SPK-OUT source */
  399. static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX,
  400. 0, rt298_dac_src);
  401. static const struct snd_kcontrol_new rt298_spo_mux =
  402. SOC_DAPM_ENUM("SPO source", rt298_spo_enum);
  403. static int rt298_spk_event(struct snd_soc_dapm_widget *w,
  404. struct snd_kcontrol *kcontrol, int event)
  405. {
  406. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  407. switch (event) {
  408. case SND_SOC_DAPM_POST_PMU:
  409. snd_soc_component_write(component,
  410. RT298_SPK_EAPD, RT298_SET_EAPD_HIGH);
  411. break;
  412. case SND_SOC_DAPM_PRE_PMD:
  413. snd_soc_component_write(component,
  414. RT298_SPK_EAPD, RT298_SET_EAPD_LOW);
  415. break;
  416. default:
  417. return 0;
  418. }
  419. return 0;
  420. }
  421. static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w,
  422. struct snd_kcontrol *kcontrol, int event)
  423. {
  424. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  425. switch (event) {
  426. case SND_SOC_DAPM_POST_PMU:
  427. snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0x20);
  428. break;
  429. case SND_SOC_DAPM_PRE_PMD:
  430. snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0);
  431. break;
  432. default:
  433. return 0;
  434. }
  435. return 0;
  436. }
  437. static int rt298_adc_event(struct snd_soc_dapm_widget *w,
  438. struct snd_kcontrol *kcontrol, int event)
  439. {
  440. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  441. unsigned int nid;
  442. nid = (w->reg >> 20) & 0xff;
  443. switch (event) {
  444. case SND_SOC_DAPM_POST_PMU:
  445. snd_soc_component_update_bits(component,
  446. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  447. 0x7080, 0x7000);
  448. /* If MCLK doesn't exist, reset AD filter */
  449. if (!(snd_soc_component_read(component, RT298_VAD_CTRL) & 0x200)) {
  450. pr_info("NO MCLK\n");
  451. switch (nid) {
  452. case RT298_ADC_IN1:
  453. snd_soc_component_update_bits(component,
  454. RT298_D_FILTER_CTRL, 0x2, 0x2);
  455. mdelay(10);
  456. snd_soc_component_update_bits(component,
  457. RT298_D_FILTER_CTRL, 0x2, 0x0);
  458. break;
  459. case RT298_ADC_IN2:
  460. snd_soc_component_update_bits(component,
  461. RT298_D_FILTER_CTRL, 0x4, 0x4);
  462. mdelay(10);
  463. snd_soc_component_update_bits(component,
  464. RT298_D_FILTER_CTRL, 0x4, 0x0);
  465. break;
  466. }
  467. }
  468. break;
  469. case SND_SOC_DAPM_PRE_PMD:
  470. snd_soc_component_update_bits(component,
  471. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  472. 0x7080, 0x7080);
  473. break;
  474. default:
  475. return 0;
  476. }
  477. return 0;
  478. }
  479. static int rt298_mic1_event(struct snd_soc_dapm_widget *w,
  480. struct snd_kcontrol *kcontrol, int event)
  481. {
  482. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  483. switch (event) {
  484. case SND_SOC_DAPM_PRE_PMU:
  485. snd_soc_component_update_bits(component,
  486. RT298_A_BIAS_CTRL3, 0xc000, 0x8000);
  487. snd_soc_component_update_bits(component,
  488. RT298_A_BIAS_CTRL2, 0xc000, 0x8000);
  489. break;
  490. case SND_SOC_DAPM_POST_PMD:
  491. snd_soc_component_update_bits(component,
  492. RT298_A_BIAS_CTRL3, 0xc000, 0x0000);
  493. snd_soc_component_update_bits(component,
  494. RT298_A_BIAS_CTRL2, 0xc000, 0x0000);
  495. break;
  496. default:
  497. return 0;
  498. }
  499. return 0;
  500. }
  501. static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = {
  502. SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1,
  503. 12, 1, NULL, 0),
  504. SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1,
  505. 0, 1, NULL, 0),
  506. SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2,
  507. 1, 0, NULL, 0),
  508. SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2,
  509. 2, 0, NULL, 0),
  510. SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2,
  511. 3, 0, NULL, 0),
  512. SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2,
  513. 4, 1, NULL, 0),
  514. SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1,
  515. 13, 1, NULL, 0),
  516. SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1,
  517. 5, 0, NULL, 0),
  518. SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
  519. 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU |
  520. SND_SOC_DAPM_POST_PMD),
  521. /* Input Lines */
  522. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  523. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  524. SND_SOC_DAPM_INPUT("MIC1"),
  525. SND_SOC_DAPM_INPUT("LINE1"),
  526. SND_SOC_DAPM_INPUT("Beep"),
  527. /* DMIC */
  528. SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1,
  529. NULL, 0, rt298_set_dmic1_event,
  530. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  531. SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1,
  532. NULL, 0),
  533. SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
  534. 0, 0, NULL, 0),
  535. /* REC Mixer */
  536. SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
  537. rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)),
  538. /* ADCs */
  539. SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
  540. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  541. /* ADC Mux */
  542. SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1,
  543. &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
  544. SND_SOC_DAPM_POST_PMU),
  545. SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1,
  546. &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
  547. SND_SOC_DAPM_POST_PMU),
  548. /* Audio Interface */
  549. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  550. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  551. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  552. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  553. /* Output Side */
  554. /* DACs */
  555. SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
  556. SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
  557. /* Output Mux */
  558. SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux),
  559. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux),
  560. SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO,
  561. RT298_SET_PIN_SFT, 0, NULL, 0),
  562. /* Output Mixer */
  563. SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1,
  564. rt298_front_mix, ARRAY_SIZE(rt298_front_mix)),
  565. SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1,
  566. NULL, 0),
  567. /* Output Pga */
  568. SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
  569. &spo_enable_control, rt298_spk_event,
  570. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  571. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  572. &hpol_enable_control),
  573. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  574. &hpor_enable_control),
  575. /* Output Lines */
  576. SND_SOC_DAPM_OUTPUT("SPOL"),
  577. SND_SOC_DAPM_OUTPUT("SPOR"),
  578. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  579. SND_SOC_DAPM_OUTPUT("SPDIF"),
  580. };
  581. static const struct snd_soc_dapm_route rt298_dapm_routes[] = {
  582. {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
  583. {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
  584. {"Front", NULL, "MCLK MODE", is_mclk_mode},
  585. {"Surround", NULL, "MCLK MODE", is_mclk_mode},
  586. {"HP Power", NULL, "LDO1"},
  587. {"HP Power", NULL, "LDO2"},
  588. {"HP Power", NULL, "LV"},
  589. {"HP Power", NULL, "VREF1"},
  590. {"HP Power", NULL, "BG_MBIAS"},
  591. {"MIC1", NULL, "LDO1"},
  592. {"MIC1", NULL, "LDO2"},
  593. {"MIC1", NULL, "HV"},
  594. {"MIC1", NULL, "LV"},
  595. {"MIC1", NULL, "VREF"},
  596. {"MIC1", NULL, "VREF1"},
  597. {"MIC1", NULL, "BG_MBIAS"},
  598. {"MIC1", NULL, "MIC1 Input Buffer"},
  599. {"SPO", NULL, "LDO1"},
  600. {"SPO", NULL, "LDO2"},
  601. {"SPO", NULL, "HV"},
  602. {"SPO", NULL, "LV"},
  603. {"SPO", NULL, "VREF"},
  604. {"SPO", NULL, "VREF1"},
  605. {"SPO", NULL, "BG_MBIAS"},
  606. {"DMIC1", NULL, "DMIC1 Pin"},
  607. {"DMIC2", NULL, "DMIC2 Pin"},
  608. {"DMIC1", NULL, "DMIC Receiver"},
  609. {"DMIC2", NULL, "DMIC Receiver"},
  610. {"RECMIX", "Beep Switch", "Beep"},
  611. {"RECMIX", "Line1 Switch", "LINE1"},
  612. {"RECMIX", "Mic1 Switch", "MIC1"},
  613. {"ADC 0 Mux", "Dmic", "DMIC1"},
  614. {"ADC 0 Mux", "RECMIX", "RECMIX"},
  615. {"ADC 0 Mux", "Mic", "MIC1"},
  616. {"ADC 1 Mux", "Dmic", "DMIC2"},
  617. {"ADC 1 Mux", "RECMIX", "RECMIX"},
  618. {"ADC 1 Mux", "Mic", "MIC1"},
  619. {"ADC 0", NULL, "ADC 0 Mux"},
  620. {"ADC 1", NULL, "ADC 1 Mux"},
  621. {"AIF1TX", NULL, "ADC 0"},
  622. {"AIF2TX", NULL, "ADC 1"},
  623. {"DAC 0", NULL, "AIF1RX"},
  624. {"DAC 1", NULL, "AIF2RX"},
  625. {"Front", "DAC Switch", "DAC 0"},
  626. {"Front", "RECMIX Switch", "RECMIX"},
  627. {"Surround", NULL, "DAC 1"},
  628. {"SPK Mux", "Front", "Front"},
  629. {"SPK Mux", "Surround", "Surround"},
  630. {"HPO Mux", "Front", "Front"},
  631. {"HPO Mux", "Surround", "Surround"},
  632. {"SPO", "Switch", "SPK Mux"},
  633. {"HPO L", "Switch", "HPO Mux"},
  634. {"HPO R", "Switch", "HPO Mux"},
  635. {"HPO L", NULL, "HP Power"},
  636. {"HPO R", NULL, "HP Power"},
  637. {"SPOL", NULL, "SPO"},
  638. {"SPOR", NULL, "SPO"},
  639. {"HPO Pin", NULL, "HPO L"},
  640. {"HPO Pin", NULL, "HPO R"},
  641. };
  642. static int rt298_hw_params(struct snd_pcm_substream *substream,
  643. struct snd_pcm_hw_params *params,
  644. struct snd_soc_dai *dai)
  645. {
  646. struct snd_soc_component *component = dai->component;
  647. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  648. unsigned int val = 0;
  649. int d_len_code;
  650. switch (params_rate(params)) {
  651. /* bit 14 0:48K 1:44.1K */
  652. case 44100:
  653. case 48000:
  654. break;
  655. default:
  656. dev_err(component->dev, "Unsupported sample rate %d\n",
  657. params_rate(params));
  658. return -EINVAL;
  659. }
  660. switch (rt298->sys_clk) {
  661. case 12288000:
  662. case 24576000:
  663. if (params_rate(params) != 48000) {
  664. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  665. params_rate(params), rt298->sys_clk);
  666. return -EINVAL;
  667. }
  668. break;
  669. case 11289600:
  670. case 22579200:
  671. if (params_rate(params) != 44100) {
  672. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  673. params_rate(params), rt298->sys_clk);
  674. return -EINVAL;
  675. }
  676. break;
  677. }
  678. if (params_channels(params) <= 16) {
  679. /* bit 3:0 Number of Channel */
  680. val |= (params_channels(params) - 1);
  681. } else {
  682. dev_err(component->dev, "Unsupported channels %d\n",
  683. params_channels(params));
  684. return -EINVAL;
  685. }
  686. d_len_code = 0;
  687. switch (params_width(params)) {
  688. /* bit 6:4 Bits per Sample */
  689. case 16:
  690. d_len_code = 0;
  691. val |= (0x1 << 4);
  692. break;
  693. case 32:
  694. d_len_code = 2;
  695. val |= (0x4 << 4);
  696. break;
  697. case 20:
  698. d_len_code = 1;
  699. val |= (0x2 << 4);
  700. break;
  701. case 24:
  702. d_len_code = 2;
  703. val |= (0x3 << 4);
  704. break;
  705. case 8:
  706. d_len_code = 3;
  707. break;
  708. default:
  709. return -EINVAL;
  710. }
  711. snd_soc_component_update_bits(component,
  712. RT298_I2S_CTRL1, 0x0018, d_len_code << 3);
  713. dev_dbg(component->dev, "format val = 0x%x\n", val);
  714. snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val);
  715. snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val);
  716. return 0;
  717. }
  718. static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  719. {
  720. struct snd_soc_component *component = dai->component;
  721. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  722. case SND_SOC_DAIFMT_CBM_CFM:
  723. snd_soc_component_update_bits(component,
  724. RT298_I2S_CTRL1, 0x800, 0x800);
  725. break;
  726. case SND_SOC_DAIFMT_CBS_CFS:
  727. snd_soc_component_update_bits(component,
  728. RT298_I2S_CTRL1, 0x800, 0x0);
  729. break;
  730. default:
  731. return -EINVAL;
  732. }
  733. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  734. case SND_SOC_DAIFMT_I2S:
  735. snd_soc_component_update_bits(component,
  736. RT298_I2S_CTRL1, 0x300, 0x0);
  737. break;
  738. case SND_SOC_DAIFMT_LEFT_J:
  739. snd_soc_component_update_bits(component,
  740. RT298_I2S_CTRL1, 0x300, 0x1 << 8);
  741. break;
  742. case SND_SOC_DAIFMT_DSP_A:
  743. snd_soc_component_update_bits(component,
  744. RT298_I2S_CTRL1, 0x300, 0x2 << 8);
  745. break;
  746. case SND_SOC_DAIFMT_DSP_B:
  747. snd_soc_component_update_bits(component,
  748. RT298_I2S_CTRL1, 0x300, 0x3 << 8);
  749. break;
  750. default:
  751. return -EINVAL;
  752. }
  753. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  754. snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x8000, 0);
  755. snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x8000, 0);
  756. return 0;
  757. }
  758. static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
  759. int clk_id, unsigned int freq, int dir)
  760. {
  761. struct snd_soc_component *component = dai->component;
  762. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  763. dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
  764. if (RT298_SCLK_S_MCLK == clk_id) {
  765. snd_soc_component_update_bits(component,
  766. RT298_I2S_CTRL2, 0x0100, 0x0);
  767. snd_soc_component_update_bits(component,
  768. RT298_PLL_CTRL1, 0x20, 0x20);
  769. } else {
  770. snd_soc_component_update_bits(component,
  771. RT298_I2S_CTRL2, 0x0100, 0x0100);
  772. snd_soc_component_update_bits(component,
  773. RT298_PLL_CTRL1, 0x20, 0x0);
  774. }
  775. switch (freq) {
  776. case 19200000:
  777. if (RT298_SCLK_S_MCLK == clk_id) {
  778. dev_err(component->dev, "Should not use MCLK\n");
  779. return -EINVAL;
  780. }
  781. snd_soc_component_update_bits(component,
  782. RT298_I2S_CTRL2, 0x40, 0x40);
  783. break;
  784. case 24000000:
  785. if (RT298_SCLK_S_MCLK == clk_id) {
  786. dev_err(component->dev, "Should not use MCLK\n");
  787. return -EINVAL;
  788. }
  789. snd_soc_component_update_bits(component,
  790. RT298_I2S_CTRL2, 0x40, 0x0);
  791. break;
  792. case 12288000:
  793. case 11289600:
  794. snd_soc_component_update_bits(component,
  795. RT298_I2S_CTRL2, 0x8, 0x0);
  796. snd_soc_component_update_bits(component,
  797. RT298_CLK_DIV, 0xfc1e, 0x0004);
  798. break;
  799. case 24576000:
  800. case 22579200:
  801. snd_soc_component_update_bits(component,
  802. RT298_I2S_CTRL2, 0x8, 0x8);
  803. snd_soc_component_update_bits(component,
  804. RT298_CLK_DIV, 0xfc1e, 0x5406);
  805. break;
  806. default:
  807. dev_err(component->dev, "Unsupported system clock\n");
  808. return -EINVAL;
  809. }
  810. rt298->sys_clk = freq;
  811. rt298->clk_id = clk_id;
  812. return 0;
  813. }
  814. static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  815. {
  816. struct snd_soc_component *component = dai->component;
  817. dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
  818. if (50 == ratio)
  819. snd_soc_component_update_bits(component,
  820. RT298_I2S_CTRL1, 0x1000, 0x1000);
  821. else
  822. snd_soc_component_update_bits(component,
  823. RT298_I2S_CTRL1, 0x1000, 0x0);
  824. return 0;
  825. }
  826. static int rt298_set_bias_level(struct snd_soc_component *component,
  827. enum snd_soc_bias_level level)
  828. {
  829. switch (level) {
  830. case SND_SOC_BIAS_PREPARE:
  831. if (SND_SOC_BIAS_STANDBY ==
  832. snd_soc_component_get_bias_level(component)) {
  833. snd_soc_component_write(component,
  834. RT298_SET_AUDIO_POWER, AC_PWRST_D0);
  835. snd_soc_component_update_bits(component, 0x0d, 0x200, 0x200);
  836. snd_soc_component_update_bits(component, 0x52, 0x80, 0x0);
  837. mdelay(20);
  838. snd_soc_component_update_bits(component, 0x0d, 0x200, 0x0);
  839. snd_soc_component_update_bits(component, 0x52, 0x80, 0x80);
  840. }
  841. break;
  842. case SND_SOC_BIAS_STANDBY:
  843. snd_soc_component_write(component,
  844. RT298_SET_AUDIO_POWER, AC_PWRST_D3);
  845. break;
  846. default:
  847. break;
  848. }
  849. return 0;
  850. }
  851. static irqreturn_t rt298_irq(int irq, void *data)
  852. {
  853. struct rt298_priv *rt298 = data;
  854. bool hp = false;
  855. bool mic = false;
  856. int ret, status = 0;
  857. ret = rt298_jack_detect(rt298, &hp, &mic);
  858. /* Clear IRQ */
  859. regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1);
  860. if (ret == 0) {
  861. if (hp)
  862. status |= SND_JACK_HEADPHONE;
  863. if (mic)
  864. status |= SND_JACK_MICROPHONE;
  865. snd_soc_jack_report(rt298->jack, status,
  866. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  867. pm_wakeup_event(&rt298->i2c->dev, 300);
  868. }
  869. return IRQ_HANDLED;
  870. }
  871. static int rt298_probe(struct snd_soc_component *component)
  872. {
  873. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  874. rt298->component = component;
  875. INIT_DELAYED_WORK(&rt298->jack_detect_work, rt298_jack_detect_work);
  876. if (rt298->i2c->irq)
  877. schedule_delayed_work(&rt298->jack_detect_work,
  878. msecs_to_jiffies(1250));
  879. return 0;
  880. }
  881. static void rt298_remove(struct snd_soc_component *component)
  882. {
  883. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  884. cancel_delayed_work_sync(&rt298->jack_detect_work);
  885. rt298->component = NULL;
  886. }
  887. #ifdef CONFIG_PM
  888. static int rt298_suspend(struct snd_soc_component *component)
  889. {
  890. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  891. rt298->is_hp_in = -1;
  892. regcache_cache_only(rt298->regmap, true);
  893. regcache_mark_dirty(rt298->regmap);
  894. return 0;
  895. }
  896. static int rt298_resume(struct snd_soc_component *component)
  897. {
  898. struct rt298_priv *rt298 = snd_soc_component_get_drvdata(component);
  899. regcache_cache_only(rt298->regmap, false);
  900. rt298_index_sync(component);
  901. regcache_sync(rt298->regmap);
  902. return 0;
  903. }
  904. #else
  905. #define rt298_suspend NULL
  906. #define rt298_resume NULL
  907. #endif
  908. #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  909. #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  910. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  911. static const struct snd_soc_dai_ops rt298_aif_dai_ops = {
  912. .hw_params = rt298_hw_params,
  913. .set_fmt = rt298_set_dai_fmt,
  914. .set_sysclk = rt298_set_dai_sysclk,
  915. .set_bclk_ratio = rt298_set_bclk_ratio,
  916. };
  917. static struct snd_soc_dai_driver rt298_dai[] = {
  918. {
  919. .name = "rt298-aif1",
  920. .id = RT298_AIF1,
  921. .playback = {
  922. .stream_name = "AIF1 Playback",
  923. .channels_min = 1,
  924. .channels_max = 2,
  925. .rates = RT298_STEREO_RATES,
  926. .formats = RT298_FORMATS,
  927. },
  928. .capture = {
  929. .stream_name = "AIF1 Capture",
  930. .channels_min = 1,
  931. .channels_max = 2,
  932. .rates = RT298_STEREO_RATES,
  933. .formats = RT298_FORMATS,
  934. },
  935. .ops = &rt298_aif_dai_ops,
  936. .symmetric_rate = 1,
  937. },
  938. {
  939. .name = "rt298-aif2",
  940. .id = RT298_AIF2,
  941. .playback = {
  942. .stream_name = "AIF2 Playback",
  943. .channels_min = 1,
  944. .channels_max = 2,
  945. .rates = RT298_STEREO_RATES,
  946. .formats = RT298_FORMATS,
  947. },
  948. .capture = {
  949. .stream_name = "AIF2 Capture",
  950. .channels_min = 1,
  951. .channels_max = 2,
  952. .rates = RT298_STEREO_RATES,
  953. .formats = RT298_FORMATS,
  954. },
  955. .ops = &rt298_aif_dai_ops,
  956. .symmetric_rate = 1,
  957. },
  958. };
  959. static const struct snd_soc_component_driver soc_component_dev_rt298 = {
  960. .probe = rt298_probe,
  961. .remove = rt298_remove,
  962. .suspend = rt298_suspend,
  963. .resume = rt298_resume,
  964. .set_bias_level = rt298_set_bias_level,
  965. .set_jack = rt298_mic_detect,
  966. .controls = rt298_snd_controls,
  967. .num_controls = ARRAY_SIZE(rt298_snd_controls),
  968. .dapm_widgets = rt298_dapm_widgets,
  969. .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets),
  970. .dapm_routes = rt298_dapm_routes,
  971. .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes),
  972. .use_pmdown_time = 1,
  973. .endianness = 1,
  974. };
  975. static const struct regmap_config rt298_regmap = {
  976. .reg_bits = 32,
  977. .val_bits = 32,
  978. .max_register = 0x02370100,
  979. .volatile_reg = rt298_volatile_register,
  980. .readable_reg = rt298_readable_register,
  981. .reg_write = rl6347a_hw_write,
  982. .reg_read = rl6347a_hw_read,
  983. .cache_type = REGCACHE_RBTREE,
  984. .reg_defaults = rt298_reg,
  985. .num_reg_defaults = ARRAY_SIZE(rt298_reg),
  986. };
  987. static const struct i2c_device_id rt298_i2c_id[] = {
  988. {"rt298", 0},
  989. {}
  990. };
  991. MODULE_DEVICE_TABLE(i2c, rt298_i2c_id);
  992. #ifdef CONFIG_ACPI
  993. static const struct acpi_device_id rt298_acpi_match[] = {
  994. { "INT343A", 0 },
  995. {},
  996. };
  997. MODULE_DEVICE_TABLE(acpi, rt298_acpi_match);
  998. #endif
  999. static const struct dmi_system_id force_combo_jack_table[] = {
  1000. {
  1001. .ident = "Intel Broxton P",
  1002. .matches = {
  1003. DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
  1004. DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P")
  1005. }
  1006. },
  1007. {
  1008. .ident = "Intel Gemini Lake",
  1009. .matches = {
  1010. DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
  1011. DMI_MATCH(DMI_PRODUCT_NAME, "Geminilake")
  1012. }
  1013. },
  1014. {
  1015. .ident = "Intel Kabylake R RVP",
  1016. .matches = {
  1017. DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
  1018. DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
  1019. }
  1020. },
  1021. { }
  1022. };
  1023. static int rt298_i2c_probe(struct i2c_client *i2c)
  1024. {
  1025. struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1026. struct rt298_priv *rt298;
  1027. struct device *dev = &i2c->dev;
  1028. const struct acpi_device_id *acpiid;
  1029. int i, ret;
  1030. rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298),
  1031. GFP_KERNEL);
  1032. if (NULL == rt298)
  1033. return -ENOMEM;
  1034. rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap);
  1035. if (IS_ERR(rt298->regmap)) {
  1036. ret = PTR_ERR(rt298->regmap);
  1037. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1038. ret);
  1039. return ret;
  1040. }
  1041. regmap_read(rt298->regmap,
  1042. RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
  1043. if (ret != RT298_VENDOR_ID) {
  1044. dev_err(&i2c->dev,
  1045. "Device with ID register %#x is not rt298\n", ret);
  1046. return -ENODEV;
  1047. }
  1048. rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def,
  1049. sizeof(rt298_index_def), GFP_KERNEL);
  1050. if (!rt298->index_cache)
  1051. return -ENOMEM;
  1052. rt298->index_cache_size = INDEX_CACHE_SIZE;
  1053. rt298->i2c = i2c;
  1054. i2c_set_clientdata(i2c, rt298);
  1055. /* restore codec default */
  1056. for (i = 0; i < INDEX_CACHE_SIZE; i++)
  1057. regmap_write(rt298->regmap, rt298->index_cache[i].reg,
  1058. rt298->index_cache[i].def);
  1059. for (i = 0; i < ARRAY_SIZE(rt298_reg); i++)
  1060. regmap_write(rt298->regmap, rt298_reg[i].reg,
  1061. rt298_reg[i].def);
  1062. if (pdata)
  1063. rt298->pdata = *pdata;
  1064. /* enable jack combo mode on supported devices */
  1065. acpiid = acpi_match_device(dev->driver->acpi_match_table, dev);
  1066. if (acpiid && acpiid->driver_data) {
  1067. rt298->pdata = *(struct rt298_platform_data *)
  1068. acpiid->driver_data;
  1069. }
  1070. if (dmi_check_system(force_combo_jack_table)) {
  1071. rt298->pdata.cbj_en = true;
  1072. rt298->pdata.gpio2_en = false;
  1073. }
  1074. /* VREF Charging */
  1075. regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80);
  1076. regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860);
  1077. /* Vref2 */
  1078. regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20);
  1079. regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3);
  1080. for (i = 0; i < RT298_POWER_REG_LEN; i++)
  1081. regmap_write(rt298->regmap,
  1082. RT298_SET_POWER(rt298_support_power_controls[i]),
  1083. AC_PWRST_D1);
  1084. if (!rt298->pdata.cbj_en) {
  1085. regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000);
  1086. regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816);
  1087. regmap_update_bits(rt298->regmap,
  1088. RT298_CBJ_CTRL1, 0xf000, 0xb000);
  1089. } else {
  1090. regmap_update_bits(rt298->regmap,
  1091. RT298_CBJ_CTRL1, 0xf000, 0x5000);
  1092. }
  1093. mdelay(10);
  1094. if (!rt298->pdata.gpio2_en)
  1095. regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40);
  1096. else
  1097. regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0);
  1098. mdelay(10);
  1099. regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000);
  1100. regmap_update_bits(rt298->regmap,
  1101. RT298_WIND_FILTER_CTRL, 0x0082, 0x0082);
  1102. regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81);
  1103. regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82);
  1104. regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84);
  1105. regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2);
  1106. rt298->is_hp_in = -1;
  1107. if (rt298->i2c->irq) {
  1108. ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq,
  1109. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298);
  1110. if (ret != 0) {
  1111. dev_err(&i2c->dev,
  1112. "Failed to reguest IRQ: %d\n", ret);
  1113. return ret;
  1114. }
  1115. }
  1116. ret = devm_snd_soc_register_component(&i2c->dev,
  1117. &soc_component_dev_rt298,
  1118. rt298_dai, ARRAY_SIZE(rt298_dai));
  1119. return ret;
  1120. }
  1121. static void rt298_i2c_remove(struct i2c_client *i2c)
  1122. {
  1123. struct rt298_priv *rt298 = i2c_get_clientdata(i2c);
  1124. if (i2c->irq)
  1125. free_irq(i2c->irq, rt298);
  1126. }
  1127. static struct i2c_driver rt298_i2c_driver = {
  1128. .driver = {
  1129. .name = "rt298",
  1130. .acpi_match_table = ACPI_PTR(rt298_acpi_match),
  1131. },
  1132. .probe_new = rt298_i2c_probe,
  1133. .remove = rt298_i2c_remove,
  1134. .id_table = rt298_i2c_id,
  1135. };
  1136. module_i2c_driver(rt298_i2c_driver);
  1137. MODULE_DESCRIPTION("ASoC RT298 driver");
  1138. MODULE_AUTHOR("Bard Liao <[email protected]>");
  1139. MODULE_LICENSE("GPL");