rt286.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * rt286.c -- RT286 ALSA SoC audio codec driver
  4. *
  5. * Copyright 2013 Realtek Semiconductor Corp.
  6. * Author: Bard Liao <[email protected]>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/delay.h>
  12. #include <linux/pm.h>
  13. #include <linux/i2c.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/dmi.h>
  17. #include <linux/acpi.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <sound/jack.h>
  26. #include <linux/workqueue.h>
  27. #include <sound/rt286.h>
  28. #include "rl6347a.h"
  29. #include "rt286.h"
  30. #define RT286_VENDOR_ID 0x10ec0286
  31. #define RT288_VENDOR_ID 0x10ec0288
  32. struct rt286_priv {
  33. struct reg_default *index_cache;
  34. int index_cache_size;
  35. struct regmap *regmap;
  36. struct snd_soc_component *component;
  37. struct rt286_platform_data pdata;
  38. struct i2c_client *i2c;
  39. struct snd_soc_jack *jack;
  40. struct delayed_work jack_detect_work;
  41. int sys_clk;
  42. int clk_id;
  43. };
  44. static const struct reg_default rt286_index_def[] = {
  45. { 0x01, 0xaaaa },
  46. { 0x02, 0x8aaa },
  47. { 0x03, 0x0002 },
  48. { 0x04, 0xaf01 },
  49. { 0x08, 0x000d },
  50. { 0x09, 0xd810 },
  51. { 0x0a, 0x0120 },
  52. { 0x0b, 0x0000 },
  53. { 0x0d, 0x2800 },
  54. { 0x0f, 0x0000 },
  55. { 0x19, 0x0a17 },
  56. { 0x20, 0x0020 },
  57. { 0x33, 0x0208 },
  58. { 0x49, 0x0004 },
  59. { 0x4f, 0x50e9 },
  60. { 0x50, 0x2000 },
  61. { 0x63, 0x2902 },
  62. { 0x67, 0x1111 },
  63. { 0x68, 0x1016 },
  64. { 0x69, 0x273f },
  65. };
  66. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  67. static const struct reg_default rt286_reg[] = {
  68. { 0x00170500, 0x00000400 },
  69. { 0x00220000, 0x00000031 },
  70. { 0x00239000, 0x0000007f },
  71. { 0x0023a000, 0x0000007f },
  72. { 0x00270500, 0x00000400 },
  73. { 0x00370500, 0x00000400 },
  74. { 0x00870500, 0x00000400 },
  75. { 0x00920000, 0x00000031 },
  76. { 0x00935000, 0x000000c3 },
  77. { 0x00936000, 0x000000c3 },
  78. { 0x00970500, 0x00000400 },
  79. { 0x00b37000, 0x00000097 },
  80. { 0x00b37200, 0x00000097 },
  81. { 0x00b37300, 0x00000097 },
  82. { 0x00c37000, 0x00000000 },
  83. { 0x00c37100, 0x00000080 },
  84. { 0x01270500, 0x00000400 },
  85. { 0x01370500, 0x00000400 },
  86. { 0x01371f00, 0x411111f0 },
  87. { 0x01439000, 0x00000080 },
  88. { 0x0143a000, 0x00000080 },
  89. { 0x01470700, 0x00000000 },
  90. { 0x01470500, 0x00000400 },
  91. { 0x01470c00, 0x00000000 },
  92. { 0x01470100, 0x00000000 },
  93. { 0x01837000, 0x00000000 },
  94. { 0x01870500, 0x00000400 },
  95. { 0x02050000, 0x00000000 },
  96. { 0x02139000, 0x00000080 },
  97. { 0x0213a000, 0x00000080 },
  98. { 0x02170100, 0x00000000 },
  99. { 0x02170500, 0x00000400 },
  100. { 0x02170700, 0x00000000 },
  101. { 0x02270100, 0x00000000 },
  102. { 0x02370100, 0x00000000 },
  103. { 0x01870700, 0x00000020 },
  104. { 0x00830000, 0x000000c3 },
  105. { 0x00930000, 0x000000c3 },
  106. { 0x01270700, 0x00000000 },
  107. };
  108. static bool rt286_volatile_register(struct device *dev, unsigned int reg)
  109. {
  110. switch (reg) {
  111. case 0 ... 0xff:
  112. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  113. case RT286_GET_HP_SENSE:
  114. case RT286_GET_MIC1_SENSE:
  115. case RT286_PROC_COEF:
  116. return true;
  117. default:
  118. return false;
  119. }
  120. }
  121. static bool rt286_readable_register(struct device *dev, unsigned int reg)
  122. {
  123. switch (reg) {
  124. case 0 ... 0xff:
  125. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  126. case RT286_GET_HP_SENSE:
  127. case RT286_GET_MIC1_SENSE:
  128. case RT286_SET_AUDIO_POWER:
  129. case RT286_SET_HPO_POWER:
  130. case RT286_SET_SPK_POWER:
  131. case RT286_SET_DMIC1_POWER:
  132. case RT286_SPK_MUX:
  133. case RT286_HPO_MUX:
  134. case RT286_ADC0_MUX:
  135. case RT286_ADC1_MUX:
  136. case RT286_SET_MIC1:
  137. case RT286_SET_PIN_HPO:
  138. case RT286_SET_PIN_SPK:
  139. case RT286_SET_PIN_DMIC1:
  140. case RT286_SPK_EAPD:
  141. case RT286_SET_AMP_GAIN_HPO:
  142. case RT286_SET_DMIC2_DEFAULT:
  143. case RT286_DACL_GAIN:
  144. case RT286_DACR_GAIN:
  145. case RT286_ADCL_GAIN:
  146. case RT286_ADCR_GAIN:
  147. case RT286_MIC_GAIN:
  148. case RT286_SPOL_GAIN:
  149. case RT286_SPOR_GAIN:
  150. case RT286_HPOL_GAIN:
  151. case RT286_HPOR_GAIN:
  152. case RT286_F_DAC_SWITCH:
  153. case RT286_F_RECMIX_SWITCH:
  154. case RT286_REC_MIC_SWITCH:
  155. case RT286_REC_I2S_SWITCH:
  156. case RT286_REC_LINE_SWITCH:
  157. case RT286_REC_BEEP_SWITCH:
  158. case RT286_DAC_FORMAT:
  159. case RT286_ADC_FORMAT:
  160. case RT286_COEF_INDEX:
  161. case RT286_PROC_COEF:
  162. case RT286_SET_AMP_GAIN_ADC_IN1:
  163. case RT286_SET_AMP_GAIN_ADC_IN2:
  164. case RT286_SET_GPIO_MASK:
  165. case RT286_SET_GPIO_DIRECTION:
  166. case RT286_SET_GPIO_DATA:
  167. case RT286_SET_POWER(RT286_DAC_OUT1):
  168. case RT286_SET_POWER(RT286_DAC_OUT2):
  169. case RT286_SET_POWER(RT286_ADC_IN1):
  170. case RT286_SET_POWER(RT286_ADC_IN2):
  171. case RT286_SET_POWER(RT286_DMIC2):
  172. case RT286_SET_POWER(RT286_MIC1):
  173. return true;
  174. default:
  175. return false;
  176. }
  177. }
  178. #ifdef CONFIG_PM
  179. static void rt286_index_sync(struct snd_soc_component *component)
  180. {
  181. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  182. int i;
  183. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  184. snd_soc_component_write(component, rt286->index_cache[i].reg,
  185. rt286->index_cache[i].def);
  186. }
  187. }
  188. #endif
  189. static int rt286_support_power_controls[] = {
  190. RT286_DAC_OUT1,
  191. RT286_DAC_OUT2,
  192. RT286_ADC_IN1,
  193. RT286_ADC_IN2,
  194. RT286_MIC1,
  195. RT286_DMIC1,
  196. RT286_DMIC2,
  197. RT286_SPK_OUT,
  198. RT286_HP_OUT,
  199. };
  200. #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
  201. static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
  202. {
  203. struct snd_soc_dapm_context *dapm;
  204. unsigned int val, buf;
  205. *hp = false;
  206. *mic = false;
  207. if (!rt286->component)
  208. return -EINVAL;
  209. dapm = snd_soc_component_get_dapm(rt286->component);
  210. if (rt286->pdata.cbj_en) {
  211. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  212. *hp = buf & 0x80000000;
  213. if (*hp) {
  214. /* power on HV,VERF */
  215. regmap_update_bits(rt286->regmap,
  216. RT286_DC_GAIN, 0x200, 0x200);
  217. snd_soc_dapm_force_enable_pin(dapm, "HV");
  218. snd_soc_dapm_force_enable_pin(dapm, "VREF");
  219. /* power LDO1 */
  220. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  221. snd_soc_dapm_sync(dapm);
  222. regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
  223. msleep(50);
  224. regmap_update_bits(rt286->regmap,
  225. RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
  226. msleep(300);
  227. regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
  228. if (0x0070 == (val & 0x0070)) {
  229. *mic = true;
  230. } else {
  231. regmap_update_bits(rt286->regmap,
  232. RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
  233. msleep(300);
  234. regmap_read(rt286->regmap,
  235. RT286_CBJ_CTRL2, &val);
  236. if (0x0070 == (val & 0x0070)) {
  237. *mic = true;
  238. } else {
  239. *mic = false;
  240. regmap_update_bits(rt286->regmap,
  241. RT286_CBJ_CTRL1,
  242. 0xfcc0, 0xc400);
  243. }
  244. }
  245. regmap_update_bits(rt286->regmap,
  246. RT286_DC_GAIN, 0x200, 0x0);
  247. } else {
  248. *mic = false;
  249. regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
  250. regmap_update_bits(rt286->regmap,
  251. RT286_CBJ_CTRL1, 0x0400, 0x0000);
  252. }
  253. } else {
  254. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  255. *hp = buf & 0x80000000;
  256. regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
  257. *mic = buf & 0x80000000;
  258. }
  259. if (!*hp) {
  260. snd_soc_dapm_disable_pin(dapm, "HV");
  261. snd_soc_dapm_disable_pin(dapm, "VREF");
  262. snd_soc_dapm_disable_pin(dapm, "LDO1");
  263. snd_soc_dapm_sync(dapm);
  264. }
  265. return 0;
  266. }
  267. static void rt286_jack_detect_work(struct work_struct *work)
  268. {
  269. struct rt286_priv *rt286 =
  270. container_of(work, struct rt286_priv, jack_detect_work.work);
  271. int status = 0;
  272. bool hp = false;
  273. bool mic = false;
  274. rt286_jack_detect(rt286, &hp, &mic);
  275. if (hp)
  276. status |= SND_JACK_HEADPHONE;
  277. if (mic)
  278. status |= SND_JACK_MICROPHONE;
  279. snd_soc_jack_report(rt286->jack, status,
  280. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  281. }
  282. static int rt286_mic_detect(struct snd_soc_component *component,
  283. struct snd_soc_jack *jack, void *data)
  284. {
  285. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  286. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  287. rt286->jack = jack;
  288. if (jack) {
  289. /* enable IRQ */
  290. if (rt286->jack->status & SND_JACK_HEADPHONE)
  291. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  292. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
  293. /* Send an initial empty report */
  294. snd_soc_jack_report(rt286->jack, rt286->jack->status,
  295. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  296. } else {
  297. /* disable IRQ */
  298. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
  299. snd_soc_dapm_disable_pin(dapm, "LDO1");
  300. }
  301. snd_soc_dapm_sync(dapm);
  302. return 0;
  303. }
  304. static int is_mclk_mode(struct snd_soc_dapm_widget *source,
  305. struct snd_soc_dapm_widget *sink)
  306. {
  307. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  308. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  309. if (rt286->clk_id == RT286_SCLK_S_MCLK)
  310. return 1;
  311. else
  312. return 0;
  313. }
  314. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  315. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  316. static const struct snd_kcontrol_new rt286_snd_controls[] = {
  317. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
  318. RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  319. SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
  320. RT286_ADCR_GAIN, 7, 1, 1),
  321. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
  322. RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  323. SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
  324. 0, 0x3, 0, mic_vol_tlv),
  325. SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
  326. RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
  327. };
  328. /* Digital Mixer */
  329. static const struct snd_kcontrol_new rt286_front_mix[] = {
  330. SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
  331. RT286_MUTE_SFT, 1, 1),
  332. SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
  333. RT286_MUTE_SFT, 1, 1),
  334. };
  335. /* Analog Input Mixer */
  336. static const struct snd_kcontrol_new rt286_rec_mix[] = {
  337. SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
  338. RT286_MUTE_SFT, 1, 1),
  339. SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
  340. RT286_MUTE_SFT, 1, 1),
  341. SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
  342. RT286_MUTE_SFT, 1, 1),
  343. SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
  344. RT286_MUTE_SFT, 1, 1),
  345. };
  346. static const struct snd_kcontrol_new spo_enable_control =
  347. SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
  348. RT286_SET_PIN_SFT, 1, 0);
  349. static const struct snd_kcontrol_new hpol_enable_control =
  350. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
  351. RT286_MUTE_SFT, 1, 1);
  352. static const struct snd_kcontrol_new hpor_enable_control =
  353. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
  354. RT286_MUTE_SFT, 1, 1);
  355. /* ADC0 source */
  356. static const char * const rt286_adc_src[] = {
  357. "Mic", "RECMIX", "Dmic"
  358. };
  359. static const int rt286_adc_values[] = {
  360. 0, 4, 5,
  361. };
  362. static SOC_VALUE_ENUM_SINGLE_DECL(
  363. rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
  364. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  365. static const struct snd_kcontrol_new rt286_adc0_mux =
  366. SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
  367. static SOC_VALUE_ENUM_SINGLE_DECL(
  368. rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
  369. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  370. static const struct snd_kcontrol_new rt286_adc1_mux =
  371. SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
  372. static const char * const rt286_dac_src[] = {
  373. "Front", "Surround"
  374. };
  375. /* HP-OUT source */
  376. static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
  377. 0, rt286_dac_src);
  378. static const struct snd_kcontrol_new rt286_hpo_mux =
  379. SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
  380. /* SPK-OUT source */
  381. static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
  382. 0, rt286_dac_src);
  383. static const struct snd_kcontrol_new rt286_spo_mux =
  384. SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
  385. static int rt286_spk_event(struct snd_soc_dapm_widget *w,
  386. struct snd_kcontrol *kcontrol, int event)
  387. {
  388. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  389. switch (event) {
  390. case SND_SOC_DAPM_POST_PMU:
  391. snd_soc_component_write(component,
  392. RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
  393. break;
  394. case SND_SOC_DAPM_PRE_PMD:
  395. snd_soc_component_write(component,
  396. RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
  397. break;
  398. default:
  399. return 0;
  400. }
  401. return 0;
  402. }
  403. static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
  404. struct snd_kcontrol *kcontrol, int event)
  405. {
  406. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  407. switch (event) {
  408. case SND_SOC_DAPM_POST_PMU:
  409. snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
  410. break;
  411. case SND_SOC_DAPM_PRE_PMD:
  412. snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
  413. break;
  414. default:
  415. return 0;
  416. }
  417. return 0;
  418. }
  419. static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
  420. struct snd_kcontrol *kcontrol, int event)
  421. {
  422. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  423. switch (event) {
  424. case SND_SOC_DAPM_POST_PMU:
  425. snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
  426. break;
  427. case SND_SOC_DAPM_PRE_PMD:
  428. snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
  429. break;
  430. default:
  431. return 0;
  432. }
  433. return 0;
  434. }
  435. static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
  436. struct snd_kcontrol *kcontrol, int event)
  437. {
  438. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  439. switch (event) {
  440. case SND_SOC_DAPM_PRE_PMU:
  441. snd_soc_component_update_bits(component,
  442. RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
  443. snd_soc_component_update_bits(component,
  444. RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
  445. break;
  446. case SND_SOC_DAPM_POST_PMD:
  447. snd_soc_component_update_bits(component,
  448. RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
  449. snd_soc_component_update_bits(component,
  450. RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
  451. break;
  452. default:
  453. return 0;
  454. }
  455. return 0;
  456. }
  457. static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
  458. SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
  459. 12, 1, NULL, 0),
  460. SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
  461. 0, 1, NULL, 0),
  462. SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
  463. 2, 0, NULL, 0),
  464. SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
  465. 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
  466. SND_SOC_DAPM_POST_PMU),
  467. SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
  468. 5, 0, NULL, 0),
  469. SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
  470. 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
  471. SND_SOC_DAPM_POST_PMD),
  472. /* Input Lines */
  473. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  474. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  475. SND_SOC_DAPM_INPUT("MIC1"),
  476. SND_SOC_DAPM_INPUT("LINE1"),
  477. SND_SOC_DAPM_INPUT("Beep"),
  478. /* DMIC */
  479. SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
  480. NULL, 0, rt286_set_dmic1_event,
  481. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  482. SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
  483. NULL, 0),
  484. SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
  485. 0, 0, NULL, 0),
  486. /* REC Mixer */
  487. SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
  488. rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
  489. /* ADCs */
  490. SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
  491. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  492. /* ADC Mux */
  493. SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
  494. &rt286_adc0_mux),
  495. SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
  496. &rt286_adc1_mux),
  497. /* Audio Interface */
  498. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  499. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  500. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  501. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  502. /* Output Side */
  503. /* DACs */
  504. SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
  505. SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
  506. /* Output Mux */
  507. SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
  508. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
  509. SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
  510. RT286_SET_PIN_SFT, 0, NULL, 0),
  511. /* Output Mixer */
  512. SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
  513. rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
  514. SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
  515. NULL, 0),
  516. /* Output Pga */
  517. SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
  518. &spo_enable_control, rt286_spk_event,
  519. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  520. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  521. &hpol_enable_control),
  522. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  523. &hpor_enable_control),
  524. /* Output Lines */
  525. SND_SOC_DAPM_OUTPUT("SPOL"),
  526. SND_SOC_DAPM_OUTPUT("SPOR"),
  527. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  528. SND_SOC_DAPM_OUTPUT("SPDIF"),
  529. };
  530. static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
  531. {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
  532. {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
  533. {"Front", NULL, "MCLK MODE", is_mclk_mode},
  534. {"Surround", NULL, "MCLK MODE", is_mclk_mode},
  535. {"HP Power", NULL, "LDO1"},
  536. {"HP Power", NULL, "LDO2"},
  537. {"MIC1", NULL, "LDO1"},
  538. {"MIC1", NULL, "LDO2"},
  539. {"MIC1", NULL, "HV"},
  540. {"MIC1", NULL, "VREF"},
  541. {"MIC1", NULL, "MIC1 Input Buffer"},
  542. {"SPO", NULL, "LDO1"},
  543. {"SPO", NULL, "LDO2"},
  544. {"SPO", NULL, "HV"},
  545. {"SPO", NULL, "VREF"},
  546. {"DMIC1", NULL, "DMIC1 Pin"},
  547. {"DMIC2", NULL, "DMIC2 Pin"},
  548. {"DMIC1", NULL, "DMIC Receiver"},
  549. {"DMIC2", NULL, "DMIC Receiver"},
  550. {"RECMIX", "Beep Switch", "Beep"},
  551. {"RECMIX", "Line1 Switch", "LINE1"},
  552. {"RECMIX", "Mic1 Switch", "MIC1"},
  553. {"ADC 0 Mux", "Dmic", "DMIC1"},
  554. {"ADC 0 Mux", "RECMIX", "RECMIX"},
  555. {"ADC 0 Mux", "Mic", "MIC1"},
  556. {"ADC 1 Mux", "Dmic", "DMIC2"},
  557. {"ADC 1 Mux", "RECMIX", "RECMIX"},
  558. {"ADC 1 Mux", "Mic", "MIC1"},
  559. {"ADC 0", NULL, "ADC 0 Mux"},
  560. {"ADC 1", NULL, "ADC 1 Mux"},
  561. {"AIF1TX", NULL, "ADC 0"},
  562. {"AIF2TX", NULL, "ADC 1"},
  563. {"DAC 0", NULL, "AIF1RX"},
  564. {"DAC 1", NULL, "AIF2RX"},
  565. {"Front", "DAC Switch", "DAC 0"},
  566. {"Front", "RECMIX Switch", "RECMIX"},
  567. {"Surround", NULL, "DAC 1"},
  568. {"SPK Mux", "Front", "Front"},
  569. {"SPK Mux", "Surround", "Surround"},
  570. {"HPO Mux", "Front", "Front"},
  571. {"HPO Mux", "Surround", "Surround"},
  572. {"SPO", "Switch", "SPK Mux"},
  573. {"HPO L", "Switch", "HPO Mux"},
  574. {"HPO R", "Switch", "HPO Mux"},
  575. {"HPO L", NULL, "HP Power"},
  576. {"HPO R", NULL, "HP Power"},
  577. {"SPOL", NULL, "SPO"},
  578. {"SPOR", NULL, "SPO"},
  579. {"HPO Pin", NULL, "HPO L"},
  580. {"HPO Pin", NULL, "HPO R"},
  581. };
  582. static int rt286_hw_params(struct snd_pcm_substream *substream,
  583. struct snd_pcm_hw_params *params,
  584. struct snd_soc_dai *dai)
  585. {
  586. struct snd_soc_component *component = dai->component;
  587. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  588. unsigned int val = 0;
  589. int d_len_code;
  590. switch (params_rate(params)) {
  591. /* bit 14 0:48K 1:44.1K */
  592. case 44100:
  593. val |= 0x4000;
  594. break;
  595. case 48000:
  596. break;
  597. default:
  598. dev_err(component->dev, "Unsupported sample rate %d\n",
  599. params_rate(params));
  600. return -EINVAL;
  601. }
  602. switch (rt286->sys_clk) {
  603. case 12288000:
  604. case 24576000:
  605. if (params_rate(params) != 48000) {
  606. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  607. params_rate(params), rt286->sys_clk);
  608. return -EINVAL;
  609. }
  610. break;
  611. case 11289600:
  612. case 22579200:
  613. if (params_rate(params) != 44100) {
  614. dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
  615. params_rate(params), rt286->sys_clk);
  616. return -EINVAL;
  617. }
  618. break;
  619. }
  620. if (params_channels(params) <= 16) {
  621. /* bit 3:0 Number of Channel */
  622. val |= (params_channels(params) - 1);
  623. } else {
  624. dev_err(component->dev, "Unsupported channels %d\n",
  625. params_channels(params));
  626. return -EINVAL;
  627. }
  628. switch (params_width(params)) {
  629. /* bit 6:4 Bits per Sample */
  630. case 16:
  631. d_len_code = 0;
  632. val |= (0x1 << 4);
  633. break;
  634. case 32:
  635. d_len_code = 2;
  636. val |= (0x4 << 4);
  637. break;
  638. case 20:
  639. d_len_code = 1;
  640. val |= (0x2 << 4);
  641. break;
  642. case 24:
  643. d_len_code = 2;
  644. val |= (0x3 << 4);
  645. break;
  646. case 8:
  647. d_len_code = 3;
  648. break;
  649. default:
  650. return -EINVAL;
  651. }
  652. snd_soc_component_update_bits(component,
  653. RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
  654. dev_dbg(component->dev, "format val = 0x%x\n", val);
  655. snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
  656. snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
  657. return 0;
  658. }
  659. static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  660. {
  661. struct snd_soc_component *component = dai->component;
  662. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  663. case SND_SOC_DAIFMT_CBM_CFM:
  664. snd_soc_component_update_bits(component,
  665. RT286_I2S_CTRL1, 0x800, 0x800);
  666. break;
  667. case SND_SOC_DAIFMT_CBS_CFS:
  668. snd_soc_component_update_bits(component,
  669. RT286_I2S_CTRL1, 0x800, 0x0);
  670. break;
  671. default:
  672. return -EINVAL;
  673. }
  674. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  675. case SND_SOC_DAIFMT_I2S:
  676. snd_soc_component_update_bits(component,
  677. RT286_I2S_CTRL1, 0x300, 0x0);
  678. break;
  679. case SND_SOC_DAIFMT_LEFT_J:
  680. snd_soc_component_update_bits(component,
  681. RT286_I2S_CTRL1, 0x300, 0x1 << 8);
  682. break;
  683. case SND_SOC_DAIFMT_DSP_A:
  684. snd_soc_component_update_bits(component,
  685. RT286_I2S_CTRL1, 0x300, 0x2 << 8);
  686. break;
  687. case SND_SOC_DAIFMT_DSP_B:
  688. snd_soc_component_update_bits(component,
  689. RT286_I2S_CTRL1, 0x300, 0x3 << 8);
  690. break;
  691. default:
  692. return -EINVAL;
  693. }
  694. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  695. snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
  696. snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
  697. return 0;
  698. }
  699. static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
  700. int clk_id, unsigned int freq, int dir)
  701. {
  702. struct snd_soc_component *component = dai->component;
  703. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  704. dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
  705. if (RT286_SCLK_S_MCLK == clk_id) {
  706. snd_soc_component_update_bits(component,
  707. RT286_I2S_CTRL2, 0x0100, 0x0);
  708. snd_soc_component_update_bits(component,
  709. RT286_PLL_CTRL1, 0x20, 0x20);
  710. } else {
  711. snd_soc_component_update_bits(component,
  712. RT286_I2S_CTRL2, 0x0100, 0x0100);
  713. snd_soc_component_update_bits(component,
  714. RT286_PLL_CTRL, 0x4, 0x4);
  715. snd_soc_component_update_bits(component,
  716. RT286_PLL_CTRL1, 0x20, 0x0);
  717. }
  718. switch (freq) {
  719. case 19200000:
  720. if (RT286_SCLK_S_MCLK == clk_id) {
  721. dev_err(component->dev, "Should not use MCLK\n");
  722. return -EINVAL;
  723. }
  724. snd_soc_component_update_bits(component,
  725. RT286_I2S_CTRL2, 0x40, 0x40);
  726. break;
  727. case 24000000:
  728. if (RT286_SCLK_S_MCLK == clk_id) {
  729. dev_err(component->dev, "Should not use MCLK\n");
  730. return -EINVAL;
  731. }
  732. snd_soc_component_update_bits(component,
  733. RT286_I2S_CTRL2, 0x40, 0x0);
  734. break;
  735. case 12288000:
  736. case 11289600:
  737. snd_soc_component_update_bits(component,
  738. RT286_I2S_CTRL2, 0x8, 0x0);
  739. snd_soc_component_update_bits(component,
  740. RT286_CLK_DIV, 0xfc1e, 0x0004);
  741. break;
  742. case 24576000:
  743. case 22579200:
  744. snd_soc_component_update_bits(component,
  745. RT286_I2S_CTRL2, 0x8, 0x8);
  746. snd_soc_component_update_bits(component,
  747. RT286_CLK_DIV, 0xfc1e, 0x5406);
  748. break;
  749. default:
  750. dev_err(component->dev, "Unsupported system clock\n");
  751. return -EINVAL;
  752. }
  753. rt286->sys_clk = freq;
  754. rt286->clk_id = clk_id;
  755. return 0;
  756. }
  757. static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  758. {
  759. struct snd_soc_component *component = dai->component;
  760. dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
  761. if (50 == ratio)
  762. snd_soc_component_update_bits(component,
  763. RT286_I2S_CTRL1, 0x1000, 0x1000);
  764. else
  765. snd_soc_component_update_bits(component,
  766. RT286_I2S_CTRL1, 0x1000, 0x0);
  767. return 0;
  768. }
  769. static int rt286_set_bias_level(struct snd_soc_component *component,
  770. enum snd_soc_bias_level level)
  771. {
  772. switch (level) {
  773. case SND_SOC_BIAS_PREPARE:
  774. if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
  775. snd_soc_component_write(component,
  776. RT286_SET_AUDIO_POWER, AC_PWRST_D0);
  777. snd_soc_component_update_bits(component,
  778. RT286_DC_GAIN, 0x200, 0x200);
  779. }
  780. break;
  781. case SND_SOC_BIAS_ON:
  782. mdelay(10);
  783. snd_soc_component_update_bits(component,
  784. RT286_DC_GAIN, 0x200, 0x0);
  785. break;
  786. case SND_SOC_BIAS_STANDBY:
  787. snd_soc_component_write(component,
  788. RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  789. break;
  790. default:
  791. break;
  792. }
  793. return 0;
  794. }
  795. static irqreturn_t rt286_irq(int irq, void *data)
  796. {
  797. struct rt286_priv *rt286 = data;
  798. bool hp = false;
  799. bool mic = false;
  800. int status = 0;
  801. rt286_jack_detect(rt286, &hp, &mic);
  802. /* Clear IRQ */
  803. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
  804. if (hp)
  805. status |= SND_JACK_HEADPHONE;
  806. if (mic)
  807. status |= SND_JACK_MICROPHONE;
  808. snd_soc_jack_report(rt286->jack, status,
  809. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  810. pm_wakeup_event(&rt286->i2c->dev, 300);
  811. return IRQ_HANDLED;
  812. }
  813. static int rt286_probe(struct snd_soc_component *component)
  814. {
  815. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  816. rt286->component = component;
  817. INIT_DELAYED_WORK(&rt286->jack_detect_work, rt286_jack_detect_work);
  818. if (rt286->i2c->irq)
  819. schedule_delayed_work(&rt286->jack_detect_work,
  820. msecs_to_jiffies(50));
  821. return 0;
  822. }
  823. static void rt286_remove(struct snd_soc_component *component)
  824. {
  825. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  826. cancel_delayed_work_sync(&rt286->jack_detect_work);
  827. rt286->component = NULL;
  828. }
  829. #ifdef CONFIG_PM
  830. static int rt286_suspend(struct snd_soc_component *component)
  831. {
  832. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  833. regcache_cache_only(rt286->regmap, true);
  834. regcache_mark_dirty(rt286->regmap);
  835. return 0;
  836. }
  837. static int rt286_resume(struct snd_soc_component *component)
  838. {
  839. struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
  840. regcache_cache_only(rt286->regmap, false);
  841. rt286_index_sync(component);
  842. regcache_sync(rt286->regmap);
  843. return 0;
  844. }
  845. #else
  846. #define rt286_suspend NULL
  847. #define rt286_resume NULL
  848. #endif
  849. #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  850. #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  851. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  852. static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
  853. .hw_params = rt286_hw_params,
  854. .set_fmt = rt286_set_dai_fmt,
  855. .set_sysclk = rt286_set_dai_sysclk,
  856. .set_bclk_ratio = rt286_set_bclk_ratio,
  857. };
  858. static struct snd_soc_dai_driver rt286_dai[] = {
  859. {
  860. .name = "rt286-aif1",
  861. .id = RT286_AIF1,
  862. .playback = {
  863. .stream_name = "AIF1 Playback",
  864. .channels_min = 1,
  865. .channels_max = 2,
  866. .rates = RT286_STEREO_RATES,
  867. .formats = RT286_FORMATS,
  868. },
  869. .capture = {
  870. .stream_name = "AIF1 Capture",
  871. .channels_min = 1,
  872. .channels_max = 2,
  873. .rates = RT286_STEREO_RATES,
  874. .formats = RT286_FORMATS,
  875. },
  876. .ops = &rt286_aif_dai_ops,
  877. .symmetric_rate = 1,
  878. },
  879. {
  880. .name = "rt286-aif2",
  881. .id = RT286_AIF2,
  882. .playback = {
  883. .stream_name = "AIF2 Playback",
  884. .channels_min = 1,
  885. .channels_max = 2,
  886. .rates = RT286_STEREO_RATES,
  887. .formats = RT286_FORMATS,
  888. },
  889. .capture = {
  890. .stream_name = "AIF2 Capture",
  891. .channels_min = 1,
  892. .channels_max = 2,
  893. .rates = RT286_STEREO_RATES,
  894. .formats = RT286_FORMATS,
  895. },
  896. .ops = &rt286_aif_dai_ops,
  897. .symmetric_rate = 1,
  898. },
  899. };
  900. static const struct snd_soc_component_driver soc_component_dev_rt286 = {
  901. .probe = rt286_probe,
  902. .remove = rt286_remove,
  903. .suspend = rt286_suspend,
  904. .resume = rt286_resume,
  905. .set_bias_level = rt286_set_bias_level,
  906. .set_jack = rt286_mic_detect,
  907. .controls = rt286_snd_controls,
  908. .num_controls = ARRAY_SIZE(rt286_snd_controls),
  909. .dapm_widgets = rt286_dapm_widgets,
  910. .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
  911. .dapm_routes = rt286_dapm_routes,
  912. .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
  913. .use_pmdown_time = 1,
  914. .endianness = 1,
  915. };
  916. static const struct regmap_config rt286_regmap = {
  917. .reg_bits = 32,
  918. .val_bits = 32,
  919. .max_register = 0x02370100,
  920. .volatile_reg = rt286_volatile_register,
  921. .readable_reg = rt286_readable_register,
  922. .reg_write = rl6347a_hw_write,
  923. .reg_read = rl6347a_hw_read,
  924. .cache_type = REGCACHE_RBTREE,
  925. .reg_defaults = rt286_reg,
  926. .num_reg_defaults = ARRAY_SIZE(rt286_reg),
  927. };
  928. static const struct i2c_device_id rt286_i2c_id[] = {
  929. {"rt286", 0},
  930. {"rt288", 0},
  931. {}
  932. };
  933. MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
  934. #ifdef CONFIG_ACPI
  935. static const struct acpi_device_id rt286_acpi_match[] = {
  936. { "INT343A", 0 },
  937. {},
  938. };
  939. MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
  940. #endif
  941. static const struct dmi_system_id force_combo_jack_table[] = {
  942. {
  943. .ident = "Intel Wilson Beach",
  944. .matches = {
  945. DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
  946. }
  947. },
  948. {
  949. .ident = "Intel Skylake RVP",
  950. .matches = {
  951. DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
  952. }
  953. },
  954. {
  955. .ident = "Intel Kabylake RVP",
  956. .matches = {
  957. DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
  958. }
  959. },
  960. {
  961. .ident = "Thinkpad Helix 2nd",
  962. .matches = {
  963. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  964. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
  965. }
  966. },
  967. { }
  968. };
  969. static const struct dmi_system_id dmi_dell[] = {
  970. {
  971. .ident = "Dell",
  972. .matches = {
  973. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  974. }
  975. },
  976. { }
  977. };
  978. static int rt286_i2c_probe(struct i2c_client *i2c)
  979. {
  980. struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
  981. struct rt286_priv *rt286;
  982. int i, ret, vendor_id;
  983. rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
  984. GFP_KERNEL);
  985. if (NULL == rt286)
  986. return -ENOMEM;
  987. rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
  988. if (IS_ERR(rt286->regmap)) {
  989. ret = PTR_ERR(rt286->regmap);
  990. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  991. ret);
  992. return ret;
  993. }
  994. ret = regmap_read(rt286->regmap,
  995. RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
  996. if (ret != 0) {
  997. dev_err(&i2c->dev, "I2C error %d\n", ret);
  998. return ret;
  999. }
  1000. if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
  1001. dev_err(&i2c->dev,
  1002. "Device with ID register %#x is not rt286\n",
  1003. vendor_id);
  1004. return -ENODEV;
  1005. }
  1006. rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
  1007. sizeof(rt286_index_def), GFP_KERNEL);
  1008. if (!rt286->index_cache)
  1009. return -ENOMEM;
  1010. rt286->index_cache_size = INDEX_CACHE_SIZE;
  1011. rt286->i2c = i2c;
  1012. i2c_set_clientdata(i2c, rt286);
  1013. /* restore codec default */
  1014. for (i = 0; i < INDEX_CACHE_SIZE; i++)
  1015. regmap_write(rt286->regmap, rt286->index_cache[i].reg,
  1016. rt286->index_cache[i].def);
  1017. for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
  1018. regmap_write(rt286->regmap, rt286_reg[i].reg,
  1019. rt286_reg[i].def);
  1020. if (pdata)
  1021. rt286->pdata = *pdata;
  1022. if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
  1023. dmi_check_system(force_combo_jack_table))
  1024. rt286->pdata.cbj_en = true;
  1025. regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  1026. for (i = 0; i < RT286_POWER_REG_LEN; i++)
  1027. regmap_write(rt286->regmap,
  1028. RT286_SET_POWER(rt286_support_power_controls[i]),
  1029. AC_PWRST_D1);
  1030. if (!rt286->pdata.cbj_en) {
  1031. regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
  1032. regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
  1033. regmap_update_bits(rt286->regmap,
  1034. RT286_CBJ_CTRL1, 0xf000, 0xb000);
  1035. } else {
  1036. regmap_update_bits(rt286->regmap,
  1037. RT286_CBJ_CTRL1, 0xf000, 0x5000);
  1038. }
  1039. mdelay(10);
  1040. if (!rt286->pdata.gpio2_en)
  1041. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x40);
  1042. else
  1043. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
  1044. mdelay(10);
  1045. regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
  1046. /* Power down LDO, VREF */
  1047. regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
  1048. regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
  1049. /* Set depop parameter */
  1050. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
  1051. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
  1052. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
  1053. if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
  1054. regmap_update_bits(rt286->regmap,
  1055. RT286_SET_GPIO_MASK, 0x40, 0x40);
  1056. regmap_update_bits(rt286->regmap,
  1057. RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
  1058. regmap_update_bits(rt286->regmap,
  1059. RT286_SET_GPIO_DATA, 0x40, 0x40);
  1060. regmap_update_bits(rt286->regmap,
  1061. RT286_GPIO_CTRL, 0xc, 0x8);
  1062. }
  1063. if (rt286->i2c->irq) {
  1064. ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
  1065. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
  1066. if (ret != 0) {
  1067. dev_err(&i2c->dev,
  1068. "Failed to reguest IRQ: %d\n", ret);
  1069. return ret;
  1070. }
  1071. }
  1072. ret = devm_snd_soc_register_component(&i2c->dev,
  1073. &soc_component_dev_rt286,
  1074. rt286_dai, ARRAY_SIZE(rt286_dai));
  1075. return ret;
  1076. }
  1077. static void rt286_i2c_remove(struct i2c_client *i2c)
  1078. {
  1079. struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
  1080. if (i2c->irq)
  1081. free_irq(i2c->irq, rt286);
  1082. }
  1083. static struct i2c_driver rt286_i2c_driver = {
  1084. .driver = {
  1085. .name = "rt286",
  1086. .acpi_match_table = ACPI_PTR(rt286_acpi_match),
  1087. },
  1088. .probe_new = rt286_i2c_probe,
  1089. .remove = rt286_i2c_remove,
  1090. .id_table = rt286_i2c_id,
  1091. };
  1092. module_i2c_driver(rt286_i2c_driver);
  1093. MODULE_DESCRIPTION("ASoC RT286 driver");
  1094. MODULE_AUTHOR("Bard Liao <[email protected]>");
  1095. MODULE_LICENSE("GPL");