rt1019.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * rt1019.h -- RT1019 ALSA SoC audio amplifier driver
  4. *
  5. * Copyright(c) 2021 Realtek Semiconductor Corp.
  6. */
  7. #ifndef __RT1019_H__
  8. #define __RT1019_H__
  9. #define RT1019_DEVICE_ID_VAL 0x1019
  10. #define RT1019_DEVICE_ID_VAL2 0x6731
  11. #define RT1019_RESET 0x0000
  12. #define RT1019_IDS_CTRL 0x0011
  13. #define RT1019_ASEL_CTRL 0x0013
  14. #define RT1019_PWR_STRP_2 0x0019
  15. #define RT1019_BEEP_TONE 0x001b
  16. #define RT1019_VER_ID 0x005c
  17. #define RT1019_VEND_ID_1 0x005e
  18. #define RT1019_VEND_ID_2 0x005f
  19. #define RT1019_DEV_ID_1 0x0061
  20. #define RT1019_DEV_ID_2 0x0062
  21. #define RT1019_SDB_CTRL 0x0066
  22. #define RT1019_CLK_TREE_1 0x0100
  23. #define RT1019_CLK_TREE_2 0x0101
  24. #define RT1019_CLK_TREE_3 0x0102
  25. #define RT1019_PLL_1 0x0311
  26. #define RT1019_PLL_2 0x0312
  27. #define RT1019_PLL_3 0x0313
  28. #define RT1019_TDM_1 0x0400
  29. #define RT1019_TDM_2 0x0401
  30. #define RT1019_TDM_3 0x0402
  31. #define RT1019_DMIX_MONO_1 0x0504
  32. #define RT1019_DMIX_MONO_2 0x0505
  33. #define RT1019_BEEP_1 0x0b00
  34. #define RT1019_BEEP_2 0x0b01
  35. /* 0x0019 Power On Strap Control-2 */
  36. #define RT1019_AUTO_BITS_SEL_MASK (0x1 << 5)
  37. #define RT1019_AUTO_BITS_SEL_AUTO (0x1 << 5)
  38. #define RT1019_AUTO_BITS_SEL_MANU (0x0 << 5)
  39. #define RT1019_AUTO_CLK_SEL_MASK (0x1 << 4)
  40. #define RT1019_AUTO_CLK_SEL_AUTO (0x1 << 4)
  41. #define RT1019_AUTO_CLK_SEL_MANU (0x0 << 4)
  42. /* 0x0100 Clock Tree Control-1 */
  43. #define RT1019_CLK_SYS_PRE_SEL_MASK (0x1 << 7)
  44. #define RT1019_CLK_SYS_PRE_SEL_SFT 7
  45. #define RT1019_CLK_SYS_PRE_SEL_BCLK (0x0 << 7)
  46. #define RT1019_CLK_SYS_PRE_SEL_PLL (0x1 << 7)
  47. #define RT1019_PLL_SRC_MASK (0x1 << 4)
  48. #define RT1019_PLL_SRC_SFT 4
  49. #define RT1019_PLL_SRC_SEL_BCLK (0x0 << 4)
  50. #define RT1019_PLL_SRC_SEL_RC (0x1 << 4)
  51. #define RT1019_SEL_FIFO_MASK (0x3 << 2)
  52. #define RT1019_SEL_FIFO_DIV1 (0x0 << 2)
  53. #define RT1019_SEL_FIFO_DIV2 (0x1 << 2)
  54. #define RT1019_SEL_FIFO_DIV4 (0x2 << 2)
  55. /* 0x0101 clock tree control-2 */
  56. #define RT1019_SYS_DIV_DA_FIL_MASK (0x7 << 5)
  57. #define RT1019_SYS_DIV_DA_FIL_DIV1 (0x2 << 5)
  58. #define RT1019_SYS_DIV_DA_FIL_DIV2 (0x3 << 5)
  59. #define RT1019_SYS_DIV_DA_FIL_DIV4 (0x4 << 5)
  60. #define RT1019_SYS_DA_OSR_MASK (0x3 << 2)
  61. #define RT1019_SYS_DA_OSR_DIV1 (0x0 << 2)
  62. #define RT1019_SYS_DA_OSR_DIV2 (0x1 << 2)
  63. #define RT1019_SYS_DA_OSR_DIV4 (0x2 << 2)
  64. #define RT1019_ASRC_256FS_MASK 0x3
  65. #define RT1019_ASRC_256FS_DIV1 0x0
  66. #define RT1019_ASRC_256FS_DIV2 0x1
  67. #define RT1019_ASRC_256FS_DIV4 0x2
  68. /* 0x0102 clock tree control-3 */
  69. #define RT1019_SEL_CLK_CAL_MASK (0x3 << 6)
  70. #define RT1019_SEL_CLK_CAL_DIV1 (0x0 << 6)
  71. #define RT1019_SEL_CLK_CAL_DIV2 (0x1 << 6)
  72. #define RT1019_SEL_CLK_CAL_DIV4 (0x2 << 6)
  73. /* 0x0311 PLL-1 */
  74. #define RT1019_PLL_M_MASK (0xf << 4)
  75. #define RT1019_PLL_M_SFT 4
  76. #define RT1019_PLL_M_BP_MASK (0x1 << 1)
  77. #define RT1019_PLL_M_BP_SFT 1
  78. #define RT1019_PLL_Q_8_8_MASK (0x1)
  79. /* 0x0312 PLL-2 */
  80. #define RT1019_PLL_Q_7_0_MASK 0xff
  81. /* 0x0313 PLL-3 */
  82. #define RT1019_PLL_K_MASK 0x1f
  83. /* 0x0400 TDM Control-1 */
  84. #define RT1019_TDM_BCLK_MASK (0x1 << 6)
  85. #define RT1019_TDM_BCLK_NORM (0x0 << 6)
  86. #define RT1019_TDM_BCLK_INV (0x1 << 6)
  87. #define RT1019_TDM_CL_MASK (0x7)
  88. #define RT1019_TDM_CL_8 (0x4)
  89. #define RT1019_TDM_CL_32 (0x3)
  90. #define RT1019_TDM_CL_24 (0x2)
  91. #define RT1019_TDM_CL_20 (0x1)
  92. #define RT1019_TDM_CL_16 (0x0)
  93. /* 0x0401 TDM Control-2 */
  94. #define RT1019_I2S_CH_TX_MASK (0x3 << 6)
  95. #define RT1019_I2S_CH_TX_SFT 6
  96. #define RT1019_I2S_TX_2CH (0x0 << 6)
  97. #define RT1019_I2S_TX_4CH (0x1 << 6)
  98. #define RT1019_I2S_TX_6CH (0x2 << 6)
  99. #define RT1019_I2S_TX_8CH (0x3 << 6)
  100. #define RT1019_I2S_DF_MASK (0x7 << 3)
  101. #define RT1019_I2S_DF_SFT 3
  102. #define RT1019_I2S_DF_I2S (0x0 << 3)
  103. #define RT1019_I2S_DF_LEFT (0x1 << 3)
  104. #define RT1019_I2S_DF_PCM_A_R (0x2 << 3)
  105. #define RT1019_I2S_DF_PCM_B_R (0x3 << 3)
  106. #define RT1019_I2S_DF_PCM_A_F (0x6 << 3)
  107. #define RT1019_I2S_DF_PCM_B_F (0x7 << 3)
  108. #define RT1019_I2S_DL_MASK 0x7
  109. #define RT1019_I2S_DL_SFT 0
  110. #define RT1019_I2S_DL_16 0x0
  111. #define RT1019_I2S_DL_20 0x1
  112. #define RT1019_I2S_DL_24 0x2
  113. #define RT1019_I2S_DL_32 0x3
  114. #define RT1019_I2S_DL_8 0x4
  115. /* TDM1 Control-3 (0x0402) */
  116. #define RT1019_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 4)
  117. #define RT1019_TDM_I2S_TX_R_DAC1_1_MASK 0x7
  118. #define RT1019_TDM_I2S_TX_L_DAC1_1_SFT 4
  119. #define RT1019_TDM_I2S_TX_R_DAC1_1_SFT 0
  120. /* System Clock Source */
  121. enum {
  122. RT1019_SCLK_S_BCLK,
  123. RT1019_SCLK_S_PLL,
  124. };
  125. /* PLL1 Source */
  126. enum {
  127. RT1019_PLL_S_BCLK,
  128. RT1019_PLL_S_RC25M,
  129. };
  130. enum {
  131. RT1019_AIF1,
  132. RT1019_AIFS
  133. };
  134. struct rt1019_priv {
  135. struct snd_soc_component *component;
  136. struct regmap *regmap;
  137. int sysclk;
  138. int sysclk_src;
  139. int lrck;
  140. int bclk;
  141. int pll_src;
  142. int pll_in;
  143. int pll_out;
  144. unsigned int bclk_ratio;
  145. };
  146. #endif /* __RT1019_H__ */