rt1011.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * rt1011.h -- RT1011 ALSA SoC amplifier component driver header
  4. *
  5. * Copyright(c) 2019 Realtek Semiconductor Corp.
  6. */
  7. #ifndef _RT1011_H_
  8. #define _RT1011_H_
  9. #define RT1011_DEVICE_ID_NUM 0x1011
  10. #define RT1011_RESET 0x0000
  11. #define RT1011_CLK_1 0x0002
  12. #define RT1011_CLK_2 0x0004
  13. #define RT1011_CLK_3 0x0006
  14. #define RT1011_CLK_4 0x0008
  15. #define RT1011_PLL_1 0x000a
  16. #define RT1011_PLL_2 0x000c
  17. #define RT1011_SRC_1 0x000e
  18. #define RT1011_SRC_2 0x0010
  19. #define RT1011_SRC_3 0x0012
  20. #define RT1011_CLK_DET 0x0020
  21. #define RT1011_SIL_DET 0x0022
  22. #define RT1011_PRIV_INDEX 0x006a
  23. #define RT1011_PRIV_DATA 0x006c
  24. #define RT1011_CUSTOMER_ID 0x0076
  25. #define RT1011_FM_VER 0x0078
  26. #define RT1011_VERSION_ID 0x007a
  27. #define RT1011_VENDOR_ID 0x007c
  28. #define RT1011_DEVICE_ID 0x007d
  29. #define RT1011_DUM_RW_0 0x00f0
  30. #define RT1011_DUM_YUN 0x00f2
  31. #define RT1011_DUM_RW_1 0x00f3
  32. #define RT1011_DUM_RO 0x00f4
  33. #define RT1011_MAN_I2C_DEV 0x0100
  34. #define RT1011_DAC_SET_1 0x0102
  35. #define RT1011_DAC_SET_2 0x0104
  36. #define RT1011_DAC_SET_3 0x0106
  37. #define RT1011_ADC_SET 0x0107
  38. #define RT1011_ADC_SET_1 0x0108
  39. #define RT1011_ADC_SET_2 0x010a
  40. #define RT1011_ADC_SET_3 0x010c
  41. #define RT1011_ADC_SET_4 0x010e
  42. #define RT1011_ADC_SET_5 0x0110
  43. #define RT1011_TDM_TOTAL_SET 0x0111
  44. #define RT1011_TDM1_SET_TCON 0x0112
  45. #define RT1011_TDM1_SET_1 0x0114
  46. #define RT1011_TDM1_SET_2 0x0116
  47. #define RT1011_TDM1_SET_3 0x0118
  48. #define RT1011_TDM1_SET_4 0x011a
  49. #define RT1011_TDM1_SET_5 0x011c
  50. #define RT1011_TDM2_SET_1 0x011e
  51. #define RT1011_TDM2_SET_2 0x0120
  52. #define RT1011_TDM2_SET_3 0x0122
  53. #define RT1011_TDM2_SET_4 0x0124
  54. #define RT1011_TDM2_SET_5 0x0126
  55. #define RT1011_PWM_CAL 0x0200
  56. #define RT1011_MIXER_1 0x0300
  57. #define RT1011_MIXER_2 0x0302
  58. #define RT1011_ADRC_LIMIT 0x0310
  59. #define RT1011_A_PRO 0x0311
  60. #define RT1011_A_TIMING_1 0x0313
  61. #define RT1011_A_TIMING_2 0x0314
  62. #define RT1011_A_TEMP_SEN 0x0316
  63. #define RT1011_SPK_VOL_DET_1 0x0319
  64. #define RT1011_SPK_VOL_DET_2 0x031a
  65. #define RT1011_SPK_VOL_TEST_OUT 0x031b
  66. #define RT1011_VBAT_VOL_DET_1 0x031c
  67. #define RT1011_VBAT_VOL_DET_2 0x031d
  68. #define RT1011_VBAT_TEST_OUT_1 0x031e
  69. #define RT1011_VBAT_TEST_OUT_2 0x031f
  70. #define RT1011_VBAT_PROTECTION 0x0320
  71. #define RT1011_VBAT_DET 0x0321
  72. #define RT1011_POWER_1 0x0322
  73. #define RT1011_POWER_2 0x0324
  74. #define RT1011_POWER_3 0x0326
  75. #define RT1011_POWER_4 0x0328
  76. #define RT1011_POWER_5 0x0329
  77. #define RT1011_POWER_6 0x032a
  78. #define RT1011_POWER_7 0x032b
  79. #define RT1011_POWER_8 0x032c
  80. #define RT1011_POWER_9 0x032d
  81. #define RT1011_CLASS_D_POS 0x032e
  82. #define RT1011_BOOST_CON_1 0x0330
  83. #define RT1011_BOOST_CON_2 0x0332
  84. #define RT1011_ANALOG_CTRL 0x0334
  85. #define RT1011_POWER_SEQ 0x0340
  86. #define RT1011_SHORT_CIRCUIT_DET_1 0x0508
  87. #define RT1011_SHORT_CIRCUIT_DET_2 0x050a
  88. #define RT1011_SPK_TEMP_PROTECT_0 0x050c
  89. #define RT1011_SPK_TEMP_PROTECT_1 0x050d
  90. #define RT1011_SPK_TEMP_PROTECT_2 0x050e
  91. #define RT1011_SPK_TEMP_PROTECT_3 0x050f
  92. #define RT1011_SPK_TEMP_PROTECT_4 0x0510
  93. #define RT1011_SPK_TEMP_PROTECT_5 0x0511
  94. #define RT1011_SPK_TEMP_PROTECT_6 0x0512
  95. #define RT1011_SPK_TEMP_PROTECT_7 0x0516
  96. #define RT1011_SPK_TEMP_PROTECT_8 0x0517
  97. #define RT1011_SPK_TEMP_PROTECT_9 0x0518
  98. #define RT1011_SPK_PRO_DC_DET_1 0x0519
  99. #define RT1011_SPK_PRO_DC_DET_2 0x051a
  100. #define RT1011_SPK_PRO_DC_DET_3 0x051b
  101. #define RT1011_SPK_PRO_DC_DET_4 0x051c
  102. #define RT1011_SPK_PRO_DC_DET_5 0x051d
  103. #define RT1011_SPK_PRO_DC_DET_6 0x051e
  104. #define RT1011_SPK_PRO_DC_DET_7 0x051f
  105. #define RT1011_SPK_PRO_DC_DET_8 0x0520
  106. #define RT1011_SPL_1 0x0521
  107. #define RT1011_SPL_2 0x0522
  108. #define RT1011_SPL_3 0x0524
  109. #define RT1011_SPL_4 0x0526
  110. #define RT1011_THER_FOLD_BACK_1 0x0528
  111. #define RT1011_THER_FOLD_BACK_2 0x052a
  112. #define RT1011_EXCUR_PROTECT_1 0x0530
  113. #define RT1011_EXCUR_PROTECT_2 0x0532
  114. #define RT1011_EXCUR_PROTECT_3 0x0534
  115. #define RT1011_EXCUR_PROTECT_4 0x0535
  116. #define RT1011_BAT_GAIN_1 0x0536
  117. #define RT1011_BAT_GAIN_2 0x0538
  118. #define RT1011_BAT_GAIN_3 0x053a
  119. #define RT1011_BAT_GAIN_4 0x053c
  120. #define RT1011_BAT_GAIN_5 0x053d
  121. #define RT1011_BAT_GAIN_6 0x053e
  122. #define RT1011_BAT_GAIN_7 0x053f
  123. #define RT1011_BAT_GAIN_8 0x0540
  124. #define RT1011_BAT_GAIN_9 0x0541
  125. #define RT1011_BAT_GAIN_10 0x0542
  126. #define RT1011_BAT_GAIN_11 0x0543
  127. #define RT1011_BAT_RT_THMAX_1 0x0544
  128. #define RT1011_BAT_RT_THMAX_2 0x0545
  129. #define RT1011_BAT_RT_THMAX_3 0x0546
  130. #define RT1011_BAT_RT_THMAX_4 0x0547
  131. #define RT1011_BAT_RT_THMAX_5 0x0548
  132. #define RT1011_BAT_RT_THMAX_6 0x0549
  133. #define RT1011_BAT_RT_THMAX_7 0x054a
  134. #define RT1011_BAT_RT_THMAX_8 0x054b
  135. #define RT1011_BAT_RT_THMAX_9 0x054c
  136. #define RT1011_BAT_RT_THMAX_10 0x054d
  137. #define RT1011_BAT_RT_THMAX_11 0x054e
  138. #define RT1011_BAT_RT_THMAX_12 0x054f
  139. #define RT1011_SPREAD_SPECTURM 0x0568
  140. #define RT1011_PRO_GAIN_MODE 0x056a
  141. #define RT1011_RT_DRC_CROSS 0x0600
  142. #define RT1011_RT_DRC_HB_1 0x0611
  143. #define RT1011_RT_DRC_HB_2 0x0612
  144. #define RT1011_RT_DRC_HB_3 0x0613
  145. #define RT1011_RT_DRC_HB_4 0x0614
  146. #define RT1011_RT_DRC_HB_5 0x0615
  147. #define RT1011_RT_DRC_HB_6 0x0616
  148. #define RT1011_RT_DRC_HB_7 0x0617
  149. #define RT1011_RT_DRC_HB_8 0x0618
  150. #define RT1011_RT_DRC_BB_1 0x0621
  151. #define RT1011_RT_DRC_BB_2 0x0622
  152. #define RT1011_RT_DRC_BB_3 0x0623
  153. #define RT1011_RT_DRC_BB_4 0x0624
  154. #define RT1011_RT_DRC_BB_5 0x0625
  155. #define RT1011_RT_DRC_BB_6 0x0626
  156. #define RT1011_RT_DRC_BB_7 0x0627
  157. #define RT1011_RT_DRC_BB_8 0x0628
  158. #define RT1011_RT_DRC_POS_1 0x0631
  159. #define RT1011_RT_DRC_POS_2 0x0632
  160. #define RT1011_RT_DRC_POS_3 0x0633
  161. #define RT1011_RT_DRC_POS_4 0x0634
  162. #define RT1011_RT_DRC_POS_5 0x0635
  163. #define RT1011_RT_DRC_POS_6 0x0636
  164. #define RT1011_RT_DRC_POS_7 0x0637
  165. #define RT1011_RT_DRC_POS_8 0x0638
  166. #define RT1011_CROSS_BQ_SET_1 0x0702
  167. #define RT1011_CROSS_BQ_SET_2 0x0704
  168. #define RT1011_BQ_SET_0 0x0706
  169. #define RT1011_BQ_SET_1 0x0708
  170. #define RT1011_BQ_SET_2 0x070a
  171. #define RT1011_BQ_PRE_GAIN_28_16 0x0710
  172. #define RT1011_BQ_PRE_GAIN_15_0 0x0711
  173. #define RT1011_BQ_POST_GAIN_28_16 0x0712
  174. #define RT1011_BQ_POST_GAIN_15_0 0x0713
  175. #define RT1011_BQ_H0_28_16 0x0720
  176. #define RT1011_BQ_A2_15_0 0x0729
  177. #define RT1011_BQ_1_H0_28_16 0x0730
  178. #define RT1011_BQ_1_A2_15_0 0x0739
  179. #define RT1011_BQ_2_H0_28_16 0x0740
  180. #define RT1011_BQ_2_A2_15_0 0x0749
  181. #define RT1011_BQ_3_H0_28_16 0x0750
  182. #define RT1011_BQ_3_A2_15_0 0x0759
  183. #define RT1011_BQ_4_H0_28_16 0x0760
  184. #define RT1011_BQ_4_A2_15_0 0x0769
  185. #define RT1011_BQ_5_H0_28_16 0x0770
  186. #define RT1011_BQ_5_A2_15_0 0x0779
  187. #define RT1011_BQ_6_H0_28_16 0x0780
  188. #define RT1011_BQ_6_A2_15_0 0x0789
  189. #define RT1011_BQ_7_H0_28_16 0x0790
  190. #define RT1011_BQ_7_A2_15_0 0x0799
  191. #define RT1011_BQ_8_H0_28_16 0x07a0
  192. #define RT1011_BQ_8_A2_15_0 0x07a9
  193. #define RT1011_BQ_9_H0_28_16 0x07b0
  194. #define RT1011_BQ_9_A2_15_0 0x07b9
  195. #define RT1011_BQ_10_H0_28_16 0x07c0
  196. #define RT1011_BQ_10_A2_15_0 0x07c9
  197. #define RT1011_TEST_PAD_STATUS 0x1000
  198. #define RT1011_SYSTEM_RESET_1 0x1007
  199. #define RT1011_SYSTEM_RESET_2 0x1008
  200. #define RT1011_SYSTEM_RESET_3 0x1009
  201. #define RT1011_ADCDAT_OUT_SOURCE 0x100D
  202. #define RT1011_PLL_INTERNAL_SET 0x1010
  203. #define RT1011_TEST_OUT_1 0x1020
  204. #define RT1011_TEST_OUT_3 0x1024
  205. #define RT1011_DC_CALIB_CLASSD_1 0x1200
  206. #define RT1011_DC_CALIB_CLASSD_2 0x1202
  207. #define RT1011_DC_CALIB_CLASSD_3 0x1204
  208. #define RT1011_DC_CALIB_CLASSD_5 0x1208
  209. #define RT1011_DC_CALIB_CLASSD_6 0x120a
  210. #define RT1011_DC_CALIB_CLASSD_7 0x120c
  211. #define RT1011_DC_CALIB_CLASSD_8 0x120e
  212. #define RT1011_DC_CALIB_CLASSD_10 0x1212
  213. #define RT1011_CLASSD_INTERNAL_SET_1 0x1300
  214. #define RT1011_CLASSD_INTERNAL_SET_3 0x1304
  215. #define RT1011_CLASSD_INTERNAL_SET_8 0x130c
  216. #define RT1011_VREF_LV_1 0x131a
  217. #define RT1011_SMART_BOOST_TIMING_1 0x1322
  218. #define RT1011_SMART_BOOST_TIMING_36 0x1349
  219. #define RT1011_SINE_GEN_REG_1 0x1500
  220. #define RT1011_SINE_GEN_REG_2 0x1502
  221. #define RT1011_SINE_GEN_REG_3 0x1504
  222. #define RT1011_STP_INITIAL_RS_TEMP 0x1510
  223. #define RT1011_STP_CALIB_RS_TEMP 0x152a
  224. #define RT1011_INIT_RECIPROCAL_REG_24_16 0x1538
  225. #define RT1011_INIT_RECIPROCAL_REG_15_0 0x1539
  226. #define RT1011_STP_INITIAL_RESISTANCE_TEMP 0x153c
  227. #define RT1011_STP_ALPHA_RECIPROCAL_MSB 0x153e
  228. #define RT1011_SPK_RESISTANCE_1 0x1544
  229. #define RT1011_SPK_RESISTANCE_2 0x1546
  230. #define RT1011_SPK_THERMAL 0x1548
  231. #define RT1011_STP_OTP_TH 0x1552
  232. #define RT1011_ALC_BK_GAIN_O 0x1554
  233. #define RT1011_ALC_BK_GAIN_O_PRE 0x1556
  234. #define RT1011_SPK_DC_O_23_16 0x155a
  235. #define RT1011_SPK_DC_O_15_0 0x155c
  236. #define RT1011_INIT_RECIPROCAL_SYN_24_16 0x1560
  237. #define RT1011_INIT_RECIPROCAL_SYN_15_0 0x1562
  238. #define RT1011_STP_BQ_1_A1_L_28_16 0x1570
  239. #define RT1011_STP_BQ_1_H0_R_15_0 0x1583
  240. #define RT1011_STP_BQ_2_A1_L_28_16 0x1590
  241. #define RT1011_SPK_EXCURSION_23_16 0x15be
  242. #define RT1011_SPK_EXCURSION_15_0 0x15bf
  243. #define RT1011_SEP_MAIN_OUT_23_16 0x15c0
  244. #define RT1011_SEP_MAIN_OUT_15_0 0x15c1
  245. #define RT1011_SEP_RE_REG_15_0 0x15f9
  246. #define RT1011_DRC_CF_PARAMS_1 0x1600
  247. #define RT1011_DRC_CF_PARAMS_12 0x160b
  248. #define RT1011_ALC_DRC_HB_INTERNAL_1 0x1611
  249. #define RT1011_ALC_DRC_HB_INTERNAL_5 0x1615
  250. #define RT1011_ALC_DRC_HB_INTERNAL_6 0x1616
  251. #define RT1011_ALC_DRC_HB_INTERNAL_7 0x1617
  252. #define RT1011_ALC_DRC_BB_INTERNAL_1 0x1621
  253. #define RT1011_ALC_DRC_BB_INTERNAL_5 0x1625
  254. #define RT1011_ALC_DRC_BB_INTERNAL_6 0x1626
  255. #define RT1011_ALC_DRC_BB_INTERNAL_7 0x1627
  256. #define RT1011_ALC_DRC_POS_INTERNAL_1 0x1631
  257. #define RT1011_ALC_DRC_POS_INTERNAL_5 0x1635
  258. #define RT1011_ALC_DRC_POS_INTERNAL_6 0x1636
  259. #define RT1011_ALC_DRC_POS_INTERNAL_7 0x1637
  260. #define RT1011_ALC_DRC_POS_INTERNAL_8 0x1638
  261. #define RT1011_ALC_DRC_POS_INTERNAL_9 0x163a
  262. #define RT1011_ALC_DRC_POS_INTERNAL_10 0x163c
  263. #define RT1011_ALC_DRC_POS_INTERNAL_11 0x163e
  264. #define RT1011_BQ_1_PARAMS_CHECK_5 0x1648
  265. #define RT1011_BQ_2_PARAMS_CHECK_1 0x1650
  266. #define RT1011_BQ_2_PARAMS_CHECK_5 0x1658
  267. #define RT1011_BQ_3_PARAMS_CHECK_1 0x1660
  268. #define RT1011_BQ_3_PARAMS_CHECK_5 0x1668
  269. #define RT1011_BQ_4_PARAMS_CHECK_1 0x1670
  270. #define RT1011_BQ_4_PARAMS_CHECK_5 0x1678
  271. #define RT1011_BQ_5_PARAMS_CHECK_1 0x1680
  272. #define RT1011_BQ_5_PARAMS_CHECK_5 0x1688
  273. #define RT1011_BQ_6_PARAMS_CHECK_1 0x1690
  274. #define RT1011_BQ_6_PARAMS_CHECK_5 0x1698
  275. #define RT1011_BQ_7_PARAMS_CHECK_1 0x1700
  276. #define RT1011_BQ_7_PARAMS_CHECK_5 0x1708
  277. #define RT1011_BQ_8_PARAMS_CHECK_1 0x1710
  278. #define RT1011_BQ_8_PARAMS_CHECK_5 0x1718
  279. #define RT1011_BQ_9_PARAMS_CHECK_1 0x1720
  280. #define RT1011_BQ_9_PARAMS_CHECK_5 0x1728
  281. #define RT1011_BQ_10_PARAMS_CHECK_1 0x1730
  282. #define RT1011_BQ_10_PARAMS_CHECK_5 0x1738
  283. #define RT1011_IRQ_1 0x173a
  284. #define RT1011_PART_NUMBER_EFUSE 0x173e
  285. #define RT1011_EFUSE_CONTROL_1 0x17bb
  286. #define RT1011_EFUSE_CONTROL_2 0x17bd
  287. #define RT1011_EFUSE_MATCH_DONE 0x17cb
  288. #define RT1011_EFUSE_ADC_OFFSET_18_16 0x17e5
  289. #define RT1011_EFUSE_ADC_OFFSET_15_0 0x17e7
  290. #define RT1011_EFUSE_DAC_OFFSET_G0_20_16 0x17e9
  291. #define RT1011_EFUSE_DAC_OFFSET_G0_15_0 0x17eb
  292. #define RT1011_EFUSE_DAC_OFFSET_G1_20_16 0x17ed
  293. #define RT1011_EFUSE_DAC_OFFSET_G1_15_0 0x17ef
  294. #define RT1011_EFUSE_READ_R0_3_15_0 0x1803
  295. #define RT1011_MAX_REG 0x1803
  296. #define RT1011_REG_DISP_LEN 23
  297. /* CLOCK-2 (0x0004) */
  298. #define RT1011_FS_SYS_PRE_MASK (0x3 << 14)
  299. #define RT1011_FS_SYS_PRE_SFT 14
  300. #define RT1011_FS_SYS_PRE_MCLK (0x0 << 14)
  301. #define RT1011_FS_SYS_PRE_BCLK (0x1 << 14)
  302. #define RT1011_FS_SYS_PRE_PLL1 (0x2 << 14)
  303. #define RT1011_FS_SYS_PRE_RCCLK (0x3 << 14)
  304. #define RT1011_PLL1_SRC_MASK (0x1 << 13)
  305. #define RT1011_PLL1_SRC_SFT 13
  306. #define RT1011_PLL1_SRC_PLL2 (0x0 << 13)
  307. #define RT1011_PLL1_SRC_BCLK (0x1 << 13)
  308. #define RT1011_PLL2_SRC_MASK (0x1 << 12)
  309. #define RT1011_PLL2_SRC_SFT 12
  310. #define RT1011_PLL2_SRC_MCLK (0x0 << 12)
  311. #define RT1011_PLL2_SRC_RCCLK (0x1 << 12)
  312. #define RT1011_PLL2_SRC_DIV_MASK (0x3 << 10)
  313. #define RT1011_PLL2_SRC_DIV_SFT 10
  314. #define RT1011_SRCIN_DIV_MASK (0x3 << 8)
  315. #define RT1011_SRCIN_DIV_SFT 8
  316. #define RT1011_FS_SYS_DIV_MASK (0x7 << 4)
  317. #define RT1011_FS_SYS_DIV_SFT 4
  318. /* PLL-1 (0x000a) */
  319. #define RT1011_PLL1_QM_MASK (0xf << 12)
  320. #define RT1011_PLL1_QM_SFT 12
  321. #define RT1011_PLL1_BPM_MASK (0x1 << 11)
  322. #define RT1011_PLL1_BPM_SFT 11
  323. #define RT1011_PLL1_BPM (0x1 << 11)
  324. #define RT1011_PLL1_QN_MASK (0x1ff << 0)
  325. #define RT1011_PLL1_QN_SFT 0
  326. /* PLL-2 (0x000c) */
  327. #define RT1011_PLL2_BPK_MASK (0x1 << 5)
  328. #define RT1011_PLL2_BPK_SFT 5
  329. #define RT1011_PLL2_BPK (0x1 << 5)
  330. #define RT1011_PLL2_QK_MASK (0x1f << 0)
  331. #define RT1011_PLL2_QK_SFT 0
  332. /* Clock Detect (0x0020) */
  333. #define RT1011_EN_MCLK_DET_MASK (0x1 << 15)
  334. #define RT1011_EN_MCLK_DET_SFT 15
  335. #define RT1011_EN_MCLK_DET (0x1 << 15)
  336. /* DAC Setting-2 (0x0104) */
  337. #define RT1011_EN_CKGEN_DAC_MASK (0x1 << 13)
  338. #define RT1011_EN_CKGEN_DAC_SFT 13
  339. #define RT1011_EN_CKGEN_DAC (0x1 << 13)
  340. /* DAC Setting-3 (0x0106) */
  341. #define RT1011_DA_MUTE_EN_MASK (0x1 << 15)
  342. #define RT1011_DA_MUTE_EN_SFT 15
  343. /* ADC Setting-5 (0x0110) */
  344. #define RT1011_AD_EN_CKGEN_ADC_MASK (0x1 << 9)
  345. #define RT1011_AD_EN_CKGEN_ADC_SFT 9
  346. #define RT1011_AD_EN_CKGEN_ADC (0x1 << 9)
  347. /* TDM Total Setting (0x0111) */
  348. #define RT1011_I2S_TDM_MS_MASK (0x1 << 14)
  349. #define RT1011_I2S_TDM_MS_SFT 14
  350. #define RT1011_I2S_TDM_MS_S (0x0 << 14)
  351. #define RT1011_I2S_TDM_MS_M (0x1 << 14)
  352. #define RT1011_I2S_TX_DL_MASK (0x7 << 8)
  353. #define RT1011_I2S_TX_DL_SFT 8
  354. #define RT1011_I2S_TX_DL_16B (0x0 << 8)
  355. #define RT1011_I2S_TX_DL_20B (0x1 << 8)
  356. #define RT1011_I2S_TX_DL_24B (0x2 << 8)
  357. #define RT1011_I2S_TX_DL_32B (0x3 << 8)
  358. #define RT1011_I2S_TX_DL_8B (0x4 << 8)
  359. #define RT1011_I2S_RX_DL_MASK (0x7 << 5)
  360. #define RT1011_I2S_RX_DL_SFT 5
  361. #define RT1011_I2S_RX_DL_16B (0x0 << 5)
  362. #define RT1011_I2S_RX_DL_20B (0x1 << 5)
  363. #define RT1011_I2S_RX_DL_24B (0x2 << 5)
  364. #define RT1011_I2S_RX_DL_32B (0x3 << 5)
  365. #define RT1011_I2S_RX_DL_8B (0x4 << 5)
  366. #define RT1011_ADCDAT1_PIN_CONFIG (0x1 << 4)
  367. #define RT1011_ADCDAT1_OUTPUT (0x0 << 4)
  368. #define RT1011_ADCDAT1_INPUT (0x1 << 4)
  369. #define RT1011_ADCDAT2_PIN_CONFIG (0x1 << 3)
  370. #define RT1011_ADCDAT2_OUTPUT (0x0 << 3)
  371. #define RT1011_ADCDAT2_INPUT (0x1 << 3)
  372. #define RT1011_I2S_TDM_DF_MASK (0x7 << 0)
  373. #define RT1011_I2S_TDM_DF_SFT 0
  374. #define RT1011_I2S_TDM_DF_I2S (0x0)
  375. #define RT1011_I2S_TDM_DF_LEFT (0x1)
  376. #define RT1011_I2S_TDM_DF_PCM_A (0x2)
  377. #define RT1011_I2S_TDM_DF_PCM_B (0x3)
  378. #define RT1011_I2S_TDM_DF_PCM_A_N (0x6)
  379. #define RT1011_I2S_TDM_DF_PCM_B_N (0x7)
  380. /* TDM_tcon Setting (0x0112) */
  381. #define RT1011_TCON_DF_MASK (0x7 << 13)
  382. #define RT1011_TCON_DF_SFT 13
  383. #define RT1011_TCON_DF_I2S (0x0 << 13)
  384. #define RT1011_TCON_DF_LEFT (0x1 << 13)
  385. #define RT1011_TCON_DF_PCM_A (0x2 << 13)
  386. #define RT1011_TCON_DF_PCM_B (0x3 << 13)
  387. #define RT1011_TCON_DF_PCM_A_N (0x6 << 13)
  388. #define RT1011_TCON_DF_PCM_B_N (0x7 << 13)
  389. #define RT1011_TCON_BCLK_SEL_MASK (0x3 << 10)
  390. #define RT1011_TCON_BCLK_SEL_SFT 10
  391. #define RT1011_TCON_BCLK_SEL_32FS (0x0 << 10)
  392. #define RT1011_TCON_BCLK_SEL_64FS (0x1 << 10)
  393. #define RT1011_TCON_BCLK_SEL_128FS (0x2 << 10)
  394. #define RT1011_TCON_BCLK_SEL_256FS (0x3 << 10)
  395. #define RT1011_TCON_CH_LEN_MASK (0x3 << 5)
  396. #define RT1011_TCON_CH_LEN_SFT 5
  397. #define RT1011_TCON_CH_LEN_16B (0x0 << 5)
  398. #define RT1011_TCON_CH_LEN_20B (0x1 << 5)
  399. #define RT1011_TCON_CH_LEN_24B (0x2 << 5)
  400. #define RT1011_TCON_CH_LEN_32B (0x3 << 5)
  401. #define RT1011_TCON_BCLK_MST_MASK (0x1 << 4)
  402. #define RT1011_TCON_BCLK_MST_SFT 4
  403. #define RT1011_TCON_BCLK_MST_INV (0x1 << 4)
  404. /* TDM1 Setting-1 (0x0114) */
  405. #define RT1011_TDM_INV_BCLK_MASK (0x1 << 15)
  406. #define RT1011_TDM_INV_BCLK_SFT 15
  407. #define RT1011_TDM_INV_BCLK (0x1 << 15)
  408. #define RT1011_I2S_CH_TX_MASK (0x3 << 10)
  409. #define RT1011_I2S_CH_TX_SFT 10
  410. #define RT1011_I2S_TX_2CH (0x0 << 10)
  411. #define RT1011_I2S_TX_4CH (0x1 << 10)
  412. #define RT1011_I2S_TX_6CH (0x2 << 10)
  413. #define RT1011_I2S_TX_8CH (0x3 << 10)
  414. #define RT1011_I2S_CH_RX_MASK (0x3 << 8)
  415. #define RT1011_I2S_CH_RX_SFT 8
  416. #define RT1011_I2S_RX_2CH (0x0 << 8)
  417. #define RT1011_I2S_RX_4CH (0x1 << 8)
  418. #define RT1011_I2S_RX_6CH (0x2 << 8)
  419. #define RT1011_I2S_RX_8CH (0x3 << 8)
  420. #define RT1011_I2S_LR_CH_SEL_MASK (0x1 << 7)
  421. #define RT1011_I2S_LR_CH_SEL_SFT 7
  422. #define RT1011_I2S_LEFT_CH_SEL (0x0 << 7)
  423. #define RT1011_I2S_RIGHT_CH_SEL (0x1 << 7)
  424. #define RT1011_I2S_CH_TX_LEN_MASK (0x7 << 4)
  425. #define RT1011_I2S_CH_TX_LEN_SFT 4
  426. #define RT1011_I2S_CH_TX_LEN_16B (0x0 << 4)
  427. #define RT1011_I2S_CH_TX_LEN_20B (0x1 << 4)
  428. #define RT1011_I2S_CH_TX_LEN_24B (0x2 << 4)
  429. #define RT1011_I2S_CH_TX_LEN_32B (0x3 << 4)
  430. #define RT1011_I2S_CH_TX_LEN_8B (0x4 << 4)
  431. #define RT1011_I2S_CH_RX_LEN_MASK (0x7 << 0)
  432. #define RT1011_I2S_CH_RX_LEN_SFT 0
  433. #define RT1011_I2S_CH_RX_LEN_16B (0x0 << 0)
  434. #define RT1011_I2S_CH_RX_LEN_20B (0x1 << 0)
  435. #define RT1011_I2S_CH_RX_LEN_24B (0x2 << 0)
  436. #define RT1011_I2S_CH_RX_LEN_32B (0x3 << 0)
  437. #define RT1011_I2S_CH_RX_LEN_8B (0x4 << 0)
  438. /* TDM1 Setting-2 (0x0116) */
  439. #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK (0x7 << 13)
  440. #define RT1011_TDM_I2S_DOCK_ADCDAT_2CH (0x1 << 13)
  441. #define RT1011_TDM_I2S_DOCK_ADCDAT_4CH (0x3 << 13)
  442. #define RT1011_TDM_I2S_DOCK_ADCDAT_6CH (0x5 << 13)
  443. #define RT1011_TDM_I2S_DOCK_ADCDAT_8CH (0x7 << 13)
  444. #define RT1011_TDM_I2S_DOCK_EN_1_MASK (0x1 << 3)
  445. #define RT1011_TDM_I2S_DOCK_EN_1_SFT 3
  446. #define RT1011_TDM_I2S_DOCK_EN_1 (0x1 << 3)
  447. #define RT1011_TDM_ADCDAT1_DATA_LOCATION (0x7 << 0)
  448. /* TDM1 Setting-3 (0x0118) */
  449. #define RT1011_TDM_I2S_RX_ADC1_1_MASK (0x3 << 6)
  450. #define RT1011_TDM_I2S_RX_ADC2_1_MASK (0x3 << 4)
  451. #define RT1011_TDM_I2S_RX_ADC3_1_MASK (0x3 << 2)
  452. #define RT1011_TDM_I2S_RX_ADC4_1_MASK (0x3 << 0)
  453. #define RT1011_TDM_I2S_RX_ADC1_1_LL (0x2 << 6)
  454. #define RT1011_TDM_I2S_RX_ADC2_1_LL (0x2 << 4)
  455. #define RT1011_TDM_I2S_RX_ADC3_1_LL (0x2 << 2)
  456. #define RT1011_TDM_I2S_RX_ADC4_1_LL (0x2 << 0)
  457. /* TDM1 Setting-4 (0x011a) */
  458. #define RT1011_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12)
  459. #define RT1011_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8)
  460. #define RT1011_TDM_I2S_TX_L_DAC1_1_SFT 12
  461. #define RT1011_TDM_I2S_TX_R_DAC1_1_SFT 8
  462. /* TDM2 Setting-2 (0x0120) */
  463. #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_2_MASK (0x7 << 13)
  464. #define RT1011_TDM_I2S_DOCK_EN_2_MASK (0x1 << 3)
  465. #define RT1011_TDM_I2S_DOCK_EN_2_SFT 3
  466. #define RT1011_TDM_I2S_DOCK_EN_2 (0x1 << 3)
  467. /* MIXER 1 (0x0300) */
  468. #define RT1011_MIXER_MUTE_MIX_I_MASK (0x1 << 15)
  469. #define RT1011_MIXER_MUTE_MIX_I_SFT 15
  470. #define RT1011_MIXER_MUTE_MIX_I (0x1 << 15)
  471. #define RT1011_MIXER_MUTE_SUM_I_MASK (0x1 << 14)
  472. #define RT1011_MIXER_MUTE_SUM_I_SFT 14
  473. #define RT1011_MIXER_MUTE_SUM_I (0x1 << 14)
  474. #define RT1011_MIXER_MUTE_MIX_V_MASK (0x1 << 7)
  475. #define RT1011_MIXER_MUTE_MIX_V_SFT 7
  476. #define RT1011_MIXER_MUTE_MIX_V (0x1 << 7)
  477. #define RT1011_MIXER_MUTE_SUM_V_MASK (0x1 << 6)
  478. #define RT1011_MIXER_MUTE_SUM_V_SFT 6
  479. #define RT1011_MIXER_MUTE_SUM_V (0x1 << 6)
  480. /* Analog Temperature Sensor (0x0316) */
  481. #define RT1011_POW_TEMP_REG (0x1 << 2)
  482. #define RT1011_POW_TEMP_REG_BIT 2
  483. /* POWER-1 (0x0322) */
  484. #define RT1011_POW_LDO2 (0x1 << 15)
  485. #define RT1011_POW_LDO2_BIT 15
  486. #define RT1011_POW_DAC (0x1 << 14)
  487. #define RT1011_POW_DAC_BIT 14
  488. #define RT1011_POW_CLK12M (0x1 << 13)
  489. #define RT1011_POW_CLK12M_BIT 13
  490. #define RT1011_POW_TEMP (0x1 << 12)
  491. #define RT1011_POW_TEMP_BIT 12
  492. #define RT1011_POW_ISENSE_SPK (0x1 << 7)
  493. #define RT1011_POW_ISENSE_SPK_BIT 7
  494. #define RT1011_POW_LPF_SPK (0x1 << 6)
  495. #define RT1011_POW_LPF_SPK_BIT 6
  496. #define RT1011_POW_VSENSE_SPK (0x1 << 5)
  497. #define RT1011_POW_VSENSE_SPK_BIT 5
  498. #define RT1011_POW_TWO_BATTERY_SPK (0x1 << 4)
  499. #define RT1011_POW_TWO_BATTERY_SPK_BIT 4
  500. /* POWER-2 (0x0324) */
  501. #define RT1011_PLLEN (0x1 << 2)
  502. #define RT1011_PLLEN_BIT 2
  503. #define RT1011_POW_BG (0x1 << 1)
  504. #define RT1011_POW_BG_BIT 1
  505. #define RT1011_POW_BG_MBIAS_LV (0x1 << 0)
  506. #define RT1011_POW_BG_MBIAS_LV_BIT 0
  507. /* POWER-3 (0x0326) */
  508. #define RT1011_POW_DET_SPKVDD (0x1 << 15)
  509. #define RT1011_POW_DET_SPKVDD_BIT 15
  510. #define RT1011_POW_DET_VBAT (0x1 << 14)
  511. #define RT1011_POW_DET_VBAT_BIT 14
  512. #define RT1011_POW_FC (0x1 << 13)
  513. #define RT1011_POW_FC_BIT 13
  514. #define RT1011_POW_MBIAS_LV (0x1 << 12)
  515. #define RT1011_POW_MBIAS_LV_BIT 12
  516. #define RT1011_POW_ADC_I (0x1 << 11)
  517. #define RT1011_POW_ADC_I_BIT 11
  518. #define RT1011_POW_ADC_V (0x1 << 10)
  519. #define RT1011_POW_ADC_V_BIT 10
  520. #define RT1011_POW_ADC_T (0x1 << 9)
  521. #define RT1011_POW_ADC_T_BIT 9
  522. #define RT1011_POWD_ADC_T (0x1 << 8)
  523. #define RT1011_POWD_ADC_T_BIT 8
  524. #define RT1011_POW_MIX_I (0x1 << 7)
  525. #define RT1011_POW_MIX_I_BIT 7
  526. #define RT1011_POW_MIX_V (0x1 << 6)
  527. #define RT1011_POW_MIX_V_BIT 6
  528. #define RT1011_POW_SUM_I (0x1 << 5)
  529. #define RT1011_POW_SUM_I_BIT 5
  530. #define RT1011_POW_SUM_V (0x1 << 4)
  531. #define RT1011_POW_SUM_V_BIT 4
  532. #define RT1011_POW_MIX_T (0x1 << 2)
  533. #define RT1011_POW_MIX_T_BIT 2
  534. #define RT1011_BYPASS_MIX_T (0x1 << 1)
  535. #define RT1011_BYPASS_MIX_T_BIT 1
  536. #define RT1011_POW_VREF_LV (0x1 << 0)
  537. #define RT1011_POW_VREF_LV_BIT 0
  538. /* POWER-4 (0x0328) */
  539. #define RT1011_POW_EN_SWR (0x1 << 12)
  540. #define RT1011_POW_EN_SWR_BIT 12
  541. #define RT1011_POW_EN_PASS_BGOK_SWR (0x1 << 10)
  542. #define RT1011_POW_EN_PASS_BGOK_SWR_BIT 10
  543. #define RT1011_POW_EN_PASS_VPOK_SWR (0x1 << 9)
  544. #define RT1011_POW_EN_PASS_VPOK_SWR_BIT 9
  545. /* POWER-9 (0x032d) */
  546. #define RT1011_POW_SDB_REG_MASK (0x1 << 9)
  547. #define RT1011_POW_SDB_REG_BIT 9
  548. #define RT1011_POW_SDB_REG (0x1 << 9)
  549. #define RT1011_POW_SEL_SDB_MODE_MASK (0x1 << 6)
  550. #define RT1011_POW_SEL_SDB_MODE_BIT 6
  551. #define RT1011_POW_SEL_SDB_MODE (0x1 << 6)
  552. #define RT1011_POW_MNL_SDB_MASK (0x1 << 5)
  553. #define RT1011_POW_MNL_SDB_BIT 5
  554. #define RT1011_POW_MNL_SDB (0x1 << 5)
  555. /* SPK Protection-Temperature Protection (0x050c) */
  556. #define RT1011_STP_EN_MASK (0x1 << 15)
  557. #define RT1011_STP_EN_BIT 15
  558. #define RT1011_STP_EN (0x1 << 15)
  559. #define RT1011_STP_RS_CLB_EN_MASK (0x1 << 14)
  560. #define RT1011_STP_RS_CLB_EN_BIT 14
  561. #define RT1011_STP_RS_CLB_EN (0x1 << 14)
  562. /* SPK Protection-Temperature Protection-4 (0x0510) */
  563. #define RT1011_STP_R0_SELECT_MASK (0x3 << 6)
  564. #define RT1011_STP_R0_SELECT_EFUSE (0x0 << 6)
  565. #define RT1011_STP_R0_SELECT_START_VAL (0x1 << 6)
  566. #define RT1011_STP_R0_SELECT_REG (0x2 << 6)
  567. #define RT1011_STP_R0_SELECT_FORCE_ZERO (0x3 << 6)
  568. /* SPK Protection-Temperature Protection-6 (0x0512) */
  569. #define RT1011_STP_R0_EN_MASK (0x1 << 7)
  570. #define RT1011_STP_R0_EN_BIT 7
  571. #define RT1011_STP_R0_EN (0x1 << 7)
  572. #define RT1011_STP_T0_EN_MASK (0x1 << 6)
  573. #define RT1011_STP_T0_EN_BIT 6
  574. #define RT1011_STP_T0_EN (0x1 << 6)
  575. /* Cross Biquad Setting-1 (0x0702) */
  576. #define RT1011_MONO_LR_SEL_MASK (0x3 << 5)
  577. #define RT1011_MONO_L_CHANNEL (0x0 << 5)
  578. #define RT1011_MONO_R_CHANNEL (0x1 << 5)
  579. #define RT1011_MONO_LR_MIX_CHANNEL (0x2 << 5)
  580. /* ClassD Internal Setting-1 (0x1300) */
  581. #define RT1011_DRIVER_READY_SPK (0x1 << 12)
  582. #define RT1011_DRIVER_READY_SPK_BIT 12
  583. #define RT1011_RECV_MODE_SPK_MASK (0x1 << 5)
  584. #define RT1011_SPK_MODE (0x0 << 5)
  585. #define RT1011_RECV_MODE (0x1 << 5)
  586. #define RT1011_RECV_MODE_SPK_BIT 5
  587. /* ClassD Internal Setting-3 (0x1304) */
  588. #define RT1011_REG_GAIN_CLASSD_RI_SPK_MASK (0x7 << 12)
  589. #define RT1011_REG_GAIN_CLASSD_RI_410K (0x0 << 12)
  590. #define RT1011_REG_GAIN_CLASSD_RI_95K (0x1 << 12)
  591. #define RT1011_REG_GAIN_CLASSD_RI_82P5K (0x2 << 12)
  592. #define RT1011_REG_GAIN_CLASSD_RI_72P5K (0x3 << 12)
  593. #define RT1011_REG_GAIN_CLASSD_RI_62P5K (0x4 << 12)
  594. /* ClassD Internal Setting-8 (0x130c) */
  595. #define RT1011_TM_PORPVDD_SPK (0x1 << 1)
  596. #define RT1011_TM_PORPVDD_SPK_BIT 1
  597. /* SPK Protection-Temperature Protection-SINE_GEN_REG-1 (0x1500) */
  598. #define RT1011_STP_SIN_GEN_EN_MASK (0x1 << 13)
  599. #define RT1011_STP_SIN_GEN_EN (0x1 << 13)
  600. #define RT1011_STP_SIN_GEN_EN_BIT 13
  601. /* System Clock Source */
  602. enum {
  603. RT1011_FS_SYS_PRE_S_MCLK,
  604. RT1011_FS_SYS_PRE_S_BCLK,
  605. RT1011_FS_SYS_PRE_S_PLL1,
  606. RT1011_FS_SYS_PRE_S_RCCLK, /* 12M Hz */
  607. };
  608. /* PLL Source 1/2 */
  609. enum {
  610. RT1011_PLL1_S_BCLK,
  611. RT1011_PLL2_S_MCLK,
  612. RT1011_PLL2_S_RCCLK, /* 12M Hz */
  613. };
  614. enum {
  615. RT1011_AIF1,
  616. RT1011_AIFS
  617. };
  618. enum {
  619. RT1011_I2S_REF_NONE,
  620. RT1011_I2S_REF_LEFT_CH,
  621. RT1011_I2S_REF_RIGHT_CH,
  622. };
  623. /* BiQual & DRC related settings */
  624. #define RT1011_BQ_DRC_NUM 128
  625. struct rt1011_bq_drc_params {
  626. unsigned short val;
  627. unsigned short reg;
  628. #ifdef CONFIG_64BIT
  629. unsigned int reserved;
  630. #endif
  631. };
  632. enum {
  633. RT1011_ADVMODE_INITIAL_SET,
  634. RT1011_ADVMODE_SEP_BQ_COEFF,
  635. RT1011_ADVMODE_EQ_BQ_COEFF,
  636. RT1011_ADVMODE_BQ_UI_COEFF,
  637. RT1011_ADVMODE_SMARTBOOST_COEFF,
  638. RT1011_ADVMODE_NUM,
  639. };
  640. struct rt1011_priv {
  641. struct snd_soc_component *component;
  642. struct regmap *regmap;
  643. struct work_struct cali_work;
  644. struct rt1011_bq_drc_params **bq_drc_params;
  645. int sysclk;
  646. int sysclk_src;
  647. int lrck;
  648. int bclk;
  649. int id;
  650. int pll_src;
  651. int pll_in;
  652. int pll_out;
  653. int bq_drc_set;
  654. unsigned int r0_reg, cali_done;
  655. unsigned int r0_calib, temperature_calib;
  656. int recv_spk_mode;
  657. int i2s_ref;
  658. };
  659. #endif /* end of _RT1011_H_ */