pcm186x.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments PCM186x Universal Audio ADC
  4. *
  5. * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
  6. * Andreas Dannenberg <[email protected]>
  7. * Andrew F. Davis <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/jack.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include "pcm186x.h"
  26. static const char * const pcm186x_supply_names[] = {
  27. "avdd", /* Analog power supply. Connect to 3.3-V supply. */
  28. "dvdd", /* Digital power supply. Connect to 3.3-V supply. */
  29. "iovdd", /* I/O power supply. Connect to 3.3-V or 1.8-V. */
  30. };
  31. #define PCM186x_NUM_SUPPLIES ARRAY_SIZE(pcm186x_supply_names)
  32. struct pcm186x_priv {
  33. struct regmap *regmap;
  34. struct regulator_bulk_data supplies[PCM186x_NUM_SUPPLIES];
  35. unsigned int sysclk;
  36. unsigned int tdm_offset;
  37. bool is_tdm_mode;
  38. bool is_provider_mode;
  39. };
  40. static const DECLARE_TLV_DB_SCALE(pcm186x_pga_tlv, -1200, 50, 0);
  41. static const struct snd_kcontrol_new pcm1863_snd_controls[] = {
  42. SOC_DOUBLE_R_S_TLV("ADC Capture Volume", PCM186X_PGA_VAL_CH1_L,
  43. PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
  44. pcm186x_pga_tlv),
  45. };
  46. static const struct snd_kcontrol_new pcm1865_snd_controls[] = {
  47. SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", PCM186X_PGA_VAL_CH1_L,
  48. PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
  49. pcm186x_pga_tlv),
  50. SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", PCM186X_PGA_VAL_CH2_L,
  51. PCM186X_PGA_VAL_CH2_R, 0, -24, 80, 7, 0,
  52. pcm186x_pga_tlv),
  53. };
  54. static const unsigned int pcm186x_adc_input_channel_sel_value[] = {
  55. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  56. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  57. 0x10, 0x20, 0x30
  58. };
  59. static const char * const pcm186x_adcl_input_channel_sel_text[] = {
  60. "No Select",
  61. "VINL1[SE]", /* Default for ADC1L */
  62. "VINL2[SE]", /* Default for ADC2L */
  63. "VINL2[SE] + VINL1[SE]",
  64. "VINL3[SE]",
  65. "VINL3[SE] + VINL1[SE]",
  66. "VINL3[SE] + VINL2[SE]",
  67. "VINL3[SE] + VINL2[SE] + VINL1[SE]",
  68. "VINL4[SE]",
  69. "VINL4[SE] + VINL1[SE]",
  70. "VINL4[SE] + VINL2[SE]",
  71. "VINL4[SE] + VINL2[SE] + VINL1[SE]",
  72. "VINL4[SE] + VINL3[SE]",
  73. "VINL4[SE] + VINL3[SE] + VINL1[SE]",
  74. "VINL4[SE] + VINL3[SE] + VINL2[SE]",
  75. "VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]",
  76. "{VIN1P, VIN1M}[DIFF]",
  77. "{VIN4P, VIN4M}[DIFF]",
  78. "{VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]"
  79. };
  80. static const char * const pcm186x_adcr_input_channel_sel_text[] = {
  81. "No Select",
  82. "VINR1[SE]", /* Default for ADC1R */
  83. "VINR2[SE]", /* Default for ADC2R */
  84. "VINR2[SE] + VINR1[SE]",
  85. "VINR3[SE]",
  86. "VINR3[SE] + VINR1[SE]",
  87. "VINR3[SE] + VINR2[SE]",
  88. "VINR3[SE] + VINR2[SE] + VINR1[SE]",
  89. "VINR4[SE]",
  90. "VINR4[SE] + VINR1[SE]",
  91. "VINR4[SE] + VINR2[SE]",
  92. "VINR4[SE] + VINR2[SE] + VINR1[SE]",
  93. "VINR4[SE] + VINR3[SE]",
  94. "VINR4[SE] + VINR3[SE] + VINR1[SE]",
  95. "VINR4[SE] + VINR3[SE] + VINR2[SE]",
  96. "VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]",
  97. "{VIN2P, VIN2M}[DIFF]",
  98. "{VIN3P, VIN3M}[DIFF]",
  99. "{VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]"
  100. };
  101. static const struct soc_enum pcm186x_adc_input_channel_sel[] = {
  102. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_L, 0,
  103. PCM186X_ADC_INPUT_SEL_MASK,
  104. ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
  105. pcm186x_adcl_input_channel_sel_text,
  106. pcm186x_adc_input_channel_sel_value),
  107. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_R, 0,
  108. PCM186X_ADC_INPUT_SEL_MASK,
  109. ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
  110. pcm186x_adcr_input_channel_sel_text,
  111. pcm186x_adc_input_channel_sel_value),
  112. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_L, 0,
  113. PCM186X_ADC_INPUT_SEL_MASK,
  114. ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
  115. pcm186x_adcl_input_channel_sel_text,
  116. pcm186x_adc_input_channel_sel_value),
  117. SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_R, 0,
  118. PCM186X_ADC_INPUT_SEL_MASK,
  119. ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
  120. pcm186x_adcr_input_channel_sel_text,
  121. pcm186x_adc_input_channel_sel_value),
  122. };
  123. static const struct snd_kcontrol_new pcm186x_adc_mux_controls[] = {
  124. SOC_DAPM_ENUM("ADC1 Left Input", pcm186x_adc_input_channel_sel[0]),
  125. SOC_DAPM_ENUM("ADC1 Right Input", pcm186x_adc_input_channel_sel[1]),
  126. SOC_DAPM_ENUM("ADC2 Left Input", pcm186x_adc_input_channel_sel[2]),
  127. SOC_DAPM_ENUM("ADC2 Right Input", pcm186x_adc_input_channel_sel[3]),
  128. };
  129. static const struct snd_soc_dapm_widget pcm1863_dapm_widgets[] = {
  130. SND_SOC_DAPM_INPUT("VINL1"),
  131. SND_SOC_DAPM_INPUT("VINR1"),
  132. SND_SOC_DAPM_INPUT("VINL2"),
  133. SND_SOC_DAPM_INPUT("VINR2"),
  134. SND_SOC_DAPM_INPUT("VINL3"),
  135. SND_SOC_DAPM_INPUT("VINR3"),
  136. SND_SOC_DAPM_INPUT("VINL4"),
  137. SND_SOC_DAPM_INPUT("VINR4"),
  138. SND_SOC_DAPM_MUX("ADC Left Capture Source", SND_SOC_NOPM, 0, 0,
  139. &pcm186x_adc_mux_controls[0]),
  140. SND_SOC_DAPM_MUX("ADC Right Capture Source", SND_SOC_NOPM, 0, 0,
  141. &pcm186x_adc_mux_controls[1]),
  142. /*
  143. * Put the codec into SLEEP mode when not in use, allowing the
  144. * Energysense mechanism to operate.
  145. */
  146. SND_SOC_DAPM_ADC("ADC", "HiFi Capture", PCM186X_POWER_CTRL, 1, 1),
  147. };
  148. static const struct snd_soc_dapm_widget pcm1865_dapm_widgets[] = {
  149. SND_SOC_DAPM_INPUT("VINL1"),
  150. SND_SOC_DAPM_INPUT("VINR1"),
  151. SND_SOC_DAPM_INPUT("VINL2"),
  152. SND_SOC_DAPM_INPUT("VINR2"),
  153. SND_SOC_DAPM_INPUT("VINL3"),
  154. SND_SOC_DAPM_INPUT("VINR3"),
  155. SND_SOC_DAPM_INPUT("VINL4"),
  156. SND_SOC_DAPM_INPUT("VINR4"),
  157. SND_SOC_DAPM_MUX("ADC1 Left Capture Source", SND_SOC_NOPM, 0, 0,
  158. &pcm186x_adc_mux_controls[0]),
  159. SND_SOC_DAPM_MUX("ADC1 Right Capture Source", SND_SOC_NOPM, 0, 0,
  160. &pcm186x_adc_mux_controls[1]),
  161. SND_SOC_DAPM_MUX("ADC2 Left Capture Source", SND_SOC_NOPM, 0, 0,
  162. &pcm186x_adc_mux_controls[2]),
  163. SND_SOC_DAPM_MUX("ADC2 Right Capture Source", SND_SOC_NOPM, 0, 0,
  164. &pcm186x_adc_mux_controls[3]),
  165. /*
  166. * Put the codec into SLEEP mode when not in use, allowing the
  167. * Energysense mechanism to operate.
  168. */
  169. SND_SOC_DAPM_ADC("ADC1", "HiFi Capture 1", PCM186X_POWER_CTRL, 1, 1),
  170. SND_SOC_DAPM_ADC("ADC2", "HiFi Capture 2", PCM186X_POWER_CTRL, 1, 1),
  171. };
  172. static const struct snd_soc_dapm_route pcm1863_dapm_routes[] = {
  173. { "ADC Left Capture Source", NULL, "VINL1" },
  174. { "ADC Left Capture Source", NULL, "VINR1" },
  175. { "ADC Left Capture Source", NULL, "VINL2" },
  176. { "ADC Left Capture Source", NULL, "VINR2" },
  177. { "ADC Left Capture Source", NULL, "VINL3" },
  178. { "ADC Left Capture Source", NULL, "VINR3" },
  179. { "ADC Left Capture Source", NULL, "VINL4" },
  180. { "ADC Left Capture Source", NULL, "VINR4" },
  181. { "ADC", NULL, "ADC Left Capture Source" },
  182. { "ADC Right Capture Source", NULL, "VINL1" },
  183. { "ADC Right Capture Source", NULL, "VINR1" },
  184. { "ADC Right Capture Source", NULL, "VINL2" },
  185. { "ADC Right Capture Source", NULL, "VINR2" },
  186. { "ADC Right Capture Source", NULL, "VINL3" },
  187. { "ADC Right Capture Source", NULL, "VINR3" },
  188. { "ADC Right Capture Source", NULL, "VINL4" },
  189. { "ADC Right Capture Source", NULL, "VINR4" },
  190. { "ADC", NULL, "ADC Right Capture Source" },
  191. };
  192. static const struct snd_soc_dapm_route pcm1865_dapm_routes[] = {
  193. { "ADC1 Left Capture Source", NULL, "VINL1" },
  194. { "ADC1 Left Capture Source", NULL, "VINR1" },
  195. { "ADC1 Left Capture Source", NULL, "VINL2" },
  196. { "ADC1 Left Capture Source", NULL, "VINR2" },
  197. { "ADC1 Left Capture Source", NULL, "VINL3" },
  198. { "ADC1 Left Capture Source", NULL, "VINR3" },
  199. { "ADC1 Left Capture Source", NULL, "VINL4" },
  200. { "ADC1 Left Capture Source", NULL, "VINR4" },
  201. { "ADC1", NULL, "ADC1 Left Capture Source" },
  202. { "ADC1 Right Capture Source", NULL, "VINL1" },
  203. { "ADC1 Right Capture Source", NULL, "VINR1" },
  204. { "ADC1 Right Capture Source", NULL, "VINL2" },
  205. { "ADC1 Right Capture Source", NULL, "VINR2" },
  206. { "ADC1 Right Capture Source", NULL, "VINL3" },
  207. { "ADC1 Right Capture Source", NULL, "VINR3" },
  208. { "ADC1 Right Capture Source", NULL, "VINL4" },
  209. { "ADC1 Right Capture Source", NULL, "VINR4" },
  210. { "ADC1", NULL, "ADC1 Right Capture Source" },
  211. { "ADC2 Left Capture Source", NULL, "VINL1" },
  212. { "ADC2 Left Capture Source", NULL, "VINR1" },
  213. { "ADC2 Left Capture Source", NULL, "VINL2" },
  214. { "ADC2 Left Capture Source", NULL, "VINR2" },
  215. { "ADC2 Left Capture Source", NULL, "VINL3" },
  216. { "ADC2 Left Capture Source", NULL, "VINR3" },
  217. { "ADC2 Left Capture Source", NULL, "VINL4" },
  218. { "ADC2 Left Capture Source", NULL, "VINR4" },
  219. { "ADC2", NULL, "ADC2 Left Capture Source" },
  220. { "ADC2 Right Capture Source", NULL, "VINL1" },
  221. { "ADC2 Right Capture Source", NULL, "VINR1" },
  222. { "ADC2 Right Capture Source", NULL, "VINL2" },
  223. { "ADC2 Right Capture Source", NULL, "VINR2" },
  224. { "ADC2 Right Capture Source", NULL, "VINL3" },
  225. { "ADC2 Right Capture Source", NULL, "VINR3" },
  226. { "ADC2 Right Capture Source", NULL, "VINL4" },
  227. { "ADC2 Right Capture Source", NULL, "VINR4" },
  228. { "ADC2", NULL, "ADC2 Right Capture Source" },
  229. };
  230. static int pcm186x_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *params,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct snd_soc_component *component = dai->component;
  235. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  236. unsigned int rate = params_rate(params);
  237. snd_pcm_format_t format = params_format(params);
  238. unsigned int width = params_width(params);
  239. unsigned int channels = params_channels(params);
  240. unsigned int div_lrck;
  241. unsigned int div_bck;
  242. u8 tdm_tx_sel = 0;
  243. u8 pcm_cfg = 0;
  244. dev_dbg(component->dev, "%s() rate=%u format=0x%x width=%u channels=%u\n",
  245. __func__, rate, format, width, channels);
  246. switch (width) {
  247. case 16:
  248. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_16 <<
  249. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  250. PCM186X_PCM_CFG_TX_WLEN_16 <<
  251. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  252. break;
  253. case 20:
  254. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_20 <<
  255. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  256. PCM186X_PCM_CFG_TX_WLEN_20 <<
  257. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  258. break;
  259. case 24:
  260. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_24 <<
  261. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  262. PCM186X_PCM_CFG_TX_WLEN_24 <<
  263. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  264. break;
  265. case 32:
  266. pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_32 <<
  267. PCM186X_PCM_CFG_RX_WLEN_SHIFT |
  268. PCM186X_PCM_CFG_TX_WLEN_32 <<
  269. PCM186X_PCM_CFG_TX_WLEN_SHIFT;
  270. break;
  271. default:
  272. return -EINVAL;
  273. }
  274. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  275. PCM186X_PCM_CFG_RX_WLEN_MASK |
  276. PCM186X_PCM_CFG_TX_WLEN_MASK,
  277. pcm_cfg);
  278. div_lrck = width * channels;
  279. if (priv->is_tdm_mode) {
  280. /* Select TDM transmission data */
  281. switch (channels) {
  282. case 2:
  283. tdm_tx_sel = PCM186X_TDM_TX_SEL_2CH;
  284. break;
  285. case 4:
  286. tdm_tx_sel = PCM186X_TDM_TX_SEL_4CH;
  287. break;
  288. case 6:
  289. tdm_tx_sel = PCM186X_TDM_TX_SEL_6CH;
  290. break;
  291. default:
  292. return -EINVAL;
  293. }
  294. snd_soc_component_update_bits(component, PCM186X_TDM_TX_SEL,
  295. PCM186X_TDM_TX_SEL_MASK, tdm_tx_sel);
  296. /* In DSP/TDM mode, the LRCLK divider must be 256 */
  297. div_lrck = 256;
  298. /* Configure 1/256 duty cycle for LRCK */
  299. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  300. PCM186X_PCM_CFG_TDM_LRCK_MODE,
  301. PCM186X_PCM_CFG_TDM_LRCK_MODE);
  302. }
  303. /* Only configure clock dividers in provider mode. */
  304. if (priv->is_provider_mode) {
  305. div_bck = priv->sysclk / (div_lrck * rate);
  306. dev_dbg(component->dev,
  307. "%s() master_clk=%u div_bck=%u div_lrck=%u\n",
  308. __func__, priv->sysclk, div_bck, div_lrck);
  309. snd_soc_component_write(component, PCM186X_BCK_DIV, div_bck - 1);
  310. snd_soc_component_write(component, PCM186X_LRK_DIV, div_lrck - 1);
  311. }
  312. return 0;
  313. }
  314. static int pcm186x_set_fmt(struct snd_soc_dai *dai, unsigned int format)
  315. {
  316. struct snd_soc_component *component = dai->component;
  317. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  318. u8 clk_ctrl = 0;
  319. u8 pcm_cfg = 0;
  320. dev_dbg(component->dev, "%s() format=0x%x\n", __func__, format);
  321. switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  322. case SND_SOC_DAIFMT_CBP_CFP:
  323. if (!priv->sysclk) {
  324. dev_err(component->dev, "operating in provider mode requires sysclock to be configured\n");
  325. return -EINVAL;
  326. }
  327. clk_ctrl |= PCM186X_CLK_CTRL_MST_MODE;
  328. priv->is_provider_mode = true;
  329. break;
  330. case SND_SOC_DAIFMT_CBC_CFC:
  331. priv->is_provider_mode = false;
  332. break;
  333. default:
  334. dev_err(component->dev, "Invalid DAI master/slave interface\n");
  335. return -EINVAL;
  336. }
  337. /* set interface polarity */
  338. switch (format & SND_SOC_DAIFMT_INV_MASK) {
  339. case SND_SOC_DAIFMT_NB_NF:
  340. break;
  341. default:
  342. dev_err(component->dev, "Inverted DAI clocks not supported\n");
  343. return -EINVAL;
  344. }
  345. /* set interface format */
  346. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  347. case SND_SOC_DAIFMT_I2S:
  348. pcm_cfg = PCM186X_PCM_CFG_FMT_I2S;
  349. break;
  350. case SND_SOC_DAIFMT_LEFT_J:
  351. pcm_cfg = PCM186X_PCM_CFG_FMT_LEFTJ;
  352. break;
  353. case SND_SOC_DAIFMT_DSP_A:
  354. priv->tdm_offset += 1;
  355. fallthrough;
  356. /* DSP_A uses the same basic config as DSP_B
  357. * except we need to shift the TDM output by one BCK cycle
  358. */
  359. case SND_SOC_DAIFMT_DSP_B:
  360. priv->is_tdm_mode = true;
  361. pcm_cfg = PCM186X_PCM_CFG_FMT_TDM;
  362. break;
  363. default:
  364. dev_err(component->dev, "Invalid DAI format\n");
  365. return -EINVAL;
  366. }
  367. snd_soc_component_update_bits(component, PCM186X_CLK_CTRL,
  368. PCM186X_CLK_CTRL_MST_MODE, clk_ctrl);
  369. snd_soc_component_write(component, PCM186X_TDM_TX_OFFSET, priv->tdm_offset);
  370. snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
  371. PCM186X_PCM_CFG_FMT_MASK, pcm_cfg);
  372. return 0;
  373. }
  374. static int pcm186x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  375. unsigned int rx_mask, int slots, int slot_width)
  376. {
  377. struct snd_soc_component *component = dai->component;
  378. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  379. unsigned int first_slot, last_slot, tdm_offset;
  380. dev_dbg(component->dev,
  381. "%s() tx_mask=0x%x rx_mask=0x%x slots=%d slot_width=%d\n",
  382. __func__, tx_mask, rx_mask, slots, slot_width);
  383. if (!tx_mask) {
  384. dev_err(component->dev, "tdm tx mask must not be 0\n");
  385. return -EINVAL;
  386. }
  387. first_slot = __ffs(tx_mask);
  388. last_slot = __fls(tx_mask);
  389. if (last_slot - first_slot != hweight32(tx_mask) - 1) {
  390. dev_err(component->dev, "tdm tx mask must be contiguous\n");
  391. return -EINVAL;
  392. }
  393. tdm_offset = first_slot * slot_width;
  394. if (tdm_offset > 255) {
  395. dev_err(component->dev, "tdm tx slot selection out of bounds\n");
  396. return -EINVAL;
  397. }
  398. priv->tdm_offset = tdm_offset;
  399. return 0;
  400. }
  401. static int pcm186x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  402. unsigned int freq, int dir)
  403. {
  404. struct snd_soc_component *component = dai->component;
  405. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  406. dev_dbg(component->dev, "%s() clk_id=%d freq=%u dir=%d\n",
  407. __func__, clk_id, freq, dir);
  408. priv->sysclk = freq;
  409. return 0;
  410. }
  411. static const struct snd_soc_dai_ops pcm186x_dai_ops = {
  412. .set_sysclk = pcm186x_set_dai_sysclk,
  413. .set_tdm_slot = pcm186x_set_tdm_slot,
  414. .set_fmt = pcm186x_set_fmt,
  415. .hw_params = pcm186x_hw_params,
  416. };
  417. static struct snd_soc_dai_driver pcm1863_dai = {
  418. .name = "pcm1863-aif",
  419. .capture = {
  420. .stream_name = "Capture",
  421. .channels_min = 1,
  422. .channels_max = 2,
  423. .rates = PCM186X_RATES,
  424. .formats = PCM186X_FORMATS,
  425. },
  426. .ops = &pcm186x_dai_ops,
  427. };
  428. static struct snd_soc_dai_driver pcm1865_dai = {
  429. .name = "pcm1865-aif",
  430. .capture = {
  431. .stream_name = "Capture",
  432. .channels_min = 1,
  433. .channels_max = 4,
  434. .rates = PCM186X_RATES,
  435. .formats = PCM186X_FORMATS,
  436. },
  437. .ops = &pcm186x_dai_ops,
  438. };
  439. static int pcm186x_power_on(struct snd_soc_component *component)
  440. {
  441. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  442. int ret = 0;
  443. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  444. priv->supplies);
  445. if (ret)
  446. return ret;
  447. regcache_cache_only(priv->regmap, false);
  448. ret = regcache_sync(priv->regmap);
  449. if (ret) {
  450. dev_err(component->dev, "Failed to restore cache\n");
  451. regcache_cache_only(priv->regmap, true);
  452. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  453. priv->supplies);
  454. return ret;
  455. }
  456. snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
  457. PCM186X_PWR_CTRL_PWRDN, 0);
  458. return 0;
  459. }
  460. static int pcm186x_power_off(struct snd_soc_component *component)
  461. {
  462. struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
  463. snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
  464. PCM186X_PWR_CTRL_PWRDN, PCM186X_PWR_CTRL_PWRDN);
  465. regcache_cache_only(priv->regmap, true);
  466. return regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  467. priv->supplies);
  468. }
  469. static int pcm186x_set_bias_level(struct snd_soc_component *component,
  470. enum snd_soc_bias_level level)
  471. {
  472. dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
  473. snd_soc_component_get_bias_level(component), level);
  474. switch (level) {
  475. case SND_SOC_BIAS_ON:
  476. break;
  477. case SND_SOC_BIAS_PREPARE:
  478. break;
  479. case SND_SOC_BIAS_STANDBY:
  480. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  481. pcm186x_power_on(component);
  482. break;
  483. case SND_SOC_BIAS_OFF:
  484. pcm186x_power_off(component);
  485. break;
  486. }
  487. return 0;
  488. }
  489. static struct snd_soc_component_driver soc_codec_dev_pcm1863 = {
  490. .set_bias_level = pcm186x_set_bias_level,
  491. .controls = pcm1863_snd_controls,
  492. .num_controls = ARRAY_SIZE(pcm1863_snd_controls),
  493. .dapm_widgets = pcm1863_dapm_widgets,
  494. .num_dapm_widgets = ARRAY_SIZE(pcm1863_dapm_widgets),
  495. .dapm_routes = pcm1863_dapm_routes,
  496. .num_dapm_routes = ARRAY_SIZE(pcm1863_dapm_routes),
  497. .idle_bias_on = 1,
  498. .use_pmdown_time = 1,
  499. .endianness = 1,
  500. };
  501. static struct snd_soc_component_driver soc_codec_dev_pcm1865 = {
  502. .set_bias_level = pcm186x_set_bias_level,
  503. .controls = pcm1865_snd_controls,
  504. .num_controls = ARRAY_SIZE(pcm1865_snd_controls),
  505. .dapm_widgets = pcm1865_dapm_widgets,
  506. .num_dapm_widgets = ARRAY_SIZE(pcm1865_dapm_widgets),
  507. .dapm_routes = pcm1865_dapm_routes,
  508. .num_dapm_routes = ARRAY_SIZE(pcm1865_dapm_routes),
  509. .suspend_bias_off = 1,
  510. .idle_bias_on = 1,
  511. .use_pmdown_time = 1,
  512. .endianness = 1,
  513. };
  514. static bool pcm186x_volatile(struct device *dev, unsigned int reg)
  515. {
  516. switch (reg) {
  517. case PCM186X_PAGE:
  518. case PCM186X_DEVICE_STATUS:
  519. case PCM186X_FSAMPLE_STATUS:
  520. case PCM186X_DIV_STATUS:
  521. case PCM186X_CLK_STATUS:
  522. case PCM186X_SUPPLY_STATUS:
  523. case PCM186X_MMAP_STAT_CTRL:
  524. case PCM186X_MMAP_ADDRESS:
  525. return true;
  526. }
  527. return false;
  528. }
  529. static const struct regmap_range_cfg pcm186x_range = {
  530. .name = "Pages",
  531. .range_max = PCM186X_MAX_REGISTER,
  532. .selector_reg = PCM186X_PAGE,
  533. .selector_mask = 0xff,
  534. .window_len = PCM186X_PAGE_LEN,
  535. };
  536. const struct regmap_config pcm186x_regmap = {
  537. .reg_bits = 8,
  538. .val_bits = 8,
  539. .volatile_reg = pcm186x_volatile,
  540. .ranges = &pcm186x_range,
  541. .num_ranges = 1,
  542. .max_register = PCM186X_MAX_REGISTER,
  543. .cache_type = REGCACHE_RBTREE,
  544. };
  545. EXPORT_SYMBOL_GPL(pcm186x_regmap);
  546. int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq,
  547. struct regmap *regmap)
  548. {
  549. struct pcm186x_priv *priv;
  550. int i, ret;
  551. priv = devm_kzalloc(dev, sizeof(struct pcm186x_priv), GFP_KERNEL);
  552. if (!priv)
  553. return -ENOMEM;
  554. dev_set_drvdata(dev, priv);
  555. priv->regmap = regmap;
  556. for (i = 0; i < ARRAY_SIZE(priv->supplies); i++)
  557. priv->supplies[i].supply = pcm186x_supply_names[i];
  558. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
  559. priv->supplies);
  560. if (ret) {
  561. dev_err(dev, "failed to request supplies: %d\n", ret);
  562. return ret;
  563. }
  564. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  565. priv->supplies);
  566. if (ret) {
  567. dev_err(dev, "failed enable supplies: %d\n", ret);
  568. return ret;
  569. }
  570. /* Reset device registers for a consistent power-on like state */
  571. ret = regmap_write(regmap, PCM186X_PAGE, PCM186X_RESET);
  572. if (ret) {
  573. dev_err(dev, "failed to write device: %d\n", ret);
  574. return ret;
  575. }
  576. ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  577. priv->supplies);
  578. if (ret) {
  579. dev_err(dev, "failed disable supplies: %d\n", ret);
  580. return ret;
  581. }
  582. switch (type) {
  583. case PCM1865:
  584. case PCM1864:
  585. ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1865,
  586. &pcm1865_dai, 1);
  587. break;
  588. case PCM1863:
  589. case PCM1862:
  590. default:
  591. ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1863,
  592. &pcm1863_dai, 1);
  593. }
  594. if (ret) {
  595. dev_err(dev, "failed to register CODEC: %d\n", ret);
  596. return ret;
  597. }
  598. return 0;
  599. }
  600. EXPORT_SYMBOL_GPL(pcm186x_probe);
  601. MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
  602. MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
  603. MODULE_DESCRIPTION("PCM186x Universal Audio ADC driver");
  604. MODULE_LICENSE("GPL v2");