nau8824.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * NAU88L24 ALSA SoC audio driver
  4. *
  5. * Copyright 2016 Nuvoton Technology Corp.
  6. * Author: John Hsu <[email protected]>
  7. */
  8. #ifndef __NAU8824_H__
  9. #define __NAU8824_H__
  10. #define NAU8824_REG_RESET 0x00
  11. #define NAU8824_REG_ENA_CTRL 0x01
  12. #define NAU8824_REG_CLK_GATING_ENA 0x02
  13. #define NAU8824_REG_CLK_DIVIDER 0x03
  14. #define NAU8824_REG_FLL1 0x04
  15. #define NAU8824_REG_FLL2 0x05
  16. #define NAU8824_REG_FLL3 0x06
  17. #define NAU8824_REG_FLL4 0x07
  18. #define NAU8824_REG_FLL5 0x08
  19. #define NAU8824_REG_FLL6 0x09
  20. #define NAU8824_REG_FLL_VCO_RSV 0x0A
  21. #define NAU8824_REG_JACK_DET_CTRL 0x0D
  22. #define NAU8824_REG_INTERRUPT_SETTING_1 0x0F
  23. #define NAU8824_REG_IRQ 0x10
  24. #define NAU8824_REG_CLEAR_INT_REG 0x11
  25. #define NAU8824_REG_INTERRUPT_SETTING 0x12
  26. #define NAU8824_REG_SAR_ADC 0x13
  27. #define NAU8824_REG_VDET_COEFFICIENT 0x14
  28. #define NAU8824_REG_VDET_THRESHOLD_1 0x15
  29. #define NAU8824_REG_VDET_THRESHOLD_2 0x16
  30. #define NAU8824_REG_VDET_THRESHOLD_3 0x17
  31. #define NAU8824_REG_VDET_THRESHOLD_4 0x18
  32. #define NAU8824_REG_GPIO_SEL 0x1A
  33. #define NAU8824_REG_PORT0_I2S_PCM_CTRL_1 0x1C
  34. #define NAU8824_REG_PORT0_I2S_PCM_CTRL_2 0x1D
  35. #define NAU8824_REG_PORT0_LEFT_TIME_SLOT 0x1E
  36. #define NAU8824_REG_PORT0_RIGHT_TIME_SLOT 0x1F
  37. #define NAU8824_REG_TDM_CTRL 0x20
  38. #define NAU8824_REG_ADC_HPF_FILTER 0x23
  39. #define NAU8824_REG_ADC_FILTER_CTRL 0x24
  40. #define NAU8824_REG_DAC_FILTER_CTRL_1 0x25
  41. #define NAU8824_REG_DAC_FILTER_CTRL_2 0x26
  42. #define NAU8824_REG_NOTCH_FILTER_1 0x27
  43. #define NAU8824_REG_NOTCH_FILTER_2 0x28
  44. #define NAU8824_REG_EQ1_LOW 0x29
  45. #define NAU8824_REG_EQ2_EQ3 0x2A
  46. #define NAU8824_REG_EQ4_EQ5 0x2B
  47. #define NAU8824_REG_ADC_CH0_DGAIN_CTRL 0x2D
  48. #define NAU8824_REG_ADC_CH1_DGAIN_CTRL 0x2E
  49. #define NAU8824_REG_ADC_CH2_DGAIN_CTRL 0x2F
  50. #define NAU8824_REG_ADC_CH3_DGAIN_CTRL 0x30
  51. #define NAU8824_REG_DAC_MUTE_CTRL 0x31
  52. #define NAU8824_REG_DAC_CH0_DGAIN_CTRL 0x32
  53. #define NAU8824_REG_DAC_CH1_DGAIN_CTRL 0x33
  54. #define NAU8824_REG_ADC_TO_DAC_ST 0x34
  55. #define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 0x38
  56. #define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01 0x39
  57. #define NAU8824_REG_DRC_SLOPE_ADC_CH01 0x3A
  58. #define NAU8824_REG_DRC_ATKDCY_ADC_CH01 0x3B
  59. #define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23 0x3C
  60. #define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23 0x3D
  61. #define NAU8824_REG_DRC_SLOPE_ADC_CH23 0x3E
  62. #define NAU8824_REG_DRC_ATKDCY_ADC_CH23 0x3F
  63. #define NAU8824_REG_DRC_GAINL_ADC0 0x40
  64. #define NAU8824_REG_DRC_GAINL_ADC1 0x41
  65. #define NAU8824_REG_DRC_GAINL_ADC2 0x42
  66. #define NAU8824_REG_DRC_GAINL_ADC3 0x43
  67. #define NAU8824_REG_DRC_KNEE_IP12_DAC 0x45
  68. #define NAU8824_REG_DRC_KNEE_IP34_DAC 0x46
  69. #define NAU8824_REG_DRC_SLOPE_DAC 0x47
  70. #define NAU8824_REG_DRC_ATKDCY_DAC 0x48
  71. #define NAU8824_REG_DRC_GAIN_DAC_CH0 0x49
  72. #define NAU8824_REG_DRC_GAIN_DAC_CH1 0x4A
  73. #define NAU8824_REG_MODE 0x4C
  74. #define NAU8824_REG_MODE1 0x4D
  75. #define NAU8824_REG_MODE2 0x4E
  76. #define NAU8824_REG_CLASSG 0x50
  77. #define NAU8824_REG_OTP_EFUSE 0x51
  78. #define NAU8824_REG_OTPDOUT_1 0x53
  79. #define NAU8824_REG_OTPDOUT_2 0x54
  80. #define NAU8824_REG_MISC_CTRL 0x55
  81. #define NAU8824_REG_I2C_TIMEOUT 0x56
  82. #define NAU8824_REG_TEST_MODE 0x57
  83. #define NAU8824_REG_I2C_DEVICE_ID 0x58
  84. #define NAU8824_REG_SAR_ADC_DATA_OUT 0x59
  85. #define NAU8824_REG_BIAS_ADJ 0x66
  86. #define NAU8824_REG_PGA_GAIN 0x67
  87. #define NAU8824_REG_TRIM_SETTINGS 0x68
  88. #define NAU8824_REG_ANALOG_CONTROL_1 0x69
  89. #define NAU8824_REG_ANALOG_CONTROL_2 0x6A
  90. #define NAU8824_REG_ENABLE_LO 0x6B
  91. #define NAU8824_REG_GAIN_LO 0x6C
  92. #define NAU8824_REG_CLASSD_GAIN_1 0x6D
  93. #define NAU8824_REG_CLASSD_GAIN_2 0x6E
  94. #define NAU8824_REG_ANALOG_ADC_1 0x71
  95. #define NAU8824_REG_ANALOG_ADC_2 0x72
  96. #define NAU8824_REG_RDAC 0x73
  97. #define NAU8824_REG_MIC_BIAS 0x74
  98. #define NAU8824_REG_HS_VOLUME_CONTROL 0x75
  99. #define NAU8824_REG_BOOST 0x76
  100. #define NAU8824_REG_FEPGA 0x77
  101. #define NAU8824_REG_FEPGA_II 0x78
  102. #define NAU8824_REG_FEPGA_SE 0x79
  103. #define NAU8824_REG_FEPGA_ATTENUATION 0x7A
  104. #define NAU8824_REG_ATT_PORT0 0x7B
  105. #define NAU8824_REG_ATT_PORT1 0x7C
  106. #define NAU8824_REG_POWER_UP_CONTROL 0x7F
  107. #define NAU8824_REG_CHARGE_PUMP_CONTROL 0x80
  108. #define NAU8824_REG_CHARGE_PUMP_INPUT 0x81
  109. #define NAU8824_REG_MAX NAU8824_REG_CHARGE_PUMP_INPUT
  110. /* 16-bit control register address, and 16-bits control register data */
  111. #define NAU8824_REG_ADDR_LEN 16
  112. #define NAU8824_REG_DATA_LEN 16
  113. /* ENA_CTRL (0x1) */
  114. #define NAU8824_DMIC_LCH_EDGE_CH23 (0x1 << 12)
  115. #define NAU8824_DMIC_LCH_EDGE_CH01 (0x1 << 11)
  116. #define NAU8824_JD_SLEEP_MODE (0x1 << 10)
  117. #define NAU8824_ADC_CH3_DMIC_SFT 9
  118. #define NAU8824_ADC_CH3_DMIC_EN (0x1 << NAU8824_ADC_CH3_DMIC_SFT)
  119. #define NAU8824_ADC_CH2_DMIC_SFT 8
  120. #define NAU8824_ADC_CH2_DMIC_EN (0x1 << NAU8824_ADC_CH2_DMIC_SFT)
  121. #define NAU8824_ADC_CH1_DMIC_SFT 7
  122. #define NAU8824_ADC_CH1_DMIC_EN (0x1 << NAU8824_ADC_CH1_DMIC_SFT)
  123. #define NAU8824_ADC_CH0_DMIC_SFT 6
  124. #define NAU8824_ADC_CH0_DMIC_EN (0x1 << NAU8824_ADC_CH0_DMIC_SFT)
  125. #define NAU8824_DAC_CH1_EN (0x1 << 5)
  126. #define NAU8824_DAC_CH0_EN (0x1 << 4)
  127. #define NAU8824_ADC_CH3_EN (0x1 << 3)
  128. #define NAU8824_ADC_CH2_EN (0x1 << 2)
  129. #define NAU8824_ADC_CH1_EN (0x1 << 1)
  130. #define NAU8824_ADC_CH0_EN 0x1
  131. /* CLK_GATING_ENA (0x02) */
  132. #define NAU8824_CLK_ADC_CH23_EN (0x1 << 15)
  133. #define NAU8824_CLK_ADC_CH01_EN (0x1 << 14)
  134. #define NAU8824_CLK_DAC_CH1_EN (0x1 << 13)
  135. #define NAU8824_CLK_DAC_CH0_EN (0x1 << 12)
  136. #define NAU8824_CLK_I2S_EN (0x1 << 7)
  137. #define NAU8824_CLK_GAIN_EN (0x1 << 5)
  138. #define NAU8824_CLK_SAR_EN (0x1 << 3)
  139. #define NAU8824_CLK_DMIC_CH23_EN (0x1 << 1)
  140. /* CLK_DIVIDER (0x3) */
  141. #define NAU8824_CLK_SRC_SFT 15
  142. #define NAU8824_CLK_SRC_MASK (1 << NAU8824_CLK_SRC_SFT)
  143. #define NAU8824_CLK_SRC_VCO (1 << NAU8824_CLK_SRC_SFT)
  144. #define NAU8824_CLK_SRC_MCLK (0 << NAU8824_CLK_SRC_SFT)
  145. #define NAU8824_CLK_MCLK_SRC_MASK (0xf << 0)
  146. #define NAU8824_CLK_DMIC_SRC_SFT 10
  147. #define NAU8824_CLK_DMIC_SRC_MASK (0x7 << NAU8824_CLK_DMIC_SRC_SFT)
  148. #define NAU8824_CLK_ADC_SRC_SFT 6
  149. #define NAU8824_CLK_ADC_SRC_MASK (0x3 << NAU8824_CLK_ADC_SRC_SFT)
  150. #define NAU8824_CLK_DAC_SRC_SFT 4
  151. #define NAU8824_CLK_DAC_SRC_MASK (0x3 << NAU8824_CLK_DAC_SRC_SFT)
  152. /* FLL1 (0x04) */
  153. #define NAU8824_FLL_RATIO_MASK (0x7f << 0)
  154. /* FLL3 (0x06) */
  155. #define NAU8824_FLL_INTEGER_MASK (0x3ff << 0)
  156. #define NAU8824_FLL_CLK_SRC_SFT 10
  157. #define NAU8824_FLL_CLK_SRC_MASK (0x3 << NAU8824_FLL_CLK_SRC_SFT)
  158. #define NAU8824_FLL_CLK_SRC_MCLK (0 << NAU8824_FLL_CLK_SRC_SFT)
  159. #define NAU8824_FLL_CLK_SRC_BLK (0x2 << NAU8824_FLL_CLK_SRC_SFT)
  160. #define NAU8824_FLL_CLK_SRC_FS (0x3 << NAU8824_FLL_CLK_SRC_SFT)
  161. /* FLL4 (0x07) */
  162. #define NAU8824_FLL_REF_DIV_SFT 10
  163. #define NAU8824_FLL_REF_DIV_MASK (0x3 << NAU8824_FLL_REF_DIV_SFT)
  164. /* FLL5 (0x08) */
  165. #define NAU8824_FLL_PDB_DAC_EN (0x1 << 15)
  166. #define NAU8824_FLL_LOOP_FTR_EN (0x1 << 14)
  167. #define NAU8824_FLL_CLK_SW_MASK (0x1 << 13)
  168. #define NAU8824_FLL_CLK_SW_N2 (0x1 << 13)
  169. #define NAU8824_FLL_CLK_SW_REF (0x0 << 13)
  170. #define NAU8824_FLL_FTR_SW_MASK (0x1 << 12)
  171. #define NAU8824_FLL_FTR_SW_ACCU (0x1 << 12)
  172. #define NAU8824_FLL_FTR_SW_FILTER (0x0 << 12)
  173. /* FLL6 (0x9) */
  174. #define NAU8824_DCO_EN (0x1 << 15)
  175. #define NAU8824_SDM_EN (0x1 << 14)
  176. /* IRQ (0x10) */
  177. #define NAU8824_SHORT_CIRCUIT_IRQ (0x1 << 7)
  178. #define NAU8824_IMPEDANCE_MEAS_IRQ (0x1 << 6)
  179. #define NAU8824_KEY_RELEASE_IRQ (0x1 << 5)
  180. #define NAU8824_KEY_LONG_PRESS_IRQ (0x1 << 4)
  181. #define NAU8824_KEY_SHORT_PRESS_IRQ (0x1 << 3)
  182. #define NAU8824_JACK_EJECTION_DETECTED (0x1 << 1)
  183. #define NAU8824_JACK_INSERTION_DETECTED 0x1
  184. /* JACK_DET_CTRL (0x0D) */
  185. #define NAU8824_JACK_EJECT_DT_SFT 2
  186. #define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT)
  187. #define NAU8824_JACK_LOGIC (0x1 << 1)
  188. /* INTERRUPT_SETTING_1 (0x0F) */
  189. #define NAU8824_IRQ_EJECT_EN (0x1 << 9)
  190. #define NAU8824_IRQ_INSERT_EN (0x1 << 8)
  191. /* INTERRUPT_SETTING (0x12) */
  192. #define NAU8824_IRQ_KEY_RELEASE_DIS (0x1 << 5)
  193. #define NAU8824_IRQ_KEY_SHORT_PRESS_DIS (0x1 << 3)
  194. #define NAU8824_IRQ_EJECT_DIS (0x1 << 1)
  195. #define NAU8824_IRQ_INSERT_DIS 0x1
  196. /* SAR_ADC (0x13) */
  197. #define NAU8824_SAR_ADC_EN_SFT 12
  198. #define NAU8824_SAR_TRACKING_GAIN_SFT 8
  199. #define NAU8824_SAR_TRACKING_GAIN_MASK (0x7 << NAU8824_SAR_TRACKING_GAIN_SFT)
  200. #define NAU8824_SAR_COMPARE_TIME_SFT 2
  201. #define NAU8824_SAR_COMPARE_TIME_MASK (3 << 2)
  202. #define NAU8824_SAR_SAMPLING_TIME_SFT 0
  203. #define NAU8824_SAR_SAMPLING_TIME_MASK (3 << 0)
  204. /* VDET_COEFFICIENT (0x14) */
  205. #define NAU8824_SHORTKEY_DEBOUNCE_SFT 12
  206. #define NAU8824_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT)
  207. #define NAU8824_LEVELS_NR_SFT 8
  208. #define NAU8824_LEVELS_NR_MASK (0x7 << 8)
  209. #define NAU8824_HYSTERESIS_SFT 0
  210. #define NAU8824_HYSTERESIS_MASK 0xf
  211. /* PORT0_I2S_PCM_CTRL_1 (0x1C) */
  212. #define NAU8824_I2S_BP_SFT 7
  213. #define NAU8824_I2S_BP_MASK (1 << NAU8824_I2S_BP_SFT)
  214. #define NAU8824_I2S_BP_INV (1 << NAU8824_I2S_BP_SFT)
  215. #define NAU8824_I2S_PCMB_SFT 6
  216. #define NAU8824_I2S_PCMB_EN (1 << NAU8824_I2S_PCMB_SFT)
  217. #define NAU8824_I2S_DL_SFT 2
  218. #define NAU8824_I2S_DL_MASK (0x3 << NAU8824_I2S_DL_SFT)
  219. #define NAU8824_I2S_DL_16 (0 << NAU8824_I2S_DL_SFT)
  220. #define NAU8824_I2S_DL_20 (1 << NAU8824_I2S_DL_SFT)
  221. #define NAU8824_I2S_DL_24 (2 << NAU8824_I2S_DL_SFT)
  222. #define NAU8824_I2S_DL_32 (3 << NAU8824_I2S_DL_SFT)
  223. #define NAU8824_I2S_DF_MASK 0x3
  224. #define NAU8824_I2S_DF_RIGTH 0
  225. #define NAU8824_I2S_DF_LEFT 1
  226. #define NAU8824_I2S_DF_I2S 2
  227. #define NAU8824_I2S_DF_PCM_AB 3
  228. /* PORT0_I2S_PCM_CTRL_2 (0x1D) */
  229. #define NAU8824_I2S_LRC_DIV_SFT 12
  230. #define NAU8824_I2S_LRC_DIV_MASK (0x3 << NAU8824_I2S_LRC_DIV_SFT)
  231. #define NAU8824_I2S_MS_SFT 3
  232. #define NAU8824_I2S_MS_MASK (1 << NAU8824_I2S_MS_SFT)
  233. #define NAU8824_I2S_MS_MASTER (1 << NAU8824_I2S_MS_SFT)
  234. #define NAU8824_I2S_MS_SLAVE (0 << NAU8824_I2S_MS_SFT)
  235. #define NAU8824_I2S_BLK_DIV_MASK 0x7
  236. /* PORT0_LEFT_TIME_SLOT (0x1E) */
  237. #define NAU8824_TSLOT_L_MASK 0x3ff
  238. /* TDM_CTRL (0x20) */
  239. #define NAU8824_TDM_MODE (0x1 << 15)
  240. #define NAU8824_TDM_OFFSET_EN (0x1 << 14)
  241. #define NAU8824_TDM_DACL_RX_SFT 6
  242. #define NAU8824_TDM_DACL_RX_MASK (0x3 << NAU8824_TDM_DACL_RX_SFT)
  243. #define NAU8824_TDM_DACR_RX_SFT 4
  244. #define NAU8824_TDM_DACR_RX_MASK (0x3 << NAU8824_TDM_DACR_RX_SFT)
  245. #define NAU8824_TDM_TX_MASK 0xf
  246. /* ADC_FILTER_CTRL (0x24) */
  247. #define NAU8824_ADC_SYNC_DOWN_MASK 0x3
  248. #define NAU8824_ADC_SYNC_DOWN_32 0
  249. #define NAU8824_ADC_SYNC_DOWN_64 1
  250. #define NAU8824_ADC_SYNC_DOWN_128 2
  251. #define NAU8824_ADC_SYNC_DOWN_256 3
  252. /* DAC_FILTER_CTRL_1 (0x25) */
  253. #define NAU8824_DAC_CICCLP_OFF (0x1 << 7)
  254. #define NAU8824_DAC_OVERSAMPLE_MASK 0x7
  255. #define NAU8824_DAC_OVERSAMPLE_64 0
  256. #define NAU8824_DAC_OVERSAMPLE_256 1
  257. #define NAU8824_DAC_OVERSAMPLE_128 2
  258. #define NAU8824_DAC_OVERSAMPLE_32 4
  259. /* DAC_MUTE_CTRL (0x31) */
  260. #define NAU8824_DAC_CH01_MIX 0x3
  261. #define NAU8824_DAC_ZC_EN (0x1 << 11)
  262. /* DAC_CH0_DGAIN_CTRL (0x32) */
  263. #define NAU8824_DAC_CH0_SEL_SFT 9
  264. #define NAU8824_DAC_CH0_SEL_MASK (0x1 << NAU8824_DAC_CH0_SEL_SFT)
  265. #define NAU8824_DAC_CH0_SEL_I2S0 (0x0 << NAU8824_DAC_CH0_SEL_SFT)
  266. #define NAU8824_DAC_CH0_SEL_I2S1 (0x1 << NAU8824_DAC_CH0_SEL_SFT)
  267. #define NAU8824_DAC_CH0_VOL_MASK 0x1ff
  268. /* DAC_CH1_DGAIN_CTRL (0x33) */
  269. #define NAU8824_DAC_CH1_SEL_SFT 9
  270. #define NAU8824_DAC_CH1_SEL_MASK (0x1 << NAU8824_DAC_CH1_SEL_SFT)
  271. #define NAU8824_DAC_CH1_SEL_I2S0 (0x0 << NAU8824_DAC_CH1_SEL_SFT)
  272. #define NAU8824_DAC_CH1_SEL_I2S1 (0x1 << NAU8824_DAC_CH1_SEL_SFT)
  273. #define NAU8824_DAC_CH1_VOL_MASK 0x1ff
  274. /* CLASSG (0x50) */
  275. #define NAU8824_CLASSG_TIMER_SFT 8
  276. #define NAU8824_CLASSG_TIMER_MASK (0x3f << NAU8824_CLASSG_TIMER_SFT)
  277. #define NAU8824_CLASSG_LDAC_EN_SFT 2
  278. #define NAU8824_CLASSG_RDAC_EN_SFT 1
  279. #define NAU8824_CLASSG_EN_SFT 0
  280. /* SAR_ADC_DATA_OUT (0x59) */
  281. #define NAU8824_SAR_ADC_DATA_MASK 0xff
  282. /* BIAS_ADJ (0x66) */
  283. #define NAU8824_VMID (1 << 6)
  284. #define NAU8824_VMID_SEL_SFT 4
  285. #define NAU8824_VMID_SEL_MASK (3 << NAU8824_VMID_SEL_SFT)
  286. #define NAU8824_DMIC2_EN_SFT 3
  287. #define NAU8824_DMIC1_EN_SFT 2
  288. /* TRIM_SETTINGS (0x68) */
  289. #define NAU8824_DRV_CURR_INC (1 << 15)
  290. /* ANALOG_CONTROL_1 (0x69) */
  291. #define NAU8824_DMIC_CLK_DRV_STRG (1 << 3)
  292. #define NAU8824_DMIC_CLK_SLEW_FAST (0x7)
  293. /* ANALOG_CONTROL_2 (0x6A) */
  294. #define NAU8824_CLASSD_CLAMP_DIS_SFT 3
  295. #define NAU8824_CLASSD_CLAMP_DIS (0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT)
  296. /* ENABLE_LO (0x6B) */
  297. #define NAU8824_TEST_DAC_SFT 14
  298. #define NAU8824_TEST_DAC_EN (0x3 << NAU8824_TEST_DAC_SFT)
  299. #define NAU8824_DACL_HPR_EN_SFT 3
  300. #define NAU8824_DACL_HPR_EN (0x1 << NAU8824_DACL_HPR_EN_SFT)
  301. #define NAU8824_DACR_HPR_EN_SFT 2
  302. #define NAU8824_DACR_HPR_EN (0x1 << NAU8824_DACR_HPR_EN_SFT)
  303. #define NAU8824_DACR_HPL_EN_SFT 1
  304. #define NAU8824_DACR_HPL_EN (0x1 << NAU8824_DACR_HPL_EN_SFT)
  305. #define NAU8824_DACL_HPL_EN_SFT 0
  306. #define NAU8824_DACL_HPL_EN 0x1
  307. /* CLASSD_GAIN_1 (0x6D) */
  308. #define NAU8824_CLASSD_GAIN_1R_SFT 8
  309. #define NAU8824_CLASSD_GAIN_1R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
  310. #define NAU8824_CLASSD_EN_SFT 7
  311. #define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
  312. #define NAU8824_CLASSD_GAIN_1L_MASK 0x1f
  313. /* CLASSD_GAIN_2 (0x6E) */
  314. #define NAU8824_CLASSD_GAIN_2R_SFT 8
  315. #define NAU8824_CLASSD_GAIN_2R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
  316. #define NAU8824_CLASSD_EN_SFT 7
  317. #define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
  318. #define NAU8824_CLASSD_GAIN_2L_MASK 0x1f
  319. /* ANALOG_ADC_2 (0x72) */
  320. #define NAU8824_ADCR_EN_SFT 7
  321. #define NAU8824_ADCL_EN_SFT 6
  322. /* RDAC (0x73) */
  323. #define NAU8824_DACR_EN_SFT 13
  324. #define NAU8824_DACL_EN_SFT 12
  325. #define NAU8824_DACR_CLK_SFT 9
  326. #define NAU8824_DACL_CLK_SFT 8
  327. #define NAU8824_RDAC_CLK_DELAY_SFT 4
  328. #define NAU8824_RDAC_CLK_DELAY_MASK (0x7 << NAU8824_RDAC_CLK_DELAY_SFT)
  329. #define NAU8824_RDAC_VREF_SFT 2
  330. #define NAU8824_RDAC_VREF_MASK (0x3 << NAU8824_RDAC_VREF_SFT)
  331. /* MIC_BIAS (0x74) */
  332. #define NAU8824_MICBIAS_JKSLV (1 << 14)
  333. #define NAU8824_MICBIAS_JKR2 (1 << 12)
  334. #define NAU8824_MICBIAS_POWERUP_SFT 8
  335. #define NAU8824_MICBIAS_VOLTAGE_SFT 0
  336. #define NAU8824_MICBIAS_VOLTAGE_MASK 0x7
  337. /* BOOST (0x76) */
  338. #define NAU8824_PRECHARGE_DIS (0x1 << 13)
  339. #define NAU8824_GLOBAL_BIAS_EN (0x1 << 12)
  340. #define NAU8824_HP_BOOST_DIS_SFT 9
  341. #define NAU8824_HP_BOOST_DIS (0x1 << NAU8824_HP_BOOST_DIS_SFT)
  342. #define NAU8824_HP_BOOST_G_DIS_SFT 8
  343. #define NAU8824_HP_BOOST_G_DIS (0x1 << NAU8824_HP_BOOST_G_DIS_SFT)
  344. #define NAU8824_SHORT_SHUTDOWN_DIG_EN (1 << 7)
  345. #define NAU8824_SHORT_SHUTDOWN_EN (1 << 6)
  346. /* FEPGA (0x77) */
  347. #define NAU8824_FEPGA_MODER_SHORT_SFT 7
  348. #define NAU8824_FEPGA_MODER_SHORT_EN (0x1 << NAU8824_FEPGA_MODER_SHORT_SFT)
  349. #define NAU8824_FEPGA_MODER_MIC2_SFT 5
  350. #define NAU8824_FEPGA_MODER_MIC2_EN (0x1 << NAU8824_FEPGA_MODER_MIC2_SFT)
  351. #define NAU8824_FEPGA_MODER_HSMIC_SFT 4
  352. #define NAU8824_FEPGA_MODER_HSMIC_EN (0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT)
  353. #define NAU8824_FEPGA_MODEL_SHORT_SFT 3
  354. #define NAU8824_FEPGA_MODEL_SHORT_EN (0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT)
  355. #define NAU8824_FEPGA_MODEL_MIC1_SFT 1
  356. #define NAU8824_FEPGA_MODEL_MIC1_EN (0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT)
  357. #define NAU8824_FEPGA_MODEL_HSMIC_SFT 0
  358. #define NAU8824_FEPGA_MODEL_HSMIC_EN (0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT)
  359. /* FEPGA_II (0x78) */
  360. #define NAU8824_FEPGA_GAINR_SFT 5
  361. #define NAU8824_FEPGA_GAINR_MASK (0x1f << NAU8824_FEPGA_GAINR_SFT)
  362. #define NAU8824_FEPGA_GAINL_SFT 0
  363. #define NAU8824_FEPGA_GAINL_MASK 0x1f
  364. /* CHARGE_PUMP_CONTROL (0x80) */
  365. #define NAU8824_JAMNODCLOW (0x1 << 15)
  366. #define NAU8824_SPKR_PULL_DOWN (0x1 << 13)
  367. #define NAU8824_SPKL_PULL_DOWN (0x1 << 12)
  368. #define NAU8824_POWER_DOWN_DACR (0x1 << 9)
  369. #define NAU8824_POWER_DOWN_DACL (0x1 << 8)
  370. #define NAU8824_CHARGE_PUMP_EN_SFT 5
  371. #define NAU8824_CHARGE_PUMP_EN (0x1 << NAU8824_CHARGE_PUMP_EN_SFT)
  372. #define NAU8824_CODEC_DAI "nau8824-hifi"
  373. /* System Clock Source */
  374. enum {
  375. NAU8824_CLK_DIS,
  376. NAU8824_CLK_MCLK,
  377. NAU8824_CLK_INTERNAL,
  378. NAU8824_CLK_FLL_MCLK,
  379. NAU8824_CLK_FLL_BLK,
  380. NAU8824_CLK_FLL_FS,
  381. };
  382. struct nau8824 {
  383. struct device *dev;
  384. struct regmap *regmap;
  385. struct snd_soc_dapm_context *dapm;
  386. struct snd_soc_jack *jack;
  387. struct work_struct jdet_work;
  388. struct semaphore jd_sem;
  389. int fs;
  390. int irq;
  391. int resume_lock;
  392. int micbias_voltage;
  393. int vref_impedance;
  394. int jkdet_polarity;
  395. int sar_threshold_num;
  396. int sar_threshold[8];
  397. int sar_hysteresis;
  398. int sar_voltage;
  399. int sar_compare_time;
  400. int sar_sampling_time;
  401. int key_debounce;
  402. int jack_eject_debounce;
  403. };
  404. struct nau8824_fll {
  405. int mclk_src;
  406. int ratio;
  407. int fll_frac;
  408. int fll_int;
  409. int clk_ref_div;
  410. };
  411. struct nau8824_fll_attr {
  412. unsigned int param;
  413. unsigned int val;
  414. };
  415. struct nau8824_osr_attr {
  416. unsigned int osr;
  417. unsigned int clk_src;
  418. };
  419. int nau8824_enable_jack_detect(struct snd_soc_component *component,
  420. struct snd_soc_jack *jack);
  421. const char *nau8824_components(void);
  422. #endif /* _NAU8824_H */