mt6351.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // mt6351.c -- mt6351 ALSA SoC audio codec driver
  4. //
  5. // Copyright (c) 2018 MediaTek Inc.
  6. // Author: KaiChieh Chuang <[email protected]>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/module.h>
  11. #include <linux/of_device.h>
  12. #include <linux/delay.h>
  13. #include <sound/core.h>
  14. #include <sound/pcm.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. #include "mt6351.h"
  18. /* MT6351_TOP_CLKSQ */
  19. #define RG_CLKSQ_EN_AUD_BIT (0)
  20. /* MT6351_TOP_CKPDN_CON0 */
  21. #define RG_AUDNCP_CK_PDN_BIT (12)
  22. #define RG_AUDIF_CK_PDN_BIT (13)
  23. #define RG_AUD_CK_PDN_BIT (14)
  24. #define RG_ZCD13M_CK_PDN_BIT (15)
  25. /* MT6351_AUDDEC_ANA_CON0 */
  26. #define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
  27. #define RG_AUDDACRPWRUP_VAUDP32_BIT (1)
  28. #define RG_AUD_DAC_PWR_UP_VA32_BIT (2)
  29. #define RG_AUD_DAC_PWL_UP_VA32_BIT (3)
  30. #define RG_AUDHSPWRUP_VAUDP32_BIT (4)
  31. #define RG_AUDHPLPWRUP_VAUDP32_BIT (5)
  32. #define RG_AUDHPRPWRUP_VAUDP32_BIT (6)
  33. #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7)
  34. #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
  35. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9)
  36. #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
  37. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11)
  38. #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
  39. #define RG_AUDHSSCDISABLE_VAUDP32 (13)
  40. #define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14)
  41. #define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15)
  42. /* MT6351_AUDDEC_ANA_CON1 */
  43. #define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8)
  44. /* MT6351_AUDDEC_ANA_CON3 */
  45. #define RG_AUDLOLPWRUP_VAUDP32_BIT (2)
  46. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3)
  47. #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
  48. #define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5)
  49. #define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9)
  50. /* MT6351_AUDDEC_ANA_CON6 */
  51. #define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8)
  52. #define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9)
  53. #define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10)
  54. #define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11)
  55. /* MT6351_AUDDEC_ANA_CON9 */
  56. #define RG_AUDIBIASPWRDN_VAUDP32_BIT (8)
  57. #define RG_RSTB_DECODER_VA32_BIT (9)
  58. #define RG_AUDGLB_PWRDN_VA32_BIT (12)
  59. #define RG_LCLDO_DEC_EN_VA32_BIT (13)
  60. #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15)
  61. /* MT6351_AUDDEC_ANA_CON10 */
  62. #define RG_NVREG_EN_VAUDP32_BIT (8)
  63. #define RG_AUDGLB_LP2_VOW_EN_VA32 10
  64. /* MT6351_AFE_UL_DL_CON0 */
  65. #define RG_AFE_ON_BIT (0)
  66. /* MT6351_AFE_DL_SRC2_CON0_L */
  67. #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
  68. /* MT6351_AFE_UL_SRC_CON0_L */
  69. #define UL_SRC_ON_TMP_CTL (0)
  70. /* MT6351_AFE_TOP_CON0 */
  71. #define RG_DL_SINE_ON_SFT (0)
  72. #define RG_DL_SINE_ON_MASK (0x1)
  73. #define RG_UL_SINE_ON_SFT (1)
  74. #define RG_UL_SINE_ON_MASK (0x1)
  75. /* MT6351_AUDIO_TOP_CON0 */
  76. #define AUD_TOP_PDN_RESERVED_BIT 0
  77. #define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2
  78. #define AUD_TOP_PDN_ADC_CTL_BIT 5
  79. #define AUD_TOP_PDN_DAC_CTL_BIT 6
  80. #define AUD_TOP_PDN_AFE_CTL_BIT 7
  81. /* MT6351_AFE_SGEN_CFG0 */
  82. #define SGEN_C_MUTE_SW_CTL_BIT 6
  83. #define SGEN_C_DAC_EN_CTL_BIT 7
  84. /* MT6351_AFE_NCP_CFG0 */
  85. #define RG_NCP_ON_BIT 0
  86. /* MT6351_LDO_VUSB33_CON0 */
  87. #define RG_VUSB33_EN 1
  88. #define RG_VUSB33_ON_CTRL 3
  89. /* MT6351_LDO_VA18_CON0 */
  90. #define RG_VA18_EN 1
  91. #define RG_VA18_ON_CTRL 3
  92. /* MT6351_AUDENC_ANA_CON0 */
  93. #define RG_AUDPREAMPLON 0
  94. #define RG_AUDPREAMPLDCCEN 1
  95. #define RG_AUDPREAMPLDCPRECHARGE 2
  96. #define RG_AUDPREAMPLINPUTSEL_SFT (4)
  97. #define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
  98. #define RG_AUDADCLPWRUP 12
  99. #define RG_AUDADCLINPUTSEL_SFT (13)
  100. #define RG_AUDADCLINPUTSEL_MASK (0x3)
  101. /* MT6351_AUDENC_ANA_CON1 */
  102. #define RG_AUDPREAMPRON 0
  103. #define RG_AUDPREAMPRDCCEN 1
  104. #define RG_AUDPREAMPRDCPRECHARGE 2
  105. #define RG_AUDPREAMPRINPUTSEL_SFT (4)
  106. #define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
  107. #define RG_AUDADCRPWRUP 12
  108. #define RG_AUDADCRINPUTSEL_SFT (13)
  109. #define RG_AUDADCRINPUTSEL_MASK (0x3)
  110. /* MT6351_AUDENC_ANA_CON3 */
  111. #define RG_AUDADCCLKRSTB 6
  112. /* MT6351_AUDENC_ANA_CON9 */
  113. #define RG_AUDPWDBMICBIAS0 0
  114. #define RG_AUDMICBIAS0VREF 4
  115. #define RG_AUDMICBIAS0LOWPEN 7
  116. #define RG_AUDPWDBMICBIAS2 8
  117. #define RG_AUDMICBIAS2VREF 12
  118. #define RG_AUDMICBIAS2LOWPEN 15
  119. /* MT6351_AUDENC_ANA_CON10 */
  120. #define RG_AUDPWDBMICBIAS1 0
  121. #define RG_AUDMICBIAS1DCSW1NEN 2
  122. #define RG_AUDMICBIAS1VREF 4
  123. #define RG_AUDMICBIAS1LOWPEN 7
  124. enum {
  125. AUDIO_ANALOG_VOLUME_HSOUTL,
  126. AUDIO_ANALOG_VOLUME_HSOUTR,
  127. AUDIO_ANALOG_VOLUME_HPOUTL,
  128. AUDIO_ANALOG_VOLUME_HPOUTR,
  129. AUDIO_ANALOG_VOLUME_LINEOUTL,
  130. AUDIO_ANALOG_VOLUME_LINEOUTR,
  131. AUDIO_ANALOG_VOLUME_MICAMP1,
  132. AUDIO_ANALOG_VOLUME_MICAMP2,
  133. AUDIO_ANALOG_VOLUME_TYPE_MAX
  134. };
  135. /* Supply subseq */
  136. enum {
  137. SUPPLY_SUBSEQ_SETTING,
  138. SUPPLY_SUBSEQ_ENABLE,
  139. SUPPLY_SUBSEQ_MICBIAS,
  140. };
  141. #define REG_STRIDE 2
  142. struct mt6351_priv {
  143. struct device *dev;
  144. struct regmap *regmap;
  145. unsigned int dl_rate;
  146. unsigned int ul_rate;
  147. int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  148. int hp_en_counter;
  149. };
  150. static void set_hp_gain_zero(struct snd_soc_component *cmpnt)
  151. {
  152. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
  153. 0x1f << 7, 0x8 << 7);
  154. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
  155. 0x1f << 0, 0x8 << 0);
  156. }
  157. static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt,
  158. unsigned int rate)
  159. {
  160. switch (rate) {
  161. case 8000:
  162. return 0;
  163. case 16000:
  164. return 1;
  165. case 32000:
  166. return 2;
  167. case 48000:
  168. return 3;
  169. case 96000:
  170. return 4;
  171. case 192000:
  172. return 5;
  173. default:
  174. dev_warn(cmpnt->dev, "%s(), error rate %d, return 3",
  175. __func__, rate);
  176. return 3;
  177. }
  178. }
  179. static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt,
  180. unsigned int rate)
  181. {
  182. switch (rate) {
  183. case 8000:
  184. return 0;
  185. case 11025:
  186. return 1;
  187. case 12000:
  188. return 2;
  189. case 16000:
  190. return 3;
  191. case 22050:
  192. return 4;
  193. case 24000:
  194. return 5;
  195. case 32000:
  196. return 6;
  197. case 44100:
  198. return 7;
  199. case 48000:
  200. case 96000:
  201. case 192000:
  202. return 8;
  203. default:
  204. dev_warn(cmpnt->dev, "%s(), error rate %d, return 8",
  205. __func__, rate);
  206. return 8;
  207. }
  208. }
  209. static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream,
  210. struct snd_pcm_hw_params *params,
  211. struct snd_soc_dai *dai)
  212. {
  213. struct snd_soc_component *cmpnt = dai->component;
  214. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  215. unsigned int rate = params_rate(params);
  216. dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n",
  217. __func__, substream->stream, rate);
  218. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  219. priv->dl_rate = rate;
  220. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  221. priv->ul_rate = rate;
  222. return 0;
  223. }
  224. static const struct snd_soc_dai_ops mt6351_codec_dai_ops = {
  225. .hw_params = mt6351_codec_dai_hw_params,
  226. };
  227. #define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
  228. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
  229. SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
  230. static struct snd_soc_dai_driver mt6351_dai_driver[] = {
  231. {
  232. .name = "mt6351-snd-codec-aif1",
  233. .playback = {
  234. .stream_name = "AIF1 Playback",
  235. .channels_min = 1,
  236. .channels_max = 2,
  237. .rates = SNDRV_PCM_RATE_8000_48000 |
  238. SNDRV_PCM_RATE_96000 |
  239. SNDRV_PCM_RATE_192000,
  240. .formats = MT6351_FORMATS,
  241. },
  242. .capture = {
  243. .stream_name = "AIF1 Capture",
  244. .channels_min = 1,
  245. .channels_max = 2,
  246. .rates = SNDRV_PCM_RATE_8000 |
  247. SNDRV_PCM_RATE_16000 |
  248. SNDRV_PCM_RATE_32000 |
  249. SNDRV_PCM_RATE_48000 |
  250. SNDRV_PCM_RATE_96000 |
  251. SNDRV_PCM_RATE_192000,
  252. .formats = MT6351_FORMATS,
  253. },
  254. .ops = &mt6351_codec_dai_ops,
  255. },
  256. };
  257. enum {
  258. HP_GAIN_SET_ZERO,
  259. HP_GAIN_RESTORE,
  260. };
  261. static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl)
  262. {
  263. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  264. int idx, old_idx, offset, reg_idx;
  265. if (hp_gain_ctl == HP_GAIN_SET_ZERO) {
  266. idx = 8; /* 0dB */
  267. old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
  268. } else {
  269. idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
  270. old_idx = 8; /* 0dB */
  271. }
  272. dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n",
  273. __func__, idx, old_idx);
  274. if (idx > old_idx)
  275. offset = idx - old_idx;
  276. else
  277. offset = old_idx - idx;
  278. reg_idx = old_idx;
  279. while (offset > 0) {
  280. reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
  281. /* check valid range, and set value */
  282. if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
  283. regmap_update_bits(cmpnt->regmap,
  284. MT6351_ZCD_CON2,
  285. 0xf9f,
  286. (reg_idx << 7) | reg_idx);
  287. usleep_range(100, 120);
  288. }
  289. offset--;
  290. }
  291. }
  292. static void hp_zcd_enable(struct snd_soc_component *cmpnt)
  293. {
  294. /* Enable ZCD, for minimize pop noise */
  295. /* when adjust gain during HP buffer on */
  296. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8);
  297. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7);
  298. /* timeout, 1=5ms, 0=30ms */
  299. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6);
  300. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4);
  301. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1);
  302. regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0);
  303. }
  304. static void hp_zcd_disable(struct snd_soc_component *cmpnt)
  305. {
  306. regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000);
  307. }
  308. static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
  309. static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
  310. static const struct snd_kcontrol_new mt6351_snd_controls[] = {
  311. /* dl pga gain */
  312. SOC_DOUBLE_TLV("Headphone Volume",
  313. MT6351_ZCD_CON2, 0, 7, 0x12, 1,
  314. playback_tlv),
  315. SOC_DOUBLE_TLV("Lineout Volume",
  316. MT6351_ZCD_CON1, 0, 7, 0x12, 1,
  317. playback_tlv),
  318. SOC_SINGLE_TLV("Handset Volume",
  319. MT6351_ZCD_CON3, 0, 0x12, 1,
  320. playback_tlv),
  321. /* ul pga gain */
  322. SOC_DOUBLE_R_TLV("PGA Volume",
  323. MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1,
  324. 8, 4, 0,
  325. pga_tlv),
  326. };
  327. /* MUX */
  328. /* LOL MUX */
  329. static const char *const lo_in_mux_map[] = {
  330. "Open", "Mute", "Playback", "Test Mode",
  331. };
  332. static int lo_in_mux_map_value[] = {
  333. 0x0, 0x1, 0x2, 0x3,
  334. };
  335. static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
  336. MT6351_AUDDEC_ANA_CON3,
  337. RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT,
  338. RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK,
  339. lo_in_mux_map,
  340. lo_in_mux_map_value);
  341. static const struct snd_kcontrol_new lo_in_mux_control =
  342. SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
  343. /*HP MUX */
  344. static const char *const hp_in_mux_map[] = {
  345. "Open", "LoudSPK Playback", "Audio Playback", "Test Mode",
  346. };
  347. static int hp_in_mux_map_value[] = {
  348. 0x0, 0x1, 0x2, 0x3,
  349. };
  350. static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
  351. MT6351_AUDDEC_ANA_CON0,
  352. RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT,
  353. RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK,
  354. hp_in_mux_map,
  355. hp_in_mux_map_value);
  356. static const struct snd_kcontrol_new hpl_in_mux_control =
  357. SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
  358. static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
  359. MT6351_AUDDEC_ANA_CON0,
  360. RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT,
  361. RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK,
  362. hp_in_mux_map,
  363. hp_in_mux_map_value);
  364. static const struct snd_kcontrol_new hpr_in_mux_control =
  365. SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
  366. /* RCV MUX */
  367. static const char *const rcv_in_mux_map[] = {
  368. "Open", "Mute", "Voice Playback", "Test Mode",
  369. };
  370. static int rcv_in_mux_map_value[] = {
  371. 0x0, 0x1, 0x2, 0x3,
  372. };
  373. static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
  374. MT6351_AUDDEC_ANA_CON0,
  375. RG_AUDHSMUXINPUTSEL_VAUDP32_SFT,
  376. RG_AUDHSMUXINPUTSEL_VAUDP32_MASK,
  377. rcv_in_mux_map,
  378. rcv_in_mux_map_value);
  379. static const struct snd_kcontrol_new rcv_in_mux_control =
  380. SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
  381. /* DAC In MUX */
  382. static const char *const dac_in_mux_map[] = {
  383. "Normal Path", "Sgen",
  384. };
  385. static int dac_in_mux_map_value[] = {
  386. 0x0, 0x1,
  387. };
  388. static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
  389. MT6351_AFE_TOP_CON0,
  390. RG_DL_SINE_ON_SFT,
  391. RG_DL_SINE_ON_MASK,
  392. dac_in_mux_map,
  393. dac_in_mux_map_value);
  394. static const struct snd_kcontrol_new dac_in_mux_control =
  395. SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
  396. /* AIF Out MUX */
  397. static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
  398. MT6351_AFE_TOP_CON0,
  399. RG_UL_SINE_ON_SFT,
  400. RG_UL_SINE_ON_MASK,
  401. dac_in_mux_map,
  402. dac_in_mux_map_value);
  403. static const struct snd_kcontrol_new aif_out_mux_control =
  404. SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
  405. /* ADC L MUX */
  406. static const char *const adc_left_mux_map[] = {
  407. "Idle", "AIN0", "Left Preamplifier", "Idle_1",
  408. };
  409. static int adc_left_mux_map_value[] = {
  410. 0x0, 0x1, 0x2, 0x3,
  411. };
  412. static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
  413. MT6351_AUDENC_ANA_CON0,
  414. RG_AUDADCLINPUTSEL_SFT,
  415. RG_AUDADCLINPUTSEL_MASK,
  416. adc_left_mux_map,
  417. adc_left_mux_map_value);
  418. static const struct snd_kcontrol_new adc_left_mux_control =
  419. SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
  420. /* ADC R MUX */
  421. static const char *const adc_right_mux_map[] = {
  422. "Idle", "AIN0", "Right Preamplifier", "Idle_1",
  423. };
  424. static int adc_right_mux_map_value[] = {
  425. 0x0, 0x1, 0x2, 0x3,
  426. };
  427. static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
  428. MT6351_AUDENC_ANA_CON1,
  429. RG_AUDADCRINPUTSEL_SFT,
  430. RG_AUDADCRINPUTSEL_MASK,
  431. adc_right_mux_map,
  432. adc_right_mux_map_value);
  433. static const struct snd_kcontrol_new adc_right_mux_control =
  434. SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
  435. /* PGA L MUX */
  436. static const char *const pga_left_mux_map[] = {
  437. "None", "AIN0", "AIN1", "AIN2",
  438. };
  439. static int pga_left_mux_map_value[] = {
  440. 0x0, 0x1, 0x2, 0x3,
  441. };
  442. static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
  443. MT6351_AUDENC_ANA_CON0,
  444. RG_AUDPREAMPLINPUTSEL_SFT,
  445. RG_AUDPREAMPLINPUTSEL_MASK,
  446. pga_left_mux_map,
  447. pga_left_mux_map_value);
  448. static const struct snd_kcontrol_new pga_left_mux_control =
  449. SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
  450. /* PGA R MUX */
  451. static const char *const pga_right_mux_map[] = {
  452. "None", "AIN0", "AIN3", "AIN2",
  453. };
  454. static int pga_right_mux_map_value[] = {
  455. 0x0, 0x1, 0x2, 0x3,
  456. };
  457. static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
  458. MT6351_AUDENC_ANA_CON1,
  459. RG_AUDPREAMPRINPUTSEL_SFT,
  460. RG_AUDPREAMPRINPUTSEL_MASK,
  461. pga_right_mux_map,
  462. pga_right_mux_map_value);
  463. static const struct snd_kcontrol_new pga_right_mux_control =
  464. SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
  465. static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w,
  466. struct snd_kcontrol *kcontrol,
  467. int event)
  468. {
  469. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  470. switch (event) {
  471. case SND_SOC_DAPM_POST_PMU:
  472. if (w->on_val) {
  473. /* SET REG */
  474. regmap_update_bits(cmpnt->regmap,
  475. w->reg + REG_STRIDE,
  476. 0x1 << w->shift,
  477. 0x1 << w->shift);
  478. } else {
  479. /* CLR REG */
  480. regmap_update_bits(cmpnt->regmap,
  481. w->reg + REG_STRIDE * 2,
  482. 0x1 << w->shift,
  483. 0x1 << w->shift);
  484. }
  485. break;
  486. case SND_SOC_DAPM_PRE_PMD:
  487. if (w->off_val) {
  488. /* SET REG */
  489. regmap_update_bits(cmpnt->regmap,
  490. w->reg + REG_STRIDE,
  491. 0x1 << w->shift,
  492. 0x1 << w->shift);
  493. } else {
  494. /* CLR REG */
  495. regmap_update_bits(cmpnt->regmap,
  496. w->reg + REG_STRIDE * 2,
  497. 0x1 << w->shift,
  498. 0x1 << w->shift);
  499. }
  500. break;
  501. default:
  502. break;
  503. }
  504. return 0;
  505. }
  506. static int mt_ncp_event(struct snd_soc_dapm_widget *w,
  507. struct snd_kcontrol *kcontrol,
  508. int event)
  509. {
  510. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  511. switch (event) {
  512. case SND_SOC_DAPM_PRE_PMU:
  513. regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1,
  514. 0xffff, 0x1515);
  515. /* NCP: ck1 and ck2 clock frequecy adjust configure */
  516. regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0,
  517. 0xfffe, 0x8C00);
  518. break;
  519. case SND_SOC_DAPM_POST_PMU:
  520. usleep_range(250, 270);
  521. break;
  522. default:
  523. break;
  524. }
  525. return 0;
  526. }
  527. static int mt_sgen_event(struct snd_soc_dapm_widget *w,
  528. struct snd_kcontrol *kcontrol,
  529. int event)
  530. {
  531. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  532. switch (event) {
  533. case SND_SOC_DAPM_PRE_PMU:
  534. regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0,
  535. 0xffef, 0x0008);
  536. regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1,
  537. 0xffff, 0x0101);
  538. break;
  539. default:
  540. break;
  541. }
  542. return 0;
  543. }
  544. static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
  545. struct snd_kcontrol *kcontrol,
  546. int event)
  547. {
  548. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  549. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  550. dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
  551. __func__, event, priv->dl_rate);
  552. switch (event) {
  553. case SND_SOC_DAPM_PRE_PMU:
  554. /* sdm audio fifo clock power on */
  555. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  556. 0xffff, 0x0006);
  557. /* scrambler clock on enable */
  558. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0,
  559. 0xffff, 0xC3A1);
  560. /* sdm power on */
  561. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  562. 0xffff, 0x0003);
  563. /* sdm fifo enable */
  564. regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
  565. 0xffff, 0x000B);
  566. /* set attenuation gain */
  567. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1,
  568. 0xffff, 0x001E);
  569. regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0,
  570. (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
  571. 0x330);
  572. regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H,
  573. (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
  574. 0x300);
  575. regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
  576. 0x8000, 0x8000);
  577. break;
  578. default:
  579. break;
  580. }
  581. return 0;
  582. }
  583. static int mt_hp_event(struct snd_soc_dapm_widget *w,
  584. struct snd_kcontrol *kcontrol,
  585. int event)
  586. {
  587. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  588. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  589. int reg;
  590. dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n",
  591. __func__, event, priv->hp_en_counter);
  592. switch (event) {
  593. case SND_SOC_DAPM_PRE_PMU:
  594. priv->hp_en_counter++;
  595. if (priv->hp_en_counter > 1)
  596. break; /* already enabled, do nothing */
  597. else if (priv->hp_en_counter <= 0)
  598. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  599. __func__,
  600. priv->hp_en_counter);
  601. hp_zcd_disable(cmpnt);
  602. /* from yoyo HQA script */
  603. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
  604. 0x0700, 0x0700);
  605. /* save target gain to restore after hardware open complete */
  606. regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, &reg);
  607. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f;
  608. priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f;
  609. /* Set HPR/HPL gain as minimum (~ -40dB) */
  610. regmap_update_bits(cmpnt->regmap,
  611. MT6351_ZCD_CON2, 0xffff, 0x0F9F);
  612. /* Set HS gain as minimum (~ -40dB) */
  613. regmap_update_bits(cmpnt->regmap,
  614. MT6351_ZCD_CON3, 0xffff, 0x001F);
  615. /* De_OSC of HP */
  616. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2,
  617. 0x0001, 0x0001);
  618. /* enable output STBENH */
  619. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  620. 0xffff, 0x2000);
  621. /* De_OSC of voice, enable output STBENH */
  622. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  623. 0xffff, 0x2100);
  624. /* Enable voice driver */
  625. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  626. 0x0010, 0xE090);
  627. /* Enable pre-charge buffer */
  628. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  629. 0xffff, 0x2140);
  630. usleep_range(50, 60);
  631. /* Apply digital DC compensation value to DAC */
  632. set_hp_gain_zero(cmpnt);
  633. /* Enable HPR/HPL */
  634. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  635. 0xffff, 0x2100);
  636. /* Disable pre-charge buffer */
  637. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
  638. 0xffff, 0x2000);
  639. /* Disable De_OSC of voice */
  640. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  641. 0x0010, 0xF4EF);
  642. /* Disable voice buffer */
  643. /* from yoyo HQ */
  644. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
  645. 0x0700, 0x0300);
  646. /* Enable ZCD, for minimize pop noise */
  647. /* when adjust gain during HP buffer on */
  648. hp_zcd_enable(cmpnt);
  649. /* apply volume setting */
  650. hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
  651. break;
  652. case SND_SOC_DAPM_PRE_PMD:
  653. priv->hp_en_counter--;
  654. if (priv->hp_en_counter > 0)
  655. break; /* still being used, don't close */
  656. else if (priv->hp_en_counter < 0)
  657. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  658. __func__,
  659. priv->hp_en_counter);
  660. /* Disable AUD_ZCD */
  661. hp_zcd_disable(cmpnt);
  662. /* Set HPR/HPL gain as -1dB, step by step */
  663. hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO);
  664. set_hp_gain_zero(cmpnt);
  665. break;
  666. case SND_SOC_DAPM_POST_PMD:
  667. if (priv->hp_en_counter > 0)
  668. break; /* still being used, don't close */
  669. else if (priv->hp_en_counter < 0)
  670. dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
  671. __func__,
  672. priv->hp_en_counter);
  673. /* reset*/
  674. regmap_update_bits(cmpnt->regmap,
  675. MT6351_AUDDEC_ANA_CON6,
  676. 0x0700,
  677. 0x0000);
  678. /* De_OSC of HP */
  679. regmap_update_bits(cmpnt->regmap,
  680. MT6351_AUDDEC_ANA_CON2,
  681. 0x0001,
  682. 0x0000);
  683. /* apply volume setting */
  684. hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
  685. break;
  686. default:
  687. break;
  688. }
  689. return 0;
  690. }
  691. static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
  692. struct snd_kcontrol *kcontrol,
  693. int event)
  694. {
  695. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  696. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  697. dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
  698. __func__, event, priv->ul_rate);
  699. switch (event) {
  700. case SND_SOC_DAPM_PRE_PMU:
  701. /* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */
  702. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  703. 0xffff, 0x2062);
  704. /* dcclk_pdn=1'b0 */
  705. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  706. 0xffff, 0x2060);
  707. /* dcclk_gen_on=1'b1 */
  708. regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
  709. 0xffff, 0x2061);
  710. /* UL sample rate and mode configure */
  711. regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H,
  712. 0x000E,
  713. get_cap_reg_val(cmpnt, priv->ul_rate) << 1);
  714. /* fixed 260k path for 8/16/32/48 */
  715. if (priv->ul_rate <= 48000) {
  716. /* anc ul path src on */
  717. regmap_update_bits(cmpnt->regmap,
  718. MT6351_AFE_HPANC_CFG0,
  719. 0x1 << 1,
  720. 0x1 << 1);
  721. /* ANC clk pdn release */
  722. regmap_update_bits(cmpnt->regmap,
  723. MT6351_AFE_HPANC_CFG0,
  724. 0x1 << 0,
  725. 0x0 << 0);
  726. }
  727. break;
  728. case SND_SOC_DAPM_PRE_PMD:
  729. /* fixed 260k path for 8/16/32/48 */
  730. if (priv->ul_rate <= 48000) {
  731. /* anc ul path src on */
  732. regmap_update_bits(cmpnt->regmap,
  733. MT6351_AFE_HPANC_CFG0,
  734. 0x1 << 1,
  735. 0x0 << 1);
  736. /* ANC clk pdn release */
  737. regmap_update_bits(cmpnt->regmap,
  738. MT6351_AFE_HPANC_CFG0,
  739. 0x1 << 0,
  740. 0x1 << 0);
  741. }
  742. break;
  743. default:
  744. break;
  745. }
  746. return 0;
  747. }
  748. static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w,
  749. struct snd_kcontrol *kcontrol,
  750. int event)
  751. {
  752. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  753. switch (event) {
  754. case SND_SOC_DAPM_PRE_PMU:
  755. /* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */
  756. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
  757. 0x3 << 4, 0x0);
  758. break;
  759. case SND_SOC_DAPM_POST_PMU:
  760. /* ADC CLK from: 00_13MHz from CLKSQ (Default) */
  761. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
  762. 0x3 << 2, 0x0);
  763. break;
  764. default:
  765. break;
  766. }
  767. return 0;
  768. }
  769. static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
  770. struct snd_kcontrol *kcontrol,
  771. int event)
  772. {
  773. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  774. switch (event) {
  775. case SND_SOC_DAPM_PRE_PMU:
  776. /* Audio L PGA precharge on */
  777. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  778. 0x3 << RG_AUDPREAMPLDCPRECHARGE,
  779. 0x1 << RG_AUDPREAMPLDCPRECHARGE);
  780. /* Audio L PGA mode: 1_DCC */
  781. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  782. 0x3 << RG_AUDPREAMPLDCCEN,
  783. 0x1 << RG_AUDPREAMPLDCCEN);
  784. break;
  785. case SND_SOC_DAPM_POST_PMU:
  786. usleep_range(100, 120);
  787. /* Audio L PGA precharge off */
  788. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
  789. 0x3 << RG_AUDPREAMPLDCPRECHARGE,
  790. 0x0 << RG_AUDPREAMPLDCPRECHARGE);
  791. break;
  792. default:
  793. break;
  794. }
  795. return 0;
  796. }
  797. static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
  798. struct snd_kcontrol *kcontrol,
  799. int event)
  800. {
  801. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  802. switch (event) {
  803. case SND_SOC_DAPM_PRE_PMU:
  804. /* Audio R PGA precharge on */
  805. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  806. 0x3 << RG_AUDPREAMPRDCPRECHARGE,
  807. 0x1 << RG_AUDPREAMPRDCPRECHARGE);
  808. /* Audio R PGA mode: 1_DCC */
  809. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  810. 0x3 << RG_AUDPREAMPRDCCEN,
  811. 0x1 << RG_AUDPREAMPRDCCEN);
  812. break;
  813. case SND_SOC_DAPM_POST_PMU:
  814. usleep_range(100, 120);
  815. /* Audio R PGA precharge off */
  816. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
  817. 0x3 << RG_AUDPREAMPRDCPRECHARGE,
  818. 0x0 << RG_AUDPREAMPRDCPRECHARGE);
  819. break;
  820. default:
  821. break;
  822. }
  823. return 0;
  824. }
  825. static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
  826. struct snd_kcontrol *kcontrol,
  827. int event)
  828. {
  829. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  830. switch (event) {
  831. case SND_SOC_DAPM_PRE_PMU:
  832. /* MIC Bias 0 LowPower: 0_Normal */
  833. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  834. 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0);
  835. /* MISBIAS0 = 1P9V */
  836. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  837. 0x7 << RG_AUDMICBIAS0VREF,
  838. 0x2 << RG_AUDMICBIAS0VREF);
  839. break;
  840. case SND_SOC_DAPM_POST_PMD:
  841. /* MISBIAS0 = 1P97 */
  842. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  843. 0x7 << RG_AUDMICBIAS0VREF,
  844. 0x0 << RG_AUDMICBIAS0VREF);
  845. break;
  846. default:
  847. break;
  848. }
  849. return 0;
  850. }
  851. static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
  852. struct snd_kcontrol *kcontrol,
  853. int event)
  854. {
  855. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  856. switch (event) {
  857. case SND_SOC_DAPM_PRE_PMU:
  858. /* MIC Bias 1 LowPower: 0_Normal */
  859. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  860. 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0);
  861. /* MISBIAS1 = 2P7V */
  862. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  863. 0x7 << RG_AUDMICBIAS1VREF,
  864. 0x7 << RG_AUDMICBIAS1VREF);
  865. break;
  866. case SND_SOC_DAPM_POST_PMD:
  867. /* MISBIAS1 = 1P7V */
  868. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
  869. 0x7 << RG_AUDMICBIAS1VREF,
  870. 0x0 << RG_AUDMICBIAS1VREF);
  871. break;
  872. default:
  873. break;
  874. }
  875. return 0;
  876. }
  877. static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
  878. struct snd_kcontrol *kcontrol,
  879. int event)
  880. {
  881. struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
  882. switch (event) {
  883. case SND_SOC_DAPM_PRE_PMU:
  884. /* MIC Bias 2 LowPower: 0_Normal */
  885. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  886. 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0);
  887. /* MISBIAS2 = 1P9V */
  888. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  889. 0x7 << RG_AUDMICBIAS2VREF,
  890. 0x2 << RG_AUDMICBIAS2VREF);
  891. break;
  892. case SND_SOC_DAPM_POST_PMD:
  893. /* MISBIAS2 = 1P97 */
  894. regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
  895. 0x7 << RG_AUDMICBIAS2VREF,
  896. 0x0 << RG_AUDMICBIAS2VREF);
  897. break;
  898. default:
  899. break;
  900. }
  901. return 0;
  902. }
  903. /* DAPM Widgets */
  904. static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = {
  905. /* Digital Clock */
  906. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0,
  907. AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
  908. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0,
  909. AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
  910. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0,
  911. AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
  912. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0,
  913. AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
  914. SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0,
  915. AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
  916. SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0,
  917. RG_NCP_ON_BIT, 0,
  918. mt_ncp_event,
  919. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  920. SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
  921. 0, 0, NULL, 0),
  922. /* Global Supply*/
  923. SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9,
  924. RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
  925. SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ,
  926. RG_CLKSQ_EN_AUD_BIT, 0,
  927. mt_reg_set_clr_event,
  928. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  929. SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0,
  930. RG_ZCD13M_CK_PDN_BIT, 1,
  931. mt_reg_set_clr_event,
  932. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  933. SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0,
  934. RG_AUD_CK_PDN_BIT, 1,
  935. mt_reg_set_clr_event,
  936. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  937. SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0,
  938. RG_AUDIF_CK_PDN_BIT, 1,
  939. mt_reg_set_clr_event,
  940. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  941. SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0,
  942. RG_AUDNCP_CK_PDN_BIT, 1,
  943. mt_reg_set_clr_event,
  944. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  945. SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
  946. NULL, 0),
  947. /* AIF Rx*/
  948. SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
  949. MT6351_AFE_DL_SRC2_CON0_L,
  950. RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
  951. mt_aif_in_event, SND_SOC_DAPM_PRE_PMU),
  952. /* DL Supply */
  953. SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
  954. 0, 0, NULL, 0),
  955. SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10,
  956. RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
  957. SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9,
  958. RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
  959. SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9,
  960. RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
  961. SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9,
  962. RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
  963. SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9,
  964. RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
  965. /* DAC */
  966. SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
  967. SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0,
  968. RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
  969. SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0,
  970. RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
  971. SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0,
  972. RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
  973. SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0,
  974. RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
  975. /* LOL */
  976. SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
  977. SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3,
  978. RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
  979. SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6,
  980. RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
  981. SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3,
  982. RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
  983. /* Headphone */
  984. SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
  985. SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
  986. SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0,
  987. RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
  988. mt_hp_event,
  989. SND_SOC_DAPM_PRE_PMU |
  990. SND_SOC_DAPM_PRE_PMD |
  991. SND_SOC_DAPM_POST_PMD),
  992. SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0,
  993. RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
  994. mt_hp_event,
  995. SND_SOC_DAPM_PRE_PMU |
  996. SND_SOC_DAPM_PRE_PMD |
  997. SND_SOC_DAPM_POST_PMD),
  998. /* Receiver */
  999. SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
  1000. SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1,
  1001. RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
  1002. SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6,
  1003. RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
  1004. SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0,
  1005. RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
  1006. /* Outputs */
  1007. SND_SOC_DAPM_OUTPUT("Receiver"),
  1008. SND_SOC_DAPM_OUTPUT("Headphone L"),
  1009. SND_SOC_DAPM_OUTPUT("Headphone R"),
  1010. SND_SOC_DAPM_OUTPUT("LINEOUT L"),
  1011. /* SGEN */
  1012. SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
  1013. SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
  1014. SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
  1015. SGEN_C_MUTE_SW_CTL_BIT, 1,
  1016. mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
  1017. SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
  1018. RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
  1019. SND_SOC_DAPM_INPUT("SGEN DL"),
  1020. /* Uplinks */
  1021. SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
  1022. MT6351_AFE_UL_SRC_CON0_L,
  1023. UL_SRC_ON_TMP_CTL, 0,
  1024. mt_aif_out_event,
  1025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  1026. SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
  1027. MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
  1028. NULL, 0),
  1029. SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
  1030. MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
  1031. NULL, 0),
  1032. SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
  1033. MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
  1034. SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
  1035. MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
  1036. NULL, 0),
  1037. SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE,
  1038. MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
  1039. mt_adc_clkgen_event,
  1040. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1041. /* Uplinks MUX */
  1042. SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
  1043. &aif_out_mux_control),
  1044. SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
  1045. &adc_left_mux_control),
  1046. SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
  1047. &adc_right_mux_control),
  1048. SND_SOC_DAPM_ADC("ADC L", NULL,
  1049. MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
  1050. SND_SOC_DAPM_ADC("ADC R", NULL,
  1051. MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
  1052. SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
  1053. &pga_left_mux_control),
  1054. SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
  1055. &pga_right_mux_control),
  1056. SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
  1057. NULL, 0,
  1058. mt_pga_left_event,
  1059. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1060. SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
  1061. NULL, 0,
  1062. mt_pga_right_event,
  1063. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  1064. /* main mic mic bias */
  1065. SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
  1066. MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
  1067. mt_mic_bias_0_event,
  1068. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1069. /* ref mic mic bias */
  1070. SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS,
  1071. MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
  1072. mt_mic_bias_2_event,
  1073. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1074. /* headset mic1/2 mic bias */
  1075. SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS,
  1076. MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
  1077. mt_mic_bias_1_event,
  1078. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1079. SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS,
  1080. MT6351_AUDENC_ANA_CON10,
  1081. RG_AUDMICBIAS1DCSW1NEN, 0,
  1082. NULL, 0),
  1083. /* UL input */
  1084. SND_SOC_DAPM_INPUT("AIN0"),
  1085. SND_SOC_DAPM_INPUT("AIN1"),
  1086. SND_SOC_DAPM_INPUT("AIN2"),
  1087. SND_SOC_DAPM_INPUT("AIN3"),
  1088. };
  1089. static const struct snd_soc_dapm_route mt6351_dapm_routes[] = {
  1090. /* Capture */
  1091. {"AIF1TX", NULL, "AIF Out Mux"},
  1092. {"AIF1TX", NULL, "VUSB33_LDO"},
  1093. {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"},
  1094. {"AIF1TX", NULL, "VA18_LDO"},
  1095. {"VA18_LDO", NULL, "VA18_LDO_CTRL"},
  1096. {"AIF1TX", NULL, "AUDGLB"},
  1097. {"AIF1TX", NULL, "CLKSQ Audio"},
  1098. {"AIF1TX", NULL, "AFE_ON"},
  1099. {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
  1100. {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
  1101. {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
  1102. {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1103. {"AIF Out Mux", "Normal Path", "ADC L"},
  1104. {"AIF Out Mux", "Normal Path", "ADC R"},
  1105. {"ADC L", NULL, "ADC L Mux"},
  1106. {"ADC L", NULL, "AUD_CK"},
  1107. {"ADC L", NULL, "AUDIF_CK"},
  1108. {"ADC L", NULL, "ADC CLKGEN"},
  1109. {"ADC R", NULL, "ADC R Mux"},
  1110. {"ADC R", NULL, "AUD_CK"},
  1111. {"ADC R", NULL, "AUDIF_CK"},
  1112. {"ADC R", NULL, "ADC CLKGEN"},
  1113. {"ADC L Mux", "AIN0", "AIN0"},
  1114. {"ADC L Mux", "Left Preamplifier", "PGA L"},
  1115. {"ADC R Mux", "AIN0", "AIN0"},
  1116. {"ADC R Mux", "Right Preamplifier", "PGA R"},
  1117. {"PGA L", NULL, "PGA L Mux"},
  1118. {"PGA R", NULL, "PGA R Mux"},
  1119. {"PGA L Mux", "AIN0", "AIN0"},
  1120. {"PGA L Mux", "AIN1", "AIN1"},
  1121. {"PGA L Mux", "AIN2", "AIN2"},
  1122. {"PGA R Mux", "AIN0", "AIN0"},
  1123. {"PGA R Mux", "AIN3", "AIN3"},
  1124. {"PGA R Mux", "AIN2", "AIN2"},
  1125. {"AIN0", NULL, "Mic Bias 0"},
  1126. {"AIN2", NULL, "Mic Bias 2"},
  1127. {"AIN1", NULL, "Mic Bias 1"},
  1128. {"AIN1", NULL, "Mic Bias 1 DCC pull high"},
  1129. /* DL Supply */
  1130. {"DL Power Supply", NULL, "AUDGLB"},
  1131. {"DL Power Supply", NULL, "CLKSQ Audio"},
  1132. {"DL Power Supply", NULL, "ZCD13M_CK"},
  1133. {"DL Power Supply", NULL, "AUD_CK"},
  1134. {"DL Power Supply", NULL, "AUDIF_CK"},
  1135. {"DL Power Supply", NULL, "AUDNCP_CK"},
  1136. {"DL Power Supply", NULL, "NV Regulator"},
  1137. {"DL Power Supply", NULL, "AUD_CLK"},
  1138. {"DL Power Supply", NULL, "IBIST"},
  1139. {"DL Power Supply", NULL, "LDO"},
  1140. {"LDO", NULL, "LDO_REMOTE_SENSE"},
  1141. /* DL Digital Supply */
  1142. {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
  1143. {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
  1144. {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
  1145. {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
  1146. {"DL Digital Clock", NULL, "NCP"},
  1147. {"DL Digital Clock", NULL, "AFE_ON"},
  1148. {"AIF_RX", NULL, "DL Digital Clock"},
  1149. /* DL Path */
  1150. {"DAC In Mux", "Normal Path", "AIF_RX"},
  1151. {"DAC In Mux", "Sgen", "SGEN DL"},
  1152. {"SGEN DL", NULL, "SGEN DL SRC"},
  1153. {"SGEN DL", NULL, "SGEN MUTE"},
  1154. {"SGEN DL", NULL, "SGEN DL Enable"},
  1155. {"SGEN DL", NULL, "DL Digital Clock"},
  1156. {"DACL", NULL, "DAC In Mux"},
  1157. {"DACL", NULL, "DL Power Supply"},
  1158. {"DACL", NULL, "DACL_BIASGEN"},
  1159. {"DACR", NULL, "DAC In Mux"},
  1160. {"DACR", NULL, "DL Power Supply"},
  1161. {"DACR", NULL, "DACR_BIASGEN"},
  1162. {"LOL Mux", "Playback", "DACL"},
  1163. {"LOL Buffer", NULL, "LOL Mux"},
  1164. {"LOL Buffer", NULL, "LO Stability Enh"},
  1165. {"LOL Buffer", NULL, "LOL Bias Gen"},
  1166. {"LINEOUT L", NULL, "LOL Buffer"},
  1167. /* Headphone Path */
  1168. {"HPL Mux", "Audio Playback", "DACL"},
  1169. {"HPR Mux", "Audio Playback", "DACR"},
  1170. {"HPL Mux", "LoudSPK Playback", "DACL"},
  1171. {"HPR Mux", "LoudSPK Playback", "DACR"},
  1172. {"HPL Power", NULL, "HPL Mux"},
  1173. {"HPR Power", NULL, "HPR Mux"},
  1174. {"Headphone L", NULL, "HPL Power"},
  1175. {"Headphone R", NULL, "HPR Power"},
  1176. /* Receiver Path */
  1177. {"RCV Mux", "Voice Playback", "DACL"},
  1178. {"RCV Buffer", NULL, "RCV Mux"},
  1179. {"RCV Buffer", NULL, "RCV Stability Enh"},
  1180. {"RCV Buffer", NULL, "RCV Bias Gen"},
  1181. {"Receiver", NULL, "RCV Buffer"},
  1182. };
  1183. static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt)
  1184. {
  1185. /* Disable CLKSQ 26MHz */
  1186. regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0);
  1187. /* disable AUDGLB */
  1188. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9,
  1189. 0x1000, 0x1000);
  1190. /* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */
  1191. regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET,
  1192. 0x3800, 0x3800);
  1193. /* Disable HeadphoneL/HeadphoneR/voice short circuit protection */
  1194. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
  1195. 0xe000, 0xe000);
  1196. /* [5] = 1, disable LO buffer left short circuit protection */
  1197. regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3,
  1198. 0x20, 0x20);
  1199. /* Reverse the PMIC clock*/
  1200. regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
  1201. 0x8000, 0x8000);
  1202. return 0;
  1203. }
  1204. static int mt6351_codec_probe(struct snd_soc_component *cmpnt)
  1205. {
  1206. struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
  1207. snd_soc_component_init_regmap(cmpnt, priv->regmap);
  1208. mt6351_codec_init_reg(cmpnt);
  1209. return 0;
  1210. }
  1211. static const struct snd_soc_component_driver mt6351_soc_component_driver = {
  1212. .probe = mt6351_codec_probe,
  1213. .controls = mt6351_snd_controls,
  1214. .num_controls = ARRAY_SIZE(mt6351_snd_controls),
  1215. .dapm_widgets = mt6351_dapm_widgets,
  1216. .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets),
  1217. .dapm_routes = mt6351_dapm_routes,
  1218. .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes),
  1219. .endianness = 1,
  1220. };
  1221. static int mt6351_codec_driver_probe(struct platform_device *pdev)
  1222. {
  1223. struct mt6351_priv *priv;
  1224. priv = devm_kzalloc(&pdev->dev,
  1225. sizeof(struct mt6351_priv),
  1226. GFP_KERNEL);
  1227. if (!priv)
  1228. return -ENOMEM;
  1229. dev_set_drvdata(&pdev->dev, priv);
  1230. priv->dev = &pdev->dev;
  1231. priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  1232. if (!priv->regmap)
  1233. return -ENODEV;
  1234. dev_dbg(priv->dev, "%s(), dev name %s\n",
  1235. __func__, dev_name(&pdev->dev));
  1236. return devm_snd_soc_register_component(&pdev->dev,
  1237. &mt6351_soc_component_driver,
  1238. mt6351_dai_driver,
  1239. ARRAY_SIZE(mt6351_dai_driver));
  1240. }
  1241. static const struct of_device_id mt6351_of_match[] = {
  1242. {.compatible = "mediatek,mt6351-sound",},
  1243. {}
  1244. };
  1245. static struct platform_driver mt6351_codec_driver = {
  1246. .driver = {
  1247. .name = "mt6351-sound",
  1248. .of_match_table = mt6351_of_match,
  1249. },
  1250. .probe = mt6351_codec_driver_probe,
  1251. };
  1252. module_platform_driver(mt6351_codec_driver)
  1253. /* Module information */
  1254. MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver");
  1255. MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
  1256. MODULE_LICENSE("GPL v2");