es8328.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * es8328.c -- ES8328 ALSA SoC Audio driver
  4. *
  5. * Copyright 2014 Sutajio Ko-Usagi PTE LTD
  6. *
  7. * Author: Sean Cross <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/of_device.h>
  12. #include <linux/module.h>
  13. #include <linux/pm.h>
  14. #include <linux/regmap.h>
  15. #include <linux/slab.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/initval.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/tlv.h>
  23. #include "es8328.h"
  24. static const unsigned int rates_12288[] = {
  25. 8000, 12000, 16000, 24000, 32000, 48000, 96000,
  26. };
  27. static const int ratios_12288[] = {
  28. 10, 7, 6, 4, 3, 2, 0,
  29. };
  30. static const struct snd_pcm_hw_constraint_list constraints_12288 = {
  31. .count = ARRAY_SIZE(rates_12288),
  32. .list = rates_12288,
  33. };
  34. static const unsigned int rates_11289[] = {
  35. 8018, 11025, 22050, 44100, 88200,
  36. };
  37. static const int ratios_11289[] = {
  38. 9, 7, 4, 2, 0,
  39. };
  40. static const struct snd_pcm_hw_constraint_list constraints_11289 = {
  41. .count = ARRAY_SIZE(rates_11289),
  42. .list = rates_11289,
  43. };
  44. /* regulator supplies for sgtl5000, VDDD is an optional external supply */
  45. enum sgtl5000_regulator_supplies {
  46. DVDD,
  47. AVDD,
  48. PVDD,
  49. HPVDD,
  50. ES8328_SUPPLY_NUM
  51. };
  52. /* vddd is optional supply */
  53. static const char * const supply_names[ES8328_SUPPLY_NUM] = {
  54. "DVDD",
  55. "AVDD",
  56. "PVDD",
  57. "HPVDD",
  58. };
  59. #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
  60. SNDRV_PCM_RATE_96000 | \
  61. SNDRV_PCM_RATE_88200 | \
  62. SNDRV_PCM_RATE_8000_48000)
  63. #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  64. SNDRV_PCM_FMTBIT_S18_3LE | \
  65. SNDRV_PCM_FMTBIT_S20_3LE | \
  66. SNDRV_PCM_FMTBIT_S24_LE | \
  67. SNDRV_PCM_FMTBIT_S32_LE)
  68. struct es8328_priv {
  69. struct regmap *regmap;
  70. struct clk *clk;
  71. int playback_fs;
  72. bool deemph;
  73. int mclkdiv2;
  74. const struct snd_pcm_hw_constraint_list *sysclk_constraints;
  75. const int *mclk_ratios;
  76. bool provider;
  77. struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
  78. };
  79. /*
  80. * ES8328 Controls
  81. */
  82. static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
  83. "L + R Invert"};
  84. static SOC_ENUM_SINGLE_DECL(adcpol,
  85. ES8328_ADCCONTROL6, 6, adcpol_txt);
  86. static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
  87. static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
  88. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  89. static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
  90. static const struct {
  91. int rate;
  92. unsigned int val;
  93. } deemph_settings[] = {
  94. { 0, ES8328_DACCONTROL6_DEEMPH_OFF },
  95. { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
  96. { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
  97. { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
  98. };
  99. static int es8328_set_deemph(struct snd_soc_component *component)
  100. {
  101. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  102. int val, i, best;
  103. /*
  104. * If we're using deemphasis select the nearest available sample
  105. * rate.
  106. */
  107. if (es8328->deemph) {
  108. best = 0;
  109. for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
  110. if (abs(deemph_settings[i].rate - es8328->playback_fs) <
  111. abs(deemph_settings[best].rate - es8328->playback_fs))
  112. best = i;
  113. }
  114. val = deemph_settings[best].val;
  115. } else {
  116. val = ES8328_DACCONTROL6_DEEMPH_OFF;
  117. }
  118. dev_dbg(component->dev, "Set deemphasis %d\n", val);
  119. return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
  120. ES8328_DACCONTROL6_DEEMPH_MASK, val);
  121. }
  122. static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
  123. struct snd_ctl_elem_value *ucontrol)
  124. {
  125. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  126. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  127. ucontrol->value.integer.value[0] = es8328->deemph;
  128. return 0;
  129. }
  130. static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
  131. struct snd_ctl_elem_value *ucontrol)
  132. {
  133. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  134. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  135. unsigned int deemph = ucontrol->value.integer.value[0];
  136. int ret;
  137. if (deemph > 1)
  138. return -EINVAL;
  139. if (es8328->deemph == deemph)
  140. return 0;
  141. ret = es8328_set_deemph(component);
  142. if (ret < 0)
  143. return ret;
  144. es8328->deemph = deemph;
  145. return 1;
  146. }
  147. static const struct snd_kcontrol_new es8328_snd_controls[] = {
  148. SOC_DOUBLE_R_TLV("Capture Digital Volume",
  149. ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
  150. 0, 0xc0, 1, dac_adc_tlv),
  151. SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
  152. SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
  153. es8328_get_deemph, es8328_put_deemph),
  154. SOC_ENUM("Capture Polarity", adcpol),
  155. SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
  156. ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
  157. SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
  158. ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
  159. SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
  160. ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
  161. SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
  162. ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
  163. SOC_DOUBLE_R_TLV("PCM Volume",
  164. ES8328_LDACVOL, ES8328_RDACVOL,
  165. 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
  166. SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
  167. ES8328_LOUT1VOL, ES8328_ROUT1VOL,
  168. 0, ES8328_OUT1VOL_MAX, 0, play_tlv),
  169. SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
  170. ES8328_LOUT2VOL, ES8328_ROUT2VOL,
  171. 0, ES8328_OUT2VOL_MAX, 0, play_tlv),
  172. SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
  173. 4, 0, 8, 0, mic_tlv),
  174. };
  175. /*
  176. * DAPM Controls
  177. */
  178. static const char * const es8328_line_texts[] = {
  179. "Line 1", "Line 2", "PGA", "Differential"};
  180. static const struct soc_enum es8328_lline_enum =
  181. SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
  182. ARRAY_SIZE(es8328_line_texts),
  183. es8328_line_texts);
  184. static const struct snd_kcontrol_new es8328_left_line_controls =
  185. SOC_DAPM_ENUM("Route", es8328_lline_enum);
  186. static const struct soc_enum es8328_rline_enum =
  187. SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
  188. ARRAY_SIZE(es8328_line_texts),
  189. es8328_line_texts);
  190. static const struct snd_kcontrol_new es8328_right_line_controls =
  191. SOC_DAPM_ENUM("Route", es8328_rline_enum);
  192. /* Left Mixer */
  193. static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
  194. SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
  195. SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
  196. SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
  197. SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
  198. };
  199. /* Right Mixer */
  200. static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
  201. SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
  202. SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
  203. SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
  204. SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
  205. };
  206. static const char * const es8328_pga_sel[] = {
  207. "Line 1", "Line 2", "Line 3", "Differential"};
  208. /* Left PGA Mux */
  209. static const struct soc_enum es8328_lpga_enum =
  210. SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
  211. ARRAY_SIZE(es8328_pga_sel),
  212. es8328_pga_sel);
  213. static const struct snd_kcontrol_new es8328_left_pga_controls =
  214. SOC_DAPM_ENUM("Route", es8328_lpga_enum);
  215. /* Right PGA Mux */
  216. static const struct soc_enum es8328_rpga_enum =
  217. SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
  218. ARRAY_SIZE(es8328_pga_sel),
  219. es8328_pga_sel);
  220. static const struct snd_kcontrol_new es8328_right_pga_controls =
  221. SOC_DAPM_ENUM("Route", es8328_rpga_enum);
  222. /* Differential Mux */
  223. static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
  224. static SOC_ENUM_SINGLE_DECL(diffmux,
  225. ES8328_ADCCONTROL3, 7, es8328_diff_sel);
  226. static const struct snd_kcontrol_new es8328_diffmux_controls =
  227. SOC_DAPM_ENUM("Route", diffmux);
  228. /* Mono ADC Mux */
  229. static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
  230. "Mono (Right)", "Digital Mono"};
  231. static SOC_ENUM_SINGLE_DECL(monomux,
  232. ES8328_ADCCONTROL3, 3, es8328_mono_mux);
  233. static const struct snd_kcontrol_new es8328_monomux_controls =
  234. SOC_DAPM_ENUM("Route", monomux);
  235. static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
  236. SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
  237. &es8328_diffmux_controls),
  238. SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
  239. &es8328_monomux_controls),
  240. SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
  241. &es8328_monomux_controls),
  242. SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
  243. ES8328_ADCPOWER_AINL_OFF, 1,
  244. &es8328_left_pga_controls),
  245. SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
  246. ES8328_ADCPOWER_AINR_OFF, 1,
  247. &es8328_right_pga_controls),
  248. SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
  249. &es8328_left_line_controls),
  250. SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
  251. &es8328_right_line_controls),
  252. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
  253. ES8328_ADCPOWER_ADCR_OFF, 1),
  254. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
  255. ES8328_ADCPOWER_ADCL_OFF, 1),
  256. SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
  257. ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
  258. SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
  259. ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
  260. SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
  261. ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
  262. SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
  263. ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
  264. SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
  265. ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
  266. SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
  267. ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
  268. SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
  269. ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
  270. SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
  271. ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
  272. SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
  273. ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
  274. SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
  275. ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
  276. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
  277. ES8328_DACPOWER_RDAC_OFF, 1),
  278. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
  279. ES8328_DACPOWER_LDAC_OFF, 1),
  280. SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
  281. &es8328_left_mixer_controls[0],
  282. ARRAY_SIZE(es8328_left_mixer_controls)),
  283. SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
  284. &es8328_right_mixer_controls[0],
  285. ARRAY_SIZE(es8328_right_mixer_controls)),
  286. SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
  287. ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
  288. SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
  289. ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
  290. SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
  291. ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
  292. SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
  293. ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
  294. SND_SOC_DAPM_OUTPUT("LOUT1"),
  295. SND_SOC_DAPM_OUTPUT("ROUT1"),
  296. SND_SOC_DAPM_OUTPUT("LOUT2"),
  297. SND_SOC_DAPM_OUTPUT("ROUT2"),
  298. SND_SOC_DAPM_INPUT("LINPUT1"),
  299. SND_SOC_DAPM_INPUT("LINPUT2"),
  300. SND_SOC_DAPM_INPUT("RINPUT1"),
  301. SND_SOC_DAPM_INPUT("RINPUT2"),
  302. };
  303. static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
  304. { "Left Line Mux", "Line 1", "LINPUT1" },
  305. { "Left Line Mux", "Line 2", "LINPUT2" },
  306. { "Left Line Mux", "PGA", "Left PGA Mux" },
  307. { "Left Line Mux", "Differential", "Differential Mux" },
  308. { "Right Line Mux", "Line 1", "RINPUT1" },
  309. { "Right Line Mux", "Line 2", "RINPUT2" },
  310. { "Right Line Mux", "PGA", "Right PGA Mux" },
  311. { "Right Line Mux", "Differential", "Differential Mux" },
  312. { "Left PGA Mux", "Line 1", "LINPUT1" },
  313. { "Left PGA Mux", "Line 2", "LINPUT2" },
  314. { "Left PGA Mux", "Differential", "Differential Mux" },
  315. { "Right PGA Mux", "Line 1", "RINPUT1" },
  316. { "Right PGA Mux", "Line 2", "RINPUT2" },
  317. { "Right PGA Mux", "Differential", "Differential Mux" },
  318. { "Differential Mux", "Line 1", "LINPUT1" },
  319. { "Differential Mux", "Line 1", "RINPUT1" },
  320. { "Differential Mux", "Line 2", "LINPUT2" },
  321. { "Differential Mux", "Line 2", "RINPUT2" },
  322. { "Left ADC Mux", "Stereo", "Left PGA Mux" },
  323. { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
  324. { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
  325. { "Right ADC Mux", "Stereo", "Right PGA Mux" },
  326. { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
  327. { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
  328. { "Left ADC", NULL, "Left ADC Mux" },
  329. { "Right ADC", NULL, "Right ADC Mux" },
  330. { "ADC DIG", NULL, "ADC STM" },
  331. { "ADC DIG", NULL, "ADC Vref" },
  332. { "ADC DIG", NULL, "ADC DLL" },
  333. { "Left ADC", NULL, "ADC DIG" },
  334. { "Right ADC", NULL, "ADC DIG" },
  335. { "Mic Bias", NULL, "Mic Bias Gen" },
  336. { "Left Line Mux", "Line 1", "LINPUT1" },
  337. { "Left Line Mux", "Line 2", "LINPUT2" },
  338. { "Left Line Mux", "PGA", "Left PGA Mux" },
  339. { "Left Line Mux", "Differential", "Differential Mux" },
  340. { "Right Line Mux", "Line 1", "RINPUT1" },
  341. { "Right Line Mux", "Line 2", "RINPUT2" },
  342. { "Right Line Mux", "PGA", "Right PGA Mux" },
  343. { "Right Line Mux", "Differential", "Differential Mux" },
  344. { "Left Out 1", NULL, "Left DAC" },
  345. { "Right Out 1", NULL, "Right DAC" },
  346. { "Left Out 2", NULL, "Left DAC" },
  347. { "Right Out 2", NULL, "Right DAC" },
  348. { "Left Mixer", "Playback Switch", "Left DAC" },
  349. { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
  350. { "Left Mixer", "Right Playback Switch", "Right DAC" },
  351. { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
  352. { "Right Mixer", "Left Playback Switch", "Left DAC" },
  353. { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
  354. { "Right Mixer", "Playback Switch", "Right DAC" },
  355. { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
  356. { "DAC DIG", NULL, "DAC STM" },
  357. { "DAC DIG", NULL, "DAC Vref" },
  358. { "DAC DIG", NULL, "DAC DLL" },
  359. { "Left DAC", NULL, "DAC DIG" },
  360. { "Right DAC", NULL, "DAC DIG" },
  361. { "Left Out 1", NULL, "Left Mixer" },
  362. { "LOUT1", NULL, "Left Out 1" },
  363. { "Right Out 1", NULL, "Right Mixer" },
  364. { "ROUT1", NULL, "Right Out 1" },
  365. { "Left Out 2", NULL, "Left Mixer" },
  366. { "LOUT2", NULL, "Left Out 2" },
  367. { "Right Out 2", NULL, "Right Mixer" },
  368. { "ROUT2", NULL, "Right Out 2" },
  369. };
  370. static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
  371. {
  372. return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
  373. ES8328_DACCONTROL3_DACMUTE,
  374. mute ? ES8328_DACCONTROL3_DACMUTE : 0);
  375. }
  376. static int es8328_startup(struct snd_pcm_substream *substream,
  377. struct snd_soc_dai *dai)
  378. {
  379. struct snd_soc_component *component = dai->component;
  380. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  381. if (es8328->provider && es8328->sysclk_constraints)
  382. snd_pcm_hw_constraint_list(substream->runtime, 0,
  383. SNDRV_PCM_HW_PARAM_RATE,
  384. es8328->sysclk_constraints);
  385. return 0;
  386. }
  387. static int es8328_hw_params(struct snd_pcm_substream *substream,
  388. struct snd_pcm_hw_params *params,
  389. struct snd_soc_dai *dai)
  390. {
  391. struct snd_soc_component *component = dai->component;
  392. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  393. int i;
  394. int reg;
  395. int wl;
  396. int ratio;
  397. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  398. reg = ES8328_DACCONTROL2;
  399. else
  400. reg = ES8328_ADCCONTROL5;
  401. if (es8328->provider) {
  402. if (!es8328->sysclk_constraints) {
  403. dev_err(component->dev, "No MCLK configured\n");
  404. return -EINVAL;
  405. }
  406. for (i = 0; i < es8328->sysclk_constraints->count; i++)
  407. if (es8328->sysclk_constraints->list[i] ==
  408. params_rate(params))
  409. break;
  410. if (i == es8328->sysclk_constraints->count) {
  411. dev_err(component->dev,
  412. "LRCLK %d unsupported with current clock\n",
  413. params_rate(params));
  414. return -EINVAL;
  415. }
  416. ratio = es8328->mclk_ratios[i];
  417. } else {
  418. ratio = 0;
  419. es8328->mclkdiv2 = 0;
  420. }
  421. snd_soc_component_update_bits(component, ES8328_MASTERMODE,
  422. ES8328_MASTERMODE_MCLKDIV2,
  423. es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
  424. switch (params_width(params)) {
  425. case 16:
  426. wl = 3;
  427. break;
  428. case 18:
  429. wl = 2;
  430. break;
  431. case 20:
  432. wl = 1;
  433. break;
  434. case 24:
  435. wl = 0;
  436. break;
  437. case 32:
  438. wl = 4;
  439. break;
  440. default:
  441. return -EINVAL;
  442. }
  443. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  444. snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
  445. ES8328_DACCONTROL1_DACWL_MASK,
  446. wl << ES8328_DACCONTROL1_DACWL_SHIFT);
  447. es8328->playback_fs = params_rate(params);
  448. es8328_set_deemph(component);
  449. } else
  450. snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
  451. ES8328_ADCCONTROL4_ADCWL_MASK,
  452. wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
  453. return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
  454. }
  455. static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
  456. int clk_id, unsigned int freq, int dir)
  457. {
  458. struct snd_soc_component *component = codec_dai->component;
  459. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  460. int mclkdiv2 = 0;
  461. switch (freq) {
  462. case 0:
  463. es8328->sysclk_constraints = NULL;
  464. es8328->mclk_ratios = NULL;
  465. break;
  466. case 22579200:
  467. mclkdiv2 = 1;
  468. fallthrough;
  469. case 11289600:
  470. es8328->sysclk_constraints = &constraints_11289;
  471. es8328->mclk_ratios = ratios_11289;
  472. break;
  473. case 24576000:
  474. mclkdiv2 = 1;
  475. fallthrough;
  476. case 12288000:
  477. es8328->sysclk_constraints = &constraints_12288;
  478. es8328->mclk_ratios = ratios_12288;
  479. break;
  480. default:
  481. return -EINVAL;
  482. }
  483. es8328->mclkdiv2 = mclkdiv2;
  484. return 0;
  485. }
  486. static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
  487. unsigned int fmt)
  488. {
  489. struct snd_soc_component *component = codec_dai->component;
  490. struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
  491. u8 dac_mode = 0;
  492. u8 adc_mode = 0;
  493. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  494. case SND_SOC_DAIFMT_CBP_CFP:
  495. /* Master serial port mode, with BCLK generated automatically */
  496. snd_soc_component_update_bits(component, ES8328_MASTERMODE,
  497. ES8328_MASTERMODE_MSC,
  498. ES8328_MASTERMODE_MSC);
  499. es8328->provider = true;
  500. break;
  501. case SND_SOC_DAIFMT_CBC_CFC:
  502. /* Slave serial port mode */
  503. snd_soc_component_update_bits(component, ES8328_MASTERMODE,
  504. ES8328_MASTERMODE_MSC, 0);
  505. es8328->provider = false;
  506. break;
  507. default:
  508. return -EINVAL;
  509. }
  510. /* interface format */
  511. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  512. case SND_SOC_DAIFMT_I2S:
  513. dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
  514. adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
  515. break;
  516. case SND_SOC_DAIFMT_RIGHT_J:
  517. dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
  518. adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
  519. break;
  520. case SND_SOC_DAIFMT_LEFT_J:
  521. dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
  522. adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
  523. break;
  524. default:
  525. return -EINVAL;
  526. }
  527. /* clock inversion */
  528. if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
  529. return -EINVAL;
  530. snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
  531. ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
  532. snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
  533. ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
  534. return 0;
  535. }
  536. static int es8328_set_bias_level(struct snd_soc_component *component,
  537. enum snd_soc_bias_level level)
  538. {
  539. switch (level) {
  540. case SND_SOC_BIAS_ON:
  541. break;
  542. case SND_SOC_BIAS_PREPARE:
  543. /* VREF, VMID=2x50k, digital enabled */
  544. snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
  545. snd_soc_component_update_bits(component, ES8328_CONTROL1,
  546. ES8328_CONTROL1_VMIDSEL_MASK |
  547. ES8328_CONTROL1_ENREF,
  548. ES8328_CONTROL1_VMIDSEL_50k |
  549. ES8328_CONTROL1_ENREF);
  550. break;
  551. case SND_SOC_BIAS_STANDBY:
  552. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  553. snd_soc_component_update_bits(component, ES8328_CONTROL1,
  554. ES8328_CONTROL1_VMIDSEL_MASK |
  555. ES8328_CONTROL1_ENREF,
  556. ES8328_CONTROL1_VMIDSEL_5k |
  557. ES8328_CONTROL1_ENREF);
  558. /* Charge caps */
  559. msleep(100);
  560. }
  561. snd_soc_component_write(component, ES8328_CONTROL2,
  562. ES8328_CONTROL2_OVERCURRENT_ON |
  563. ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
  564. /* VREF, VMID=2*500k, digital stopped */
  565. snd_soc_component_update_bits(component, ES8328_CONTROL1,
  566. ES8328_CONTROL1_VMIDSEL_MASK |
  567. ES8328_CONTROL1_ENREF,
  568. ES8328_CONTROL1_VMIDSEL_500k |
  569. ES8328_CONTROL1_ENREF);
  570. break;
  571. case SND_SOC_BIAS_OFF:
  572. snd_soc_component_update_bits(component, ES8328_CONTROL1,
  573. ES8328_CONTROL1_VMIDSEL_MASK |
  574. ES8328_CONTROL1_ENREF,
  575. 0);
  576. break;
  577. }
  578. return 0;
  579. }
  580. static const struct snd_soc_dai_ops es8328_dai_ops = {
  581. .startup = es8328_startup,
  582. .hw_params = es8328_hw_params,
  583. .mute_stream = es8328_mute,
  584. .set_sysclk = es8328_set_sysclk,
  585. .set_fmt = es8328_set_dai_fmt,
  586. .no_capture_mute = 1,
  587. };
  588. static struct snd_soc_dai_driver es8328_dai = {
  589. .name = "es8328-hifi-analog",
  590. .playback = {
  591. .stream_name = "Playback",
  592. .channels_min = 2,
  593. .channels_max = 2,
  594. .rates = ES8328_RATES,
  595. .formats = ES8328_FORMATS,
  596. },
  597. .capture = {
  598. .stream_name = "Capture",
  599. .channels_min = 2,
  600. .channels_max = 2,
  601. .rates = ES8328_RATES,
  602. .formats = ES8328_FORMATS,
  603. },
  604. .ops = &es8328_dai_ops,
  605. .symmetric_rate = 1,
  606. };
  607. static int es8328_suspend(struct snd_soc_component *component)
  608. {
  609. struct es8328_priv *es8328;
  610. int ret;
  611. es8328 = snd_soc_component_get_drvdata(component);
  612. clk_disable_unprepare(es8328->clk);
  613. ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
  614. es8328->supplies);
  615. if (ret) {
  616. dev_err(component->dev, "unable to disable regulators\n");
  617. return ret;
  618. }
  619. return 0;
  620. }
  621. static int es8328_resume(struct snd_soc_component *component)
  622. {
  623. struct regmap *regmap = dev_get_regmap(component->dev, NULL);
  624. struct es8328_priv *es8328;
  625. int ret;
  626. es8328 = snd_soc_component_get_drvdata(component);
  627. ret = clk_prepare_enable(es8328->clk);
  628. if (ret) {
  629. dev_err(component->dev, "unable to enable clock\n");
  630. return ret;
  631. }
  632. ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
  633. es8328->supplies);
  634. if (ret) {
  635. dev_err(component->dev, "unable to enable regulators\n");
  636. return ret;
  637. }
  638. regcache_mark_dirty(regmap);
  639. ret = regcache_sync(regmap);
  640. if (ret) {
  641. dev_err(component->dev, "unable to sync regcache\n");
  642. return ret;
  643. }
  644. return 0;
  645. }
  646. static int es8328_component_probe(struct snd_soc_component *component)
  647. {
  648. struct es8328_priv *es8328;
  649. int ret;
  650. es8328 = snd_soc_component_get_drvdata(component);
  651. ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
  652. es8328->supplies);
  653. if (ret) {
  654. dev_err(component->dev, "unable to enable regulators\n");
  655. return ret;
  656. }
  657. /* Setup clocks */
  658. es8328->clk = devm_clk_get(component->dev, NULL);
  659. if (IS_ERR(es8328->clk)) {
  660. dev_err(component->dev, "codec clock missing or invalid\n");
  661. ret = PTR_ERR(es8328->clk);
  662. goto clk_fail;
  663. }
  664. ret = clk_prepare_enable(es8328->clk);
  665. if (ret) {
  666. dev_err(component->dev, "unable to prepare codec clk\n");
  667. goto clk_fail;
  668. }
  669. return 0;
  670. clk_fail:
  671. regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
  672. es8328->supplies);
  673. return ret;
  674. }
  675. static void es8328_remove(struct snd_soc_component *component)
  676. {
  677. struct es8328_priv *es8328;
  678. es8328 = snd_soc_component_get_drvdata(component);
  679. clk_disable_unprepare(es8328->clk);
  680. regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
  681. es8328->supplies);
  682. }
  683. const struct regmap_config es8328_regmap_config = {
  684. .reg_bits = 8,
  685. .val_bits = 8,
  686. .max_register = ES8328_REG_MAX,
  687. .cache_type = REGCACHE_RBTREE,
  688. .use_single_read = true,
  689. .use_single_write = true,
  690. };
  691. EXPORT_SYMBOL_GPL(es8328_regmap_config);
  692. static const struct snd_soc_component_driver es8328_component_driver = {
  693. .probe = es8328_component_probe,
  694. .remove = es8328_remove,
  695. .suspend = es8328_suspend,
  696. .resume = es8328_resume,
  697. .set_bias_level = es8328_set_bias_level,
  698. .controls = es8328_snd_controls,
  699. .num_controls = ARRAY_SIZE(es8328_snd_controls),
  700. .dapm_widgets = es8328_dapm_widgets,
  701. .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
  702. .dapm_routes = es8328_dapm_routes,
  703. .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
  704. .suspend_bias_off = 1,
  705. .idle_bias_on = 1,
  706. .use_pmdown_time = 1,
  707. .endianness = 1,
  708. };
  709. int es8328_probe(struct device *dev, struct regmap *regmap)
  710. {
  711. struct es8328_priv *es8328;
  712. int ret;
  713. int i;
  714. if (IS_ERR(regmap))
  715. return PTR_ERR(regmap);
  716. es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
  717. if (es8328 == NULL)
  718. return -ENOMEM;
  719. es8328->regmap = regmap;
  720. for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
  721. es8328->supplies[i].supply = supply_names[i];
  722. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
  723. es8328->supplies);
  724. if (ret) {
  725. dev_err(dev, "unable to get regulators\n");
  726. return ret;
  727. }
  728. dev_set_drvdata(dev, es8328);
  729. return devm_snd_soc_register_component(dev,
  730. &es8328_component_driver, &es8328_dai, 1);
  731. }
  732. EXPORT_SYMBOL_GPL(es8328_probe);
  733. MODULE_DESCRIPTION("ASoC ES8328 driver");
  734. MODULE_AUTHOR("Sean Cross <[email protected]>");
  735. MODULE_LICENSE("GPL");