cs35l32.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cs35l32.c -- CS35L32 ALSA SoC audio driver
  4. *
  5. * Copyright 2014 CirrusLogic, Inc.
  6. *
  7. * Author: Brian Austin <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/i2c.h>
  15. #include <linux/gpio.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/gpio/consumer.h>
  21. #include <linux/of_device.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <dt-bindings/sound/cs35l32.h>
  30. #include "cs35l32.h"
  31. #include "cirrus_legacy.h"
  32. #define CS35L32_NUM_SUPPLIES 2
  33. static const char *const cs35l32_supply_names[CS35L32_NUM_SUPPLIES] = {
  34. "VA",
  35. "VP",
  36. };
  37. struct cs35l32_private {
  38. struct regmap *regmap;
  39. struct snd_soc_component *component;
  40. struct regulator_bulk_data supplies[CS35L32_NUM_SUPPLIES];
  41. struct cs35l32_platform_data pdata;
  42. struct gpio_desc *reset_gpio;
  43. };
  44. static const struct reg_default cs35l32_reg_defaults[] = {
  45. { 0x06, 0x04 }, /* Power Ctl 1 */
  46. { 0x07, 0xE8 }, /* Power Ctl 2 */
  47. { 0x08, 0x40 }, /* Clock Ctl */
  48. { 0x09, 0x20 }, /* Low Battery Threshold */
  49. { 0x0A, 0x00 }, /* Voltage Monitor [RO] */
  50. { 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
  51. { 0x0C, 0x07 }, /* IMON Scaling */
  52. { 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
  53. { 0x0F, 0x20 }, /* Serial Port Control */
  54. { 0x10, 0x14 }, /* Class D Amp CTL */
  55. { 0x11, 0x00 }, /* Protection Release CTL */
  56. { 0x12, 0xFF }, /* Interrupt Mask 1 */
  57. { 0x13, 0xFF }, /* Interrupt Mask 2 */
  58. { 0x14, 0xFF }, /* Interrupt Mask 3 */
  59. { 0x19, 0x00 }, /* LED Flash Mode Current */
  60. { 0x1A, 0x00 }, /* LED Movie Mode Current */
  61. { 0x1B, 0x20 }, /* LED Flash Timer */
  62. { 0x1C, 0x00 }, /* LED Flash Inhibit Current */
  63. };
  64. static bool cs35l32_readable_register(struct device *dev, unsigned int reg)
  65. {
  66. switch (reg) {
  67. case CS35L32_DEVID_AB ... CS35L32_AUDIO_LED_MNGR:
  68. case CS35L32_ADSP_CTL ... CS35L32_FLASH_INHIBIT:
  69. return true;
  70. default:
  71. return false;
  72. }
  73. }
  74. static bool cs35l32_volatile_register(struct device *dev, unsigned int reg)
  75. {
  76. switch (reg) {
  77. case CS35L32_DEVID_AB ... CS35L32_REV_ID:
  78. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  79. return true;
  80. default:
  81. return false;
  82. }
  83. }
  84. static bool cs35l32_precious_register(struct device *dev, unsigned int reg)
  85. {
  86. switch (reg) {
  87. case CS35L32_INT_STATUS_1 ... CS35L32_LED_STATUS:
  88. return true;
  89. default:
  90. return false;
  91. }
  92. }
  93. static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 300, 0);
  94. static const struct snd_kcontrol_new imon_ctl =
  95. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 6, 1, 1);
  96. static const struct snd_kcontrol_new vmon_ctl =
  97. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 7, 1, 1);
  98. static const struct snd_kcontrol_new vpmon_ctl =
  99. SOC_DAPM_SINGLE("Switch", CS35L32_PWRCTL2, 5, 1, 1);
  100. static const struct snd_kcontrol_new cs35l32_snd_controls[] = {
  101. SOC_SINGLE_TLV("Speaker Volume", CS35L32_CLASSD_CTL,
  102. 3, 0x04, 1, classd_ctl_tlv),
  103. SOC_SINGLE("Zero Cross Switch", CS35L32_CLASSD_CTL, 2, 1, 0),
  104. SOC_SINGLE("Gain Manager Switch", CS35L32_AUDIO_LED_MNGR, 3, 1, 0),
  105. };
  106. static const struct snd_soc_dapm_widget cs35l32_dapm_widgets[] = {
  107. SND_SOC_DAPM_SUPPLY("BOOST", CS35L32_PWRCTL1, 2, 1, NULL, 0),
  108. SND_SOC_DAPM_OUT_DRV("Speaker", CS35L32_PWRCTL1, 7, 1, NULL, 0),
  109. SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L32_PWRCTL2, 3, 1),
  110. SND_SOC_DAPM_INPUT("VP"),
  111. SND_SOC_DAPM_INPUT("ISENSE"),
  112. SND_SOC_DAPM_INPUT("VSENSE"),
  113. SND_SOC_DAPM_SWITCH("VMON ADC", CS35L32_PWRCTL2, 7, 1, &vmon_ctl),
  114. SND_SOC_DAPM_SWITCH("IMON ADC", CS35L32_PWRCTL2, 6, 1, &imon_ctl),
  115. SND_SOC_DAPM_SWITCH("VPMON ADC", CS35L32_PWRCTL2, 5, 1, &vpmon_ctl),
  116. };
  117. static const struct snd_soc_dapm_route cs35l32_audio_map[] = {
  118. {"Speaker", NULL, "BOOST"},
  119. {"VMON ADC", NULL, "VSENSE"},
  120. {"IMON ADC", NULL, "ISENSE"},
  121. {"VPMON ADC", NULL, "VP"},
  122. {"SDOUT", "Switch", "VMON ADC"},
  123. {"SDOUT", "Switch", "IMON ADC"},
  124. {"SDOUT", "Switch", "VPMON ADC"},
  125. {"Capture", NULL, "SDOUT"},
  126. };
  127. static int cs35l32_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  128. {
  129. struct snd_soc_component *component = codec_dai->component;
  130. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  131. case SND_SOC_DAIFMT_CBM_CFM:
  132. snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
  133. CS35L32_ADSP_MASTER_MASK,
  134. CS35L32_ADSP_MASTER_MASK);
  135. break;
  136. case SND_SOC_DAIFMT_CBS_CFS:
  137. snd_soc_component_update_bits(component, CS35L32_ADSP_CTL,
  138. CS35L32_ADSP_MASTER_MASK, 0);
  139. break;
  140. default:
  141. return -EINVAL;
  142. }
  143. return 0;
  144. }
  145. static int cs35l32_set_tristate(struct snd_soc_dai *dai, int tristate)
  146. {
  147. struct snd_soc_component *component = dai->component;
  148. return snd_soc_component_update_bits(component, CS35L32_PWRCTL2,
  149. CS35L32_SDOUT_3ST, tristate << 3);
  150. }
  151. static const struct snd_soc_dai_ops cs35l32_ops = {
  152. .set_fmt = cs35l32_set_dai_fmt,
  153. .set_tristate = cs35l32_set_tristate,
  154. };
  155. static struct snd_soc_dai_driver cs35l32_dai[] = {
  156. {
  157. .name = "cs35l32-monitor",
  158. .id = 0,
  159. .capture = {
  160. .stream_name = "Capture",
  161. .channels_min = 2,
  162. .channels_max = 2,
  163. .rates = CS35L32_RATES,
  164. .formats = CS35L32_FORMATS,
  165. },
  166. .ops = &cs35l32_ops,
  167. .symmetric_rate = 1,
  168. }
  169. };
  170. static int cs35l32_component_set_sysclk(struct snd_soc_component *component,
  171. int clk_id, int source, unsigned int freq, int dir)
  172. {
  173. unsigned int val;
  174. switch (freq) {
  175. case 6000000:
  176. val = CS35L32_MCLK_RATIO;
  177. break;
  178. case 12000000:
  179. val = CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO;
  180. break;
  181. case 6144000:
  182. val = 0;
  183. break;
  184. case 12288000:
  185. val = CS35L32_MCLK_DIV2_MASK;
  186. break;
  187. default:
  188. return -EINVAL;
  189. }
  190. return snd_soc_component_update_bits(component, CS35L32_CLK_CTL,
  191. CS35L32_MCLK_DIV2_MASK | CS35L32_MCLK_RATIO_MASK, val);
  192. }
  193. static const struct snd_soc_component_driver soc_component_dev_cs35l32 = {
  194. .set_sysclk = cs35l32_component_set_sysclk,
  195. .controls = cs35l32_snd_controls,
  196. .num_controls = ARRAY_SIZE(cs35l32_snd_controls),
  197. .dapm_widgets = cs35l32_dapm_widgets,
  198. .num_dapm_widgets = ARRAY_SIZE(cs35l32_dapm_widgets),
  199. .dapm_routes = cs35l32_audio_map,
  200. .num_dapm_routes = ARRAY_SIZE(cs35l32_audio_map),
  201. .idle_bias_on = 1,
  202. .use_pmdown_time = 1,
  203. .endianness = 1,
  204. };
  205. /* Current and threshold powerup sequence Pg37 in datasheet */
  206. static const struct reg_sequence cs35l32_monitor_patch[] = {
  207. { 0x00, 0x99 },
  208. { 0x48, 0x17 },
  209. { 0x49, 0x56 },
  210. { 0x43, 0x01 },
  211. { 0x3B, 0x62 },
  212. { 0x3C, 0x80 },
  213. { 0x00, 0x00 },
  214. };
  215. static const struct regmap_config cs35l32_regmap = {
  216. .reg_bits = 8,
  217. .val_bits = 8,
  218. .max_register = CS35L32_MAX_REGISTER,
  219. .reg_defaults = cs35l32_reg_defaults,
  220. .num_reg_defaults = ARRAY_SIZE(cs35l32_reg_defaults),
  221. .volatile_reg = cs35l32_volatile_register,
  222. .readable_reg = cs35l32_readable_register,
  223. .precious_reg = cs35l32_precious_register,
  224. .cache_type = REGCACHE_RBTREE,
  225. .use_single_read = true,
  226. .use_single_write = true,
  227. };
  228. static int cs35l32_handle_of_data(struct i2c_client *i2c_client,
  229. struct cs35l32_platform_data *pdata)
  230. {
  231. struct device_node *np = i2c_client->dev.of_node;
  232. unsigned int val;
  233. if (of_property_read_u32(np, "cirrus,sdout-share", &val) >= 0)
  234. pdata->sdout_share = val;
  235. if (of_property_read_u32(np, "cirrus,boost-manager", &val))
  236. val = -1u;
  237. switch (val) {
  238. case CS35L32_BOOST_MGR_AUTO:
  239. case CS35L32_BOOST_MGR_AUTO_AUDIO:
  240. case CS35L32_BOOST_MGR_BYPASS:
  241. case CS35L32_BOOST_MGR_FIXED:
  242. pdata->boost_mng = val;
  243. break;
  244. case -1u:
  245. default:
  246. dev_err(&i2c_client->dev,
  247. "Wrong cirrus,boost-manager DT value %d\n", val);
  248. pdata->boost_mng = CS35L32_BOOST_MGR_BYPASS;
  249. }
  250. if (of_property_read_u32(np, "cirrus,sdout-datacfg", &val))
  251. val = -1u;
  252. switch (val) {
  253. case CS35L32_DATA_CFG_LR_VP:
  254. case CS35L32_DATA_CFG_LR_STAT:
  255. case CS35L32_DATA_CFG_LR:
  256. case CS35L32_DATA_CFG_LR_VPSTAT:
  257. pdata->sdout_datacfg = val;
  258. break;
  259. case -1u:
  260. default:
  261. dev_err(&i2c_client->dev,
  262. "Wrong cirrus,sdout-datacfg DT value %d\n", val);
  263. pdata->sdout_datacfg = CS35L32_DATA_CFG_LR;
  264. }
  265. if (of_property_read_u32(np, "cirrus,battery-threshold", &val))
  266. val = -1u;
  267. switch (val) {
  268. case CS35L32_BATT_THRESH_3_1V:
  269. case CS35L32_BATT_THRESH_3_2V:
  270. case CS35L32_BATT_THRESH_3_3V:
  271. case CS35L32_BATT_THRESH_3_4V:
  272. pdata->batt_thresh = val;
  273. break;
  274. case -1u:
  275. default:
  276. dev_err(&i2c_client->dev,
  277. "Wrong cirrus,battery-threshold DT value %d\n", val);
  278. pdata->batt_thresh = CS35L32_BATT_THRESH_3_3V;
  279. }
  280. if (of_property_read_u32(np, "cirrus,battery-recovery", &val))
  281. val = -1u;
  282. switch (val) {
  283. case CS35L32_BATT_RECOV_3_1V:
  284. case CS35L32_BATT_RECOV_3_2V:
  285. case CS35L32_BATT_RECOV_3_3V:
  286. case CS35L32_BATT_RECOV_3_4V:
  287. case CS35L32_BATT_RECOV_3_5V:
  288. case CS35L32_BATT_RECOV_3_6V:
  289. pdata->batt_recov = val;
  290. break;
  291. case -1u:
  292. default:
  293. dev_err(&i2c_client->dev,
  294. "Wrong cirrus,battery-recovery DT value %d\n", val);
  295. pdata->batt_recov = CS35L32_BATT_RECOV_3_4V;
  296. }
  297. return 0;
  298. }
  299. static int cs35l32_i2c_probe(struct i2c_client *i2c_client)
  300. {
  301. struct cs35l32_private *cs35l32;
  302. struct cs35l32_platform_data *pdata =
  303. dev_get_platdata(&i2c_client->dev);
  304. int ret, i, devid;
  305. unsigned int reg;
  306. cs35l32 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l32), GFP_KERNEL);
  307. if (!cs35l32)
  308. return -ENOMEM;
  309. i2c_set_clientdata(i2c_client, cs35l32);
  310. cs35l32->regmap = devm_regmap_init_i2c(i2c_client, &cs35l32_regmap);
  311. if (IS_ERR(cs35l32->regmap)) {
  312. ret = PTR_ERR(cs35l32->regmap);
  313. dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
  314. return ret;
  315. }
  316. if (pdata) {
  317. cs35l32->pdata = *pdata;
  318. } else {
  319. pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
  320. GFP_KERNEL);
  321. if (!pdata)
  322. return -ENOMEM;
  323. if (i2c_client->dev.of_node) {
  324. ret = cs35l32_handle_of_data(i2c_client,
  325. &cs35l32->pdata);
  326. if (ret != 0)
  327. return ret;
  328. }
  329. }
  330. for (i = 0; i < ARRAY_SIZE(cs35l32->supplies); i++)
  331. cs35l32->supplies[i].supply = cs35l32_supply_names[i];
  332. ret = devm_regulator_bulk_get(&i2c_client->dev,
  333. ARRAY_SIZE(cs35l32->supplies),
  334. cs35l32->supplies);
  335. if (ret != 0) {
  336. dev_err(&i2c_client->dev,
  337. "Failed to request supplies: %d\n", ret);
  338. return ret;
  339. }
  340. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  341. cs35l32->supplies);
  342. if (ret != 0) {
  343. dev_err(&i2c_client->dev,
  344. "Failed to enable supplies: %d\n", ret);
  345. return ret;
  346. }
  347. /* Reset the Device */
  348. cs35l32->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
  349. "reset", GPIOD_OUT_LOW);
  350. if (IS_ERR(cs35l32->reset_gpio)) {
  351. ret = PTR_ERR(cs35l32->reset_gpio);
  352. goto err_supplies;
  353. }
  354. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  355. /* initialize codec */
  356. devid = cirrus_read_device_id(cs35l32->regmap, CS35L32_DEVID_AB);
  357. if (devid < 0) {
  358. ret = devid;
  359. dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
  360. goto err_disable;
  361. }
  362. if (devid != CS35L32_CHIP_ID) {
  363. ret = -ENODEV;
  364. dev_err(&i2c_client->dev,
  365. "CS35L32 Device ID (%X). Expected %X\n",
  366. devid, CS35L32_CHIP_ID);
  367. goto err_disable;
  368. }
  369. ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, &reg);
  370. if (ret < 0) {
  371. dev_err(&i2c_client->dev, "Get Revision ID failed\n");
  372. goto err_disable;
  373. }
  374. ret = regmap_register_patch(cs35l32->regmap, cs35l32_monitor_patch,
  375. ARRAY_SIZE(cs35l32_monitor_patch));
  376. if (ret < 0) {
  377. dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
  378. goto err_disable;
  379. }
  380. dev_info(&i2c_client->dev,
  381. "Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF);
  382. /* Setup VBOOST Management */
  383. if (cs35l32->pdata.boost_mng)
  384. regmap_update_bits(cs35l32->regmap, CS35L32_AUDIO_LED_MNGR,
  385. CS35L32_BOOST_MASK,
  386. cs35l32->pdata.boost_mng);
  387. /* Setup ADSP Format Config */
  388. if (cs35l32->pdata.sdout_share)
  389. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  390. CS35L32_ADSP_SHARE_MASK,
  391. cs35l32->pdata.sdout_share << 3);
  392. /* Setup ADSP Data Configuration */
  393. if (cs35l32->pdata.sdout_datacfg)
  394. regmap_update_bits(cs35l32->regmap, CS35L32_ADSP_CTL,
  395. CS35L32_ADSP_DATACFG_MASK,
  396. cs35l32->pdata.sdout_datacfg << 4);
  397. /* Setup Low Battery Recovery */
  398. if (cs35l32->pdata.batt_recov)
  399. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  400. CS35L32_BATT_REC_MASK,
  401. cs35l32->pdata.batt_recov << 1);
  402. /* Setup Low Battery Threshold */
  403. if (cs35l32->pdata.batt_thresh)
  404. regmap_update_bits(cs35l32->regmap, CS35L32_BATT_THRESHOLD,
  405. CS35L32_BATT_THRESH_MASK,
  406. cs35l32->pdata.batt_thresh << 4);
  407. /* Power down the AMP */
  408. regmap_update_bits(cs35l32->regmap, CS35L32_PWRCTL1, CS35L32_PDN_AMP,
  409. CS35L32_PDN_AMP);
  410. /* Clear MCLK Error Bit since we don't have the clock yet */
  411. regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, &reg);
  412. ret = devm_snd_soc_register_component(&i2c_client->dev,
  413. &soc_component_dev_cs35l32, cs35l32_dai,
  414. ARRAY_SIZE(cs35l32_dai));
  415. if (ret < 0)
  416. goto err_disable;
  417. return 0;
  418. err_disable:
  419. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  420. err_supplies:
  421. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  422. cs35l32->supplies);
  423. return ret;
  424. }
  425. static void cs35l32_i2c_remove(struct i2c_client *i2c_client)
  426. {
  427. struct cs35l32_private *cs35l32 = i2c_get_clientdata(i2c_client);
  428. /* Hold down reset */
  429. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  430. }
  431. #ifdef CONFIG_PM
  432. static int cs35l32_runtime_suspend(struct device *dev)
  433. {
  434. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  435. regcache_cache_only(cs35l32->regmap, true);
  436. regcache_mark_dirty(cs35l32->regmap);
  437. /* Hold down reset */
  438. gpiod_set_value_cansleep(cs35l32->reset_gpio, 0);
  439. /* remove power */
  440. regulator_bulk_disable(ARRAY_SIZE(cs35l32->supplies),
  441. cs35l32->supplies);
  442. return 0;
  443. }
  444. static int cs35l32_runtime_resume(struct device *dev)
  445. {
  446. struct cs35l32_private *cs35l32 = dev_get_drvdata(dev);
  447. int ret;
  448. /* Enable power */
  449. ret = regulator_bulk_enable(ARRAY_SIZE(cs35l32->supplies),
  450. cs35l32->supplies);
  451. if (ret != 0) {
  452. dev_err(dev, "Failed to enable supplies: %d\n",
  453. ret);
  454. return ret;
  455. }
  456. gpiod_set_value_cansleep(cs35l32->reset_gpio, 1);
  457. regcache_cache_only(cs35l32->regmap, false);
  458. regcache_sync(cs35l32->regmap);
  459. return 0;
  460. }
  461. #endif
  462. static const struct dev_pm_ops cs35l32_runtime_pm = {
  463. SET_RUNTIME_PM_OPS(cs35l32_runtime_suspend, cs35l32_runtime_resume,
  464. NULL)
  465. };
  466. static const struct of_device_id cs35l32_of_match[] = {
  467. { .compatible = "cirrus,cs35l32", },
  468. {},
  469. };
  470. MODULE_DEVICE_TABLE(of, cs35l32_of_match);
  471. static const struct i2c_device_id cs35l32_id[] = {
  472. {"cs35l32", 0},
  473. {}
  474. };
  475. MODULE_DEVICE_TABLE(i2c, cs35l32_id);
  476. static struct i2c_driver cs35l32_i2c_driver = {
  477. .driver = {
  478. .name = "cs35l32",
  479. .pm = &cs35l32_runtime_pm,
  480. .of_match_table = cs35l32_of_match,
  481. },
  482. .id_table = cs35l32_id,
  483. .probe_new = cs35l32_i2c_probe,
  484. .remove = cs35l32_i2c_remove,
  485. };
  486. module_i2c_driver(cs35l32_i2c_driver);
  487. MODULE_DESCRIPTION("ASoC CS35L32 driver");
  488. MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
  489. MODULE_LICENSE("GPL");