ak4375.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Based on code by Hu Jin
  4. * Copyright (C) 2014 Asahi Kasei Microdevices Corporation
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/gpio/consumer.h>
  8. #include <linux/i2c.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <sound/soc.h>
  14. #include <sound/tlv.h>
  15. /* Registers and fields */
  16. #define AK4375_00_POWER_MANAGEMENT1 0x00
  17. #define PMPLL BIT(0) /* 0: PLL off, 1: PLL on */
  18. #define AK4375_01_POWER_MANAGEMENT2 0x01
  19. #define PMCP1 BIT(0) /* Charge Pump 1: LDO1 and DAC */
  20. #define PMCP2 BIT(1) /* Charge Pump 2: Class-G HP Amp */
  21. #define PMLDO1P BIT(4)
  22. #define PMLDO1N BIT(5)
  23. #define PMLDO (PMLDO1P | PMLDO1N)
  24. #define AK4375_02_POWER_MANAGEMENT3 0x02
  25. #define AK4375_03_POWER_MANAGEMENT4 0x03
  26. #define AK4375_04_OUTPUT_MODE_SETTING 0x04
  27. #define AK4375_05_CLOCK_MODE_SELECT 0x05
  28. #define FS_MASK GENMASK(4, 0)
  29. #define FS_8KHZ 0x00
  30. #define FS_11_025KHZ 0x01
  31. #define FS_16KHZ 0x04
  32. #define FS_22_05KHZ 0x05
  33. #define FS_32KHZ 0x08
  34. #define FS_44_1KHZ 0x09
  35. #define FS_48KHZ 0x0a
  36. #define FS_88_2KHZ 0x0d
  37. #define FS_96KHZ 0x0e
  38. #define FS_176_4KHZ 0x11
  39. #define FS_192KHZ 0x12
  40. #define CM_MASK GENMASK(6, 5) /* For SRC Bypass mode */
  41. #define CM_0 (0x0 << 5)
  42. #define CM_1 (0x1 << 5)
  43. #define CM_2 (0x2 << 5)
  44. #define CM_3 (0x3 << 5)
  45. #define AK4375_06_DIGITAL_FILTER_SELECT 0x06
  46. #define DADFSEL BIT(5) /* 0: in SRC Bypass mode, 1: in SRC mode */
  47. #define DASL BIT(6)
  48. #define DASD BIT(7)
  49. #define AK4375_07_DAC_MONO_MIXING 0x07
  50. #define DACMUTE_MASK (GENMASK(5, 4) | GENMASK(1, 0)) /* Clear to mute */
  51. #define AK4375_08_JITTER_CLEANER_SETTING1 0x08
  52. #define AK4375_09_JITTER_CLEANER_SETTING2 0x09
  53. #define AK4375_0A_JITTER_CLEANER_SETTING3 0x0a
  54. #define SELDAIN BIT(1) /* 0: SRC Bypass mode, 1: SRC mode */
  55. #define XCKSEL BIT(6) /* 0: PLL0, 1: MCKI */
  56. #define XCKCPSEL BIT(7) /* Should be equal to SELDAIN and XCKSEL */
  57. #define AK4375_0B_LCH_OUTPUT_VOLUME 0x0b
  58. #define AK4375_0C_RCH_OUTPUT_VOLUME 0x0c
  59. #define AK4375_0D_HP_VOLUME_CONTROL 0x0d
  60. #define AK4375_0E_PLL_CLK_SOURCE_SELECT 0x0e
  61. #define PLS BIT(0) /* 0: MCKI, 1: BCLK */
  62. #define AK4375_0F_PLL_REF_CLK_DIVIDER1 0x0f /* Reference clock divider [15:8] bits */
  63. #define AK4375_10_PLL_REF_CLK_DIVIDER2 0x10 /* Reference clock divider [7:0] bis */
  64. #define AK4375_11_PLL_FB_CLK_DIVIDER1 0x11 /* Feedback clock divider [15:8] bits */
  65. #define AK4375_12_PLL_FB_CLK_DIVIDER2 0x12 /* Feedback clock divider [7:0] bits */
  66. #define AK4375_13_SRC_CLK_SOURCE 0x13 /* SRC Bypass: SRCCKS=XCKSEL=SELDAIN=0 */
  67. #define SRCCKS BIT(0) /* SRC Clock source 0: MCKI, 1: PLL0 */
  68. #define DIV BIT(4)
  69. #define AK4375_14_DAC_CLK_DIVIDER 0x14
  70. #define AK4375_15_AUDIO_IF_FORMAT 0x15
  71. #define DEVICEID_MASK GENMASK(7, 5)
  72. #define AK4375_24_MODE_CONTROL 0x24
  73. #define AK4375_PLL_FREQ_OUT_112896000 112896000 /* 44.1 kHz base rate */
  74. #define AK4375_PLL_FREQ_OUT_122880000 122880000 /* 32 and 48 kHz base rates */
  75. #define DEVICEID_AK4375 0x00
  76. #define DEVICEID_AK4375A 0x01
  77. #define DEVICEID_AK4376A 0x02
  78. #define DEVICEID_AK4377 0x03
  79. #define DEVICEID_AK4331 0x07
  80. static const char * const supply_names[] = {
  81. "avdd", "tvdd"
  82. };
  83. struct ak4375_drvdata {
  84. struct snd_soc_dai_driver *dai_drv;
  85. const struct snd_soc_component_driver *comp_drv;
  86. };
  87. struct ak4375_priv {
  88. struct device *dev;
  89. struct regmap *regmap;
  90. struct gpio_desc *pdn_gpiod;
  91. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  92. unsigned int rate;
  93. unsigned int pld;
  94. u8 mute_save;
  95. };
  96. static const struct reg_default ak4375_reg_defaults[] = {
  97. { 0x00, 0x00 }, { 0x01, 0x00 }, { 0x02, 0x00 },
  98. { 0x03, 0x00 }, { 0x04, 0x00 }, { 0x05, 0x00 },
  99. { 0x06, 0x00 }, { 0x07, 0x00 }, { 0x08, 0x00 },
  100. { 0x09, 0x00 }, { 0x0a, 0x00 }, { 0x0b, 0x19 },
  101. { 0x0c, 0x19 }, { 0x0d, 0x75 }, { 0x0e, 0x01 },
  102. { 0x0f, 0x00 }, { 0x10, 0x00 }, { 0x11, 0x00 },
  103. { 0x12, 0x00 }, { 0x13, 0x00 }, { 0x14, 0x00 },
  104. { 0x15, 0x00 }, { 0x24, 0x00 },
  105. };
  106. /*
  107. * Output Digital volume control:
  108. * from -12.5 to 3 dB in 0.5 dB steps (mute instead of -12.5 dB)
  109. */
  110. static DECLARE_TLV_DB_SCALE(dac_tlv, -1250, 50, 0);
  111. /*
  112. * HP-Amp Analog volume control:
  113. * from -4.2 to 6 dB in 2 dB steps (mute instead of -4.2 dB)
  114. */
  115. static DECLARE_TLV_DB_SCALE(hpg_tlv, -4200, 20, 0);
  116. static const char * const ak4375_ovolcn_select_texts[] = { "Dependent", "Independent" };
  117. static const char * const ak4375_mdac_select_texts[] = { "x1", "x1/2" };
  118. static const char * const ak4375_cpmode_select_texts[] = {
  119. "Automatic Switching",
  120. "+-VDD Operation",
  121. "+-1/2VDD Operation"
  122. };
  123. /*
  124. * DASD, DASL bits Digital Filter Setting
  125. * 0, 0 : Sharp Roll-Off Filter
  126. * 0, 1 : Slow Roll-Off Filter
  127. * 1, 0 : Short delay Sharp Roll-Off Filter
  128. * 1, 1 : Short delay Slow Roll-Off Filter
  129. */
  130. static const char * const ak4375_digfil_select_texts[] = {
  131. "Sharp Roll-Off Filter",
  132. "Slow Roll-Off Filter",
  133. "Short delay Sharp Roll-Off Filter",
  134. "Short delay Slow Roll-Off Filter",
  135. };
  136. static const struct soc_enum ak4375_ovolcn_enum =
  137. SOC_ENUM_SINGLE(AK4375_0B_LCH_OUTPUT_VOLUME, 7,
  138. ARRAY_SIZE(ak4375_ovolcn_select_texts), ak4375_ovolcn_select_texts);
  139. static const struct soc_enum ak4375_mdacl_enum =
  140. SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 2,
  141. ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
  142. static const struct soc_enum ak4375_mdacr_enum =
  143. SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 6,
  144. ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);
  145. static const struct soc_enum ak4375_cpmode_enum =
  146. SOC_ENUM_SINGLE(AK4375_03_POWER_MANAGEMENT4, 2,
  147. ARRAY_SIZE(ak4375_cpmode_select_texts), ak4375_cpmode_select_texts);
  148. static const struct soc_enum ak4375_digfil_enum =
  149. SOC_ENUM_SINGLE(AK4375_06_DIGITAL_FILTER_SELECT, 6,
  150. ARRAY_SIZE(ak4375_digfil_select_texts), ak4375_digfil_select_texts);
  151. static const struct snd_kcontrol_new ak4375_snd_controls[] = {
  152. SOC_DOUBLE_R_TLV("Digital Output Volume", AK4375_0B_LCH_OUTPUT_VOLUME,
  153. AK4375_0C_RCH_OUTPUT_VOLUME, 0, 0x1f, 0, dac_tlv),
  154. SOC_SINGLE_TLV("HP-Amp Analog Volume",
  155. AK4375_0D_HP_VOLUME_CONTROL, 0, 0x1f, 0, hpg_tlv),
  156. SOC_DOUBLE("DAC Signal Invert Switch", AK4375_07_DAC_MONO_MIXING, 3, 7, 1, 0),
  157. SOC_ENUM("Digital Volume Control", ak4375_ovolcn_enum),
  158. SOC_ENUM("DACL Signal Level", ak4375_mdacl_enum),
  159. SOC_ENUM("DACR Signal Level", ak4375_mdacr_enum),
  160. SOC_ENUM("Charge Pump Mode", ak4375_cpmode_enum),
  161. SOC_ENUM("DAC Digital Filter Mode", ak4375_digfil_enum),
  162. };
  163. static const struct snd_kcontrol_new ak4375_hpl_mixer_controls[] = {
  164. SOC_DAPM_SINGLE("LDACL Switch", AK4375_07_DAC_MONO_MIXING, 0, 1, 0),
  165. SOC_DAPM_SINGLE("RDACL Switch", AK4375_07_DAC_MONO_MIXING, 1, 1, 0),
  166. };
  167. static const struct snd_kcontrol_new ak4375_hpr_mixer_controls[] = {
  168. SOC_DAPM_SINGLE("LDACR Switch", AK4375_07_DAC_MONO_MIXING, 4, 1, 0),
  169. SOC_DAPM_SINGLE("RDACR Switch", AK4375_07_DAC_MONO_MIXING, 5, 1, 0),
  170. };
  171. static int ak4375_dac_event(struct snd_soc_dapm_widget *w,
  172. struct snd_kcontrol *kcontrol, int event)
  173. {
  174. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  175. switch (event) {
  176. case SND_SOC_DAPM_PRE_PMU:
  177. snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, PMPLL);
  178. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, PMCP1);
  179. usleep_range(6500, 7000);
  180. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, PMLDO);
  181. usleep_range(1000, 2000);
  182. break;
  183. case SND_SOC_DAPM_POST_PMU:
  184. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, PMCP2);
  185. usleep_range(4500, 5000);
  186. break;
  187. case SND_SOC_DAPM_PRE_PMD:
  188. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, 0x0);
  189. break;
  190. case SND_SOC_DAPM_POST_PMD:
  191. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, 0x0);
  192. snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, 0x0);
  193. snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, 0x0);
  194. break;
  195. }
  196. return 0;
  197. }
  198. static const struct snd_soc_dapm_widget ak4375_dapm_widgets[] = {
  199. SND_SOC_DAPM_DAC_E("DAC", NULL, AK4375_02_POWER_MANAGEMENT3, 0, 0, ak4375_dac_event,
  200. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  201. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  202. SND_SOC_DAPM_AIF_IN("SDTI", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  203. SND_SOC_DAPM_OUTPUT("HPL"),
  204. SND_SOC_DAPM_OUTPUT("HPR"),
  205. SND_SOC_DAPM_MIXER("HPR Mixer", AK4375_03_POWER_MANAGEMENT4, 1, 0,
  206. &ak4375_hpr_mixer_controls[0], ARRAY_SIZE(ak4375_hpr_mixer_controls)),
  207. SND_SOC_DAPM_MIXER("HPL Mixer", AK4375_03_POWER_MANAGEMENT4, 0, 0,
  208. &ak4375_hpl_mixer_controls[0], ARRAY_SIZE(ak4375_hpl_mixer_controls)),
  209. };
  210. static const struct snd_soc_dapm_route ak4375_intercon[] = {
  211. { "DAC", NULL, "SDTI" },
  212. { "HPL Mixer", "LDACL Switch", "DAC" },
  213. { "HPL Mixer", "RDACL Switch", "DAC" },
  214. { "HPR Mixer", "LDACR Switch", "DAC" },
  215. { "HPR Mixer", "RDACR Switch", "DAC" },
  216. { "HPL", NULL, "HPL Mixer" },
  217. { "HPR", NULL, "HPR Mixer" },
  218. };
  219. static int ak4375_hw_params(struct snd_pcm_substream *substream,
  220. struct snd_pcm_hw_params *params,
  221. struct snd_soc_dai *dai)
  222. {
  223. struct snd_soc_component *component = dai->component;
  224. struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
  225. unsigned int freq_in, freq_out;
  226. ak4375->rate = params_rate(params);
  227. if (ak4375->rate <= 96000)
  228. ak4375->pld = 0;
  229. else
  230. ak4375->pld = 1;
  231. freq_in = 32 * ak4375->rate / (ak4375->pld + 1);
  232. if ((ak4375->rate % 8000) == 0)
  233. freq_out = AK4375_PLL_FREQ_OUT_122880000;
  234. else
  235. freq_out = AK4375_PLL_FREQ_OUT_112896000;
  236. return snd_soc_dai_set_pll(dai, 0, 0, freq_in, freq_out);
  237. }
  238. static int ak4375_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
  239. unsigned int freq_in, unsigned int freq_out)
  240. {
  241. struct snd_soc_component *component = dai->component;
  242. struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
  243. unsigned int mclk, plm, mdiv, div;
  244. u8 cms, fs, cm;
  245. cms = snd_soc_component_read(component, AK4375_05_CLOCK_MODE_SELECT);
  246. fs = cms & ~FS_MASK;
  247. cm = cms & ~CM_MASK;
  248. switch (ak4375->rate) {
  249. case 8000:
  250. fs |= FS_8KHZ;
  251. break;
  252. case 11025:
  253. fs |= FS_11_025KHZ;
  254. break;
  255. case 16000:
  256. fs |= FS_16KHZ;
  257. break;
  258. case 22050:
  259. fs |= FS_22_05KHZ;
  260. break;
  261. case 32000:
  262. fs |= FS_32KHZ;
  263. break;
  264. case 44100:
  265. fs |= FS_44_1KHZ;
  266. break;
  267. case 48000:
  268. fs |= FS_48KHZ;
  269. break;
  270. case 88200:
  271. fs |= FS_88_2KHZ;
  272. break;
  273. case 96000:
  274. fs |= FS_96KHZ;
  275. break;
  276. case 176400:
  277. fs |= FS_176_4KHZ;
  278. break;
  279. case 192000:
  280. fs |= FS_192KHZ;
  281. break;
  282. default:
  283. return -EINVAL;
  284. }
  285. if (ak4375->rate <= 24000) {
  286. cm |= CM_1;
  287. mclk = 512 * ak4375->rate;
  288. mdiv = freq_out / mclk - 1;
  289. div = 0;
  290. } else if (ak4375->rate <= 96000) {
  291. cm |= CM_0;
  292. mclk = 256 * ak4375->rate;
  293. mdiv = freq_out / mclk - 1;
  294. div = 0;
  295. } else {
  296. cm |= CM_3;
  297. mclk = 128 * ak4375->rate;
  298. mdiv = 4;
  299. div = 1;
  300. }
  301. /* Writing both fields in one go seems to make playback choppy on start */
  302. snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, FS_MASK, fs);
  303. snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, CM_MASK, cm);
  304. snd_soc_component_write(component, AK4375_0F_PLL_REF_CLK_DIVIDER1,
  305. (ak4375->pld & 0xff00) >> 8);
  306. snd_soc_component_write(component, AK4375_10_PLL_REF_CLK_DIVIDER2,
  307. ak4375->pld & 0x00ff);
  308. plm = freq_out / freq_in - 1;
  309. snd_soc_component_write(component, AK4375_11_PLL_FB_CLK_DIVIDER1, (plm & 0xff00) >> 8);
  310. snd_soc_component_write(component, AK4375_12_PLL_FB_CLK_DIVIDER2, plm & 0x00ff);
  311. snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, DIV, div);
  312. /* SRCCKS bit: force to 1 for SRC PLL source clock */
  313. snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, SRCCKS, SRCCKS);
  314. snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv);
  315. dev_dbg(ak4375->dev, "rate=%d mclk=%d f_in=%d f_out=%d PLD=%d PLM=%d MDIV=%d DIV=%d\n",
  316. ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div);
  317. return 0;
  318. }
  319. static int ak4375_mute(struct snd_soc_dai *dai, int mute, int direction)
  320. {
  321. struct snd_soc_component *component = dai->component;
  322. struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);
  323. u8 val = snd_soc_component_read(component, AK4375_07_DAC_MONO_MIXING);
  324. dev_dbg(ak4375->dev, "mute=%d val=%d\n", mute, val);
  325. if (mute) {
  326. ak4375->mute_save = val & DACMUTE_MASK;
  327. val &= ~DACMUTE_MASK;
  328. } else {
  329. val |= ak4375->mute_save;
  330. }
  331. snd_soc_component_write(component, AK4375_07_DAC_MONO_MIXING, val);
  332. return 0;
  333. }
  334. #define AK4375_RATES (SNDRV_PCM_RATE_8000_48000 |\
  335. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\
  336. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  337. #define AK4375_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  338. SNDRV_PCM_FMTBIT_S24_LE |\
  339. SNDRV_PCM_FMTBIT_S32_LE)
  340. static const struct snd_soc_dai_ops ak4375_dai_ops = {
  341. .hw_params = ak4375_hw_params,
  342. .mute_stream = ak4375_mute,
  343. .set_pll = ak4375_dai_set_pll,
  344. };
  345. static struct snd_soc_dai_driver ak4375_dai = {
  346. .name = "ak4375-hifi",
  347. .playback = {
  348. .stream_name = "HiFi Playback",
  349. .channels_min = 1,
  350. .channels_max = 2,
  351. .rates = AK4375_RATES,
  352. .rate_min = 8000,
  353. .rate_max = 192000,
  354. .formats = AK4375_FORMATS,
  355. },
  356. .ops = &ak4375_dai_ops,
  357. };
  358. static void ak4375_power_off(struct ak4375_priv *ak4375)
  359. {
  360. gpiod_set_value_cansleep(ak4375->pdn_gpiod, 0);
  361. usleep_range(1000, 2000);
  362. regulator_bulk_disable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
  363. }
  364. static int ak4375_power_on(struct ak4375_priv *ak4375)
  365. {
  366. int ret;
  367. ret = regulator_bulk_enable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
  368. if (ret < 0) {
  369. dev_err(ak4375->dev, "Failed to enable regulators: %d\n", ret);
  370. return ret;
  371. }
  372. usleep_range(3000, 4000);
  373. gpiod_set_value_cansleep(ak4375->pdn_gpiod, 1);
  374. usleep_range(1000, 2000);
  375. return 0;
  376. }
  377. static int __maybe_unused ak4375_runtime_suspend(struct device *dev)
  378. {
  379. struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
  380. regcache_cache_only(ak4375->regmap, true);
  381. ak4375_power_off(ak4375);
  382. return 0;
  383. }
  384. static int __maybe_unused ak4375_runtime_resume(struct device *dev)
  385. {
  386. struct ak4375_priv *ak4375 = dev_get_drvdata(dev);
  387. int ret;
  388. ret = ak4375_power_on(ak4375);
  389. if (ret < 0)
  390. return ret;
  391. regcache_cache_only(ak4375->regmap, false);
  392. regcache_mark_dirty(ak4375->regmap);
  393. return regcache_sync(ak4375->regmap);
  394. }
  395. static const struct snd_soc_component_driver soc_codec_dev_ak4375 = {
  396. .controls = ak4375_snd_controls,
  397. .num_controls = ARRAY_SIZE(ak4375_snd_controls),
  398. .dapm_widgets = ak4375_dapm_widgets,
  399. .num_dapm_widgets = ARRAY_SIZE(ak4375_dapm_widgets),
  400. .dapm_routes = ak4375_intercon,
  401. .num_dapm_routes = ARRAY_SIZE(ak4375_intercon),
  402. .idle_bias_on = 1,
  403. .use_pmdown_time = 1,
  404. .endianness = 1,
  405. };
  406. static const struct regmap_config ak4375_regmap = {
  407. .reg_bits = 8,
  408. .val_bits = 8,
  409. .max_register = AK4375_24_MODE_CONTROL,
  410. .reg_defaults = ak4375_reg_defaults,
  411. .num_reg_defaults = ARRAY_SIZE(ak4375_reg_defaults),
  412. .cache_type = REGCACHE_RBTREE,
  413. };
  414. static const struct ak4375_drvdata ak4375_drvdata = {
  415. .dai_drv = &ak4375_dai,
  416. .comp_drv = &soc_codec_dev_ak4375,
  417. };
  418. static const struct dev_pm_ops ak4375_pm = {
  419. SET_RUNTIME_PM_OPS(ak4375_runtime_suspend, ak4375_runtime_resume, NULL)
  420. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  421. pm_runtime_force_resume)
  422. };
  423. static int ak4375_i2c_probe(struct i2c_client *i2c)
  424. {
  425. struct ak4375_priv *ak4375;
  426. const struct ak4375_drvdata *drvdata;
  427. unsigned int deviceid;
  428. int ret, i;
  429. ak4375 = devm_kzalloc(&i2c->dev, sizeof(*ak4375), GFP_KERNEL);
  430. if (!ak4375)
  431. return -ENOMEM;
  432. ak4375->regmap = devm_regmap_init_i2c(i2c, &ak4375_regmap);
  433. if (IS_ERR(ak4375->regmap))
  434. return PTR_ERR(ak4375->regmap);
  435. i2c_set_clientdata(i2c, ak4375);
  436. ak4375->dev = &i2c->dev;
  437. drvdata = of_device_get_match_data(&i2c->dev);
  438. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  439. ak4375->supplies[i].supply = supply_names[i];
  440. ret = devm_regulator_bulk_get(ak4375->dev, ARRAY_SIZE(ak4375->supplies), ak4375->supplies);
  441. if (ret < 0) {
  442. dev_err(ak4375->dev, "Failed to get regulators: %d\n", ret);
  443. return ret;
  444. }
  445. ak4375->pdn_gpiod = devm_gpiod_get_optional(ak4375->dev, "pdn", GPIOD_OUT_LOW);
  446. if (IS_ERR(ak4375->pdn_gpiod))
  447. return dev_err_probe(ak4375->dev, PTR_ERR(ak4375->pdn_gpiod),
  448. "failed to get pdn\n");
  449. ret = ak4375_power_on(ak4375);
  450. if (ret < 0)
  451. return ret;
  452. /* Don't read deviceid from cache */
  453. regcache_cache_bypass(ak4375->regmap, true);
  454. ret = regmap_read(ak4375->regmap, AK4375_15_AUDIO_IF_FORMAT, &deviceid);
  455. if (ret < 0) {
  456. dev_err(ak4375->dev, "unable to read DEVICEID!\n");
  457. return ret;
  458. }
  459. regcache_cache_bypass(ak4375->regmap, false);
  460. deviceid = (deviceid & DEVICEID_MASK) >> 5;
  461. switch (deviceid) {
  462. case DEVICEID_AK4331:
  463. dev_err(ak4375->dev, "found untested AK4331\n");
  464. return -EINVAL;
  465. case DEVICEID_AK4375:
  466. dev_dbg(ak4375->dev, "found AK4375\n");
  467. break;
  468. case DEVICEID_AK4375A:
  469. dev_dbg(ak4375->dev, "found AK4375A\n");
  470. break;
  471. case DEVICEID_AK4376A:
  472. dev_err(ak4375->dev, "found unsupported AK4376/A!\n");
  473. return -EINVAL;
  474. case DEVICEID_AK4377:
  475. dev_err(ak4375->dev, "found unsupported AK4377!\n");
  476. return -EINVAL;
  477. default:
  478. dev_err(ak4375->dev, "unrecognized DEVICEID!\n");
  479. return -EINVAL;
  480. }
  481. pm_runtime_set_active(ak4375->dev);
  482. pm_runtime_enable(ak4375->dev);
  483. ret = devm_snd_soc_register_component(ak4375->dev, drvdata->comp_drv,
  484. drvdata->dai_drv, 1);
  485. if (ret < 0) {
  486. dev_err(ak4375->dev, "Failed to register CODEC: %d\n", ret);
  487. return ret;
  488. }
  489. return 0;
  490. }
  491. static void ak4375_i2c_remove(struct i2c_client *i2c)
  492. {
  493. pm_runtime_disable(&i2c->dev);
  494. }
  495. static const struct of_device_id ak4375_of_match[] = {
  496. { .compatible = "asahi-kasei,ak4375", .data = &ak4375_drvdata },
  497. { },
  498. };
  499. MODULE_DEVICE_TABLE(of, ak4375_of_match);
  500. static struct i2c_driver ak4375_i2c_driver = {
  501. .driver = {
  502. .name = "ak4375",
  503. .pm = &ak4375_pm,
  504. .of_match_table = ak4375_of_match,
  505. },
  506. .probe_new = ak4375_i2c_probe,
  507. .remove = ak4375_i2c_remove,
  508. };
  509. module_i2c_driver(ak4375_i2c_driver);
  510. MODULE_AUTHOR("Vincent Knecht <[email protected]>");
  511. MODULE_DESCRIPTION("ASoC AK4375 DAC driver");
  512. MODULE_LICENSE("GPL");