ak4118.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ak4118.c -- Asahi Kasei ALSA Soc Audio driver
  4. *
  5. * Copyright 2018 DEVIALET
  6. */
  7. #include <linux/i2c.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of_gpio.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. #include <sound/asoundef.h>
  15. #include <sound/core.h>
  16. #include <sound/initval.h>
  17. #include <sound/soc.h>
  18. #define AK4118_REG_CLK_PWR_CTL 0x00
  19. #define AK4118_REG_FORMAT_CTL 0x01
  20. #define AK4118_REG_IO_CTL0 0x02
  21. #define AK4118_REG_IO_CTL1 0x03
  22. #define AK4118_REG_INT0_MASK 0x04
  23. #define AK4118_REG_INT1_MASK 0x05
  24. #define AK4118_REG_RCV_STATUS0 0x06
  25. #define AK4118_REG_RCV_STATUS1 0x07
  26. #define AK4118_REG_RXCHAN_STATUS0 0x08
  27. #define AK4118_REG_RXCHAN_STATUS1 0x09
  28. #define AK4118_REG_RXCHAN_STATUS2 0x0a
  29. #define AK4118_REG_RXCHAN_STATUS3 0x0b
  30. #define AK4118_REG_RXCHAN_STATUS4 0x0c
  31. #define AK4118_REG_TXCHAN_STATUS0 0x0d
  32. #define AK4118_REG_TXCHAN_STATUS1 0x0e
  33. #define AK4118_REG_TXCHAN_STATUS2 0x0f
  34. #define AK4118_REG_TXCHAN_STATUS3 0x10
  35. #define AK4118_REG_TXCHAN_STATUS4 0x11
  36. #define AK4118_REG_BURST_PREAMB_PC0 0x12
  37. #define AK4118_REG_BURST_PREAMB_PC1 0x13
  38. #define AK4118_REG_BURST_PREAMB_PD0 0x14
  39. #define AK4118_REG_BURST_PREAMB_PD1 0x15
  40. #define AK4118_REG_QSUB_CTL 0x16
  41. #define AK4118_REG_QSUB_TRACK 0x17
  42. #define AK4118_REG_QSUB_INDEX 0x18
  43. #define AK4118_REG_QSUB_MIN 0x19
  44. #define AK4118_REG_QSUB_SEC 0x1a
  45. #define AK4118_REG_QSUB_FRAME 0x1b
  46. #define AK4118_REG_QSUB_ZERO 0x1c
  47. #define AK4118_REG_QSUB_ABS_MIN 0x1d
  48. #define AK4118_REG_QSUB_ABS_SEC 0x1e
  49. #define AK4118_REG_QSUB_ABS_FRAME 0x1f
  50. #define AK4118_REG_GPE 0x20
  51. #define AK4118_REG_GPDR 0x21
  52. #define AK4118_REG_GPSCR 0x22
  53. #define AK4118_REG_GPLR 0x23
  54. #define AK4118_REG_DAT_MASK_DTS 0x24
  55. #define AK4118_REG_RX_DETECT 0x25
  56. #define AK4118_REG_STC_DAT_DETECT 0x26
  57. #define AK4118_REG_RXCHAN_STATUS5 0x27
  58. #define AK4118_REG_TXCHAN_STATUS5 0x28
  59. #define AK4118_REG_MAX 0x29
  60. #define AK4118_REG_FORMAT_CTL_DIF0 (1 << 4)
  61. #define AK4118_REG_FORMAT_CTL_DIF1 (1 << 5)
  62. #define AK4118_REG_FORMAT_CTL_DIF2 (1 << 6)
  63. struct ak4118_priv {
  64. struct regmap *regmap;
  65. struct gpio_desc *reset;
  66. struct gpio_desc *irq;
  67. struct snd_soc_component *component;
  68. };
  69. static const struct reg_default ak4118_reg_defaults[] = {
  70. {AK4118_REG_CLK_PWR_CTL, 0x43},
  71. {AK4118_REG_FORMAT_CTL, 0x6a},
  72. {AK4118_REG_IO_CTL0, 0x88},
  73. {AK4118_REG_IO_CTL1, 0x48},
  74. {AK4118_REG_INT0_MASK, 0xee},
  75. {AK4118_REG_INT1_MASK, 0xb5},
  76. {AK4118_REG_RCV_STATUS0, 0x00},
  77. {AK4118_REG_RCV_STATUS1, 0x10},
  78. {AK4118_REG_TXCHAN_STATUS0, 0x00},
  79. {AK4118_REG_TXCHAN_STATUS1, 0x00},
  80. {AK4118_REG_TXCHAN_STATUS2, 0x00},
  81. {AK4118_REG_TXCHAN_STATUS3, 0x00},
  82. {AK4118_REG_TXCHAN_STATUS4, 0x00},
  83. {AK4118_REG_GPE, 0x77},
  84. {AK4118_REG_GPDR, 0x00},
  85. {AK4118_REG_GPSCR, 0x00},
  86. {AK4118_REG_GPLR, 0x00},
  87. {AK4118_REG_DAT_MASK_DTS, 0x3f},
  88. {AK4118_REG_RX_DETECT, 0x00},
  89. {AK4118_REG_STC_DAT_DETECT, 0x00},
  90. {AK4118_REG_TXCHAN_STATUS5, 0x00},
  91. };
  92. static const char * const ak4118_input_select_txt[] = {
  93. "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7",
  94. };
  95. static SOC_ENUM_SINGLE_DECL(ak4118_insel_enum, AK4118_REG_IO_CTL1, 0x0,
  96. ak4118_input_select_txt);
  97. static const struct snd_kcontrol_new ak4118_input_mux_controls =
  98. SOC_DAPM_ENUM("Input Select", ak4118_insel_enum);
  99. static const char * const ak4118_iec958_fs_txt[] = {
  100. "44100", "48000", "32000", "22050", "11025", "24000", "16000", "88200",
  101. "8000", "96000", "64000", "176400", "192000",
  102. };
  103. static const int ak4118_iec958_fs_val[] = {
  104. 0x0, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xE,
  105. };
  106. static SOC_VALUE_ENUM_SINGLE_DECL(ak4118_iec958_fs_enum, AK4118_REG_RCV_STATUS1,
  107. 0x4, 0x4, ak4118_iec958_fs_txt,
  108. ak4118_iec958_fs_val);
  109. static struct snd_kcontrol_new ak4118_iec958_controls[] = {
  110. SOC_SINGLE("IEC958 Parity Errors", AK4118_REG_RCV_STATUS0, 0, 1, 0),
  111. SOC_SINGLE("IEC958 No Audio", AK4118_REG_RCV_STATUS0, 1, 1, 0),
  112. SOC_SINGLE("IEC958 PLL Lock", AK4118_REG_RCV_STATUS0, 4, 1, 1),
  113. SOC_SINGLE("IEC958 Non PCM", AK4118_REG_RCV_STATUS0, 6, 1, 0),
  114. SOC_ENUM("IEC958 Sampling Freq", ak4118_iec958_fs_enum),
  115. };
  116. static const struct snd_soc_dapm_widget ak4118_dapm_widgets[] = {
  117. SND_SOC_DAPM_INPUT("INRX0"),
  118. SND_SOC_DAPM_INPUT("INRX1"),
  119. SND_SOC_DAPM_INPUT("INRX2"),
  120. SND_SOC_DAPM_INPUT("INRX3"),
  121. SND_SOC_DAPM_INPUT("INRX4"),
  122. SND_SOC_DAPM_INPUT("INRX5"),
  123. SND_SOC_DAPM_INPUT("INRX6"),
  124. SND_SOC_DAPM_INPUT("INRX7"),
  125. SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
  126. &ak4118_input_mux_controls),
  127. };
  128. static const struct snd_soc_dapm_route ak4118_dapm_routes[] = {
  129. {"Input Mux", "RX0", "INRX0"},
  130. {"Input Mux", "RX1", "INRX1"},
  131. {"Input Mux", "RX2", "INRX2"},
  132. {"Input Mux", "RX3", "INRX3"},
  133. {"Input Mux", "RX4", "INRX4"},
  134. {"Input Mux", "RX5", "INRX5"},
  135. {"Input Mux", "RX6", "INRX6"},
  136. {"Input Mux", "RX7", "INRX7"},
  137. };
  138. static int ak4118_set_dai_fmt_provider(struct ak4118_priv *ak4118,
  139. unsigned int format)
  140. {
  141. int dif;
  142. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  143. case SND_SOC_DAIFMT_I2S:
  144. dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF2;
  145. break;
  146. case SND_SOC_DAIFMT_RIGHT_J:
  147. dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF1;
  148. break;
  149. case SND_SOC_DAIFMT_LEFT_J:
  150. dif = AK4118_REG_FORMAT_CTL_DIF2;
  151. break;
  152. default:
  153. return -ENOTSUPP;
  154. }
  155. return dif;
  156. }
  157. static int ak4118_set_dai_fmt_consumer(struct ak4118_priv *ak4118,
  158. unsigned int format)
  159. {
  160. int dif;
  161. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  162. case SND_SOC_DAIFMT_I2S:
  163. dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF1 |
  164. AK4118_REG_FORMAT_CTL_DIF2;
  165. break;
  166. case SND_SOC_DAIFMT_LEFT_J:
  167. dif = AK4118_REG_FORMAT_CTL_DIF1 | AK4118_REG_FORMAT_CTL_DIF2;
  168. break;
  169. default:
  170. return -ENOTSUPP;
  171. }
  172. return dif;
  173. }
  174. static int ak4118_set_dai_fmt(struct snd_soc_dai *dai,
  175. unsigned int format)
  176. {
  177. struct snd_soc_component *component = dai->component;
  178. struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
  179. int dif;
  180. int ret = 0;
  181. switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  182. case SND_SOC_DAIFMT_CBP_CFP:
  183. dif = ak4118_set_dai_fmt_provider(ak4118, format);
  184. break;
  185. case SND_SOC_DAIFMT_CBC_CFC:
  186. dif = ak4118_set_dai_fmt_consumer(ak4118, format);
  187. break;
  188. default:
  189. ret = -ENOTSUPP;
  190. goto exit;
  191. }
  192. /* format not supported */
  193. if (dif < 0) {
  194. ret = dif;
  195. goto exit;
  196. }
  197. ret = regmap_update_bits(ak4118->regmap, AK4118_REG_FORMAT_CTL,
  198. AK4118_REG_FORMAT_CTL_DIF0 |
  199. AK4118_REG_FORMAT_CTL_DIF1 |
  200. AK4118_REG_FORMAT_CTL_DIF2, dif);
  201. if (ret < 0)
  202. goto exit;
  203. exit:
  204. return ret;
  205. }
  206. static int ak4118_hw_params(struct snd_pcm_substream *substream,
  207. struct snd_pcm_hw_params *params,
  208. struct snd_soc_dai *dai)
  209. {
  210. return 0;
  211. }
  212. static const struct snd_soc_dai_ops ak4118_dai_ops = {
  213. .hw_params = ak4118_hw_params,
  214. .set_fmt = ak4118_set_dai_fmt,
  215. };
  216. static struct snd_soc_dai_driver ak4118_dai = {
  217. .name = "ak4118-hifi",
  218. .capture = {
  219. .stream_name = "Capture",
  220. .channels_min = 2,
  221. .channels_max = 2,
  222. .rates = SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
  223. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
  224. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
  225. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
  226. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  227. SNDRV_PCM_FMTBIT_S24_3LE |
  228. SNDRV_PCM_FMTBIT_S24_LE
  229. },
  230. .ops = &ak4118_dai_ops,
  231. };
  232. static irqreturn_t ak4118_irq_handler(int irq, void *data)
  233. {
  234. struct ak4118_priv *ak4118 = data;
  235. struct snd_soc_component *component = ak4118->component;
  236. struct snd_kcontrol_new *kctl_new;
  237. struct snd_kcontrol *kctl;
  238. struct snd_ctl_elem_id *id;
  239. unsigned int i;
  240. if (!component)
  241. return IRQ_NONE;
  242. for (i = 0; i < ARRAY_SIZE(ak4118_iec958_controls); i++) {
  243. kctl_new = &ak4118_iec958_controls[i];
  244. kctl = snd_soc_card_get_kcontrol(component->card,
  245. kctl_new->name);
  246. if (!kctl)
  247. continue;
  248. id = &kctl->id;
  249. snd_ctl_notify(component->card->snd_card,
  250. SNDRV_CTL_EVENT_MASK_VALUE, id);
  251. }
  252. return IRQ_HANDLED;
  253. }
  254. static int ak4118_probe(struct snd_soc_component *component)
  255. {
  256. struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
  257. int ret = 0;
  258. ak4118->component = component;
  259. /* release reset */
  260. gpiod_set_value(ak4118->reset, 0);
  261. /* unmask all int1 sources */
  262. ret = regmap_write(ak4118->regmap, AK4118_REG_INT1_MASK, 0x00);
  263. if (ret < 0) {
  264. dev_err(component->dev,
  265. "failed to write regmap 0x%x 0x%x: %d\n",
  266. AK4118_REG_INT1_MASK, 0x00, ret);
  267. return ret;
  268. }
  269. /* rx detect enable on all channels */
  270. ret = regmap_write(ak4118->regmap, AK4118_REG_RX_DETECT, 0xff);
  271. if (ret < 0) {
  272. dev_err(component->dev,
  273. "failed to write regmap 0x%x 0x%x: %d\n",
  274. AK4118_REG_RX_DETECT, 0xff, ret);
  275. return ret;
  276. }
  277. ret = snd_soc_add_component_controls(component, ak4118_iec958_controls,
  278. ARRAY_SIZE(ak4118_iec958_controls));
  279. if (ret) {
  280. dev_err(component->dev,
  281. "failed to add component kcontrols: %d\n", ret);
  282. return ret;
  283. }
  284. return 0;
  285. }
  286. static void ak4118_remove(struct snd_soc_component *component)
  287. {
  288. struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
  289. /* hold reset */
  290. gpiod_set_value(ak4118->reset, 1);
  291. }
  292. static const struct snd_soc_component_driver soc_component_drv_ak4118 = {
  293. .probe = ak4118_probe,
  294. .remove = ak4118_remove,
  295. .dapm_widgets = ak4118_dapm_widgets,
  296. .num_dapm_widgets = ARRAY_SIZE(ak4118_dapm_widgets),
  297. .dapm_routes = ak4118_dapm_routes,
  298. .num_dapm_routes = ARRAY_SIZE(ak4118_dapm_routes),
  299. .idle_bias_on = 1,
  300. .use_pmdown_time = 1,
  301. .endianness = 1,
  302. };
  303. static const struct regmap_config ak4118_regmap = {
  304. .reg_bits = 8,
  305. .val_bits = 8,
  306. .reg_defaults = ak4118_reg_defaults,
  307. .num_reg_defaults = ARRAY_SIZE(ak4118_reg_defaults),
  308. .cache_type = REGCACHE_NONE,
  309. .max_register = AK4118_REG_MAX - 1,
  310. };
  311. static int ak4118_i2c_probe(struct i2c_client *i2c)
  312. {
  313. struct ak4118_priv *ak4118;
  314. int ret;
  315. ak4118 = devm_kzalloc(&i2c->dev, sizeof(struct ak4118_priv),
  316. GFP_KERNEL);
  317. if (ak4118 == NULL)
  318. return -ENOMEM;
  319. ak4118->regmap = devm_regmap_init_i2c(i2c, &ak4118_regmap);
  320. if (IS_ERR(ak4118->regmap))
  321. return PTR_ERR(ak4118->regmap);
  322. i2c_set_clientdata(i2c, ak4118);
  323. ak4118->reset = devm_gpiod_get(&i2c->dev, "reset", GPIOD_OUT_HIGH);
  324. if (IS_ERR(ak4118->reset))
  325. return dev_err_probe(&i2c->dev, PTR_ERR(ak4118->reset),
  326. "Failed to get reset\n");
  327. ak4118->irq = devm_gpiod_get(&i2c->dev, "irq", GPIOD_IN);
  328. if (IS_ERR(ak4118->irq))
  329. return dev_err_probe(&i2c->dev, PTR_ERR(ak4118->irq),
  330. "Failed to get IRQ\n");
  331. ret = devm_request_threaded_irq(&i2c->dev, gpiod_to_irq(ak4118->irq),
  332. NULL, ak4118_irq_handler,
  333. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  334. "ak4118-irq", ak4118);
  335. if (ret < 0) {
  336. dev_err(&i2c->dev, "Fail to request_irq: %d\n", ret);
  337. return ret;
  338. }
  339. return devm_snd_soc_register_component(&i2c->dev,
  340. &soc_component_drv_ak4118, &ak4118_dai, 1);
  341. }
  342. #ifdef CONFIG_OF
  343. static const struct of_device_id ak4118_of_match[] = {
  344. { .compatible = "asahi-kasei,ak4118", },
  345. {}
  346. };
  347. MODULE_DEVICE_TABLE(of, ak4118_of_match);
  348. #endif
  349. static const struct i2c_device_id ak4118_id_table[] = {
  350. { "ak4118", 0 },
  351. {}
  352. };
  353. MODULE_DEVICE_TABLE(i2c, ak4118_id_table);
  354. static struct i2c_driver ak4118_i2c_driver = {
  355. .driver = {
  356. .name = "ak4118",
  357. .of_match_table = of_match_ptr(ak4118_of_match),
  358. },
  359. .id_table = ak4118_id_table,
  360. .probe_new = ak4118_i2c_probe,
  361. };
  362. module_i2c_driver(ak4118_i2c_driver);
  363. MODULE_DESCRIPTION("Asahi Kasei AK4118 ALSA SoC driver");
  364. MODULE_AUTHOR("Adrien Charruel <[email protected]>");
  365. MODULE_LICENSE("GPL");